FreeRTOS port on GAP8/RISC-V
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Data Structures | Macros
periph.h File Reference

Data Structures

struct  UDMA_Type
 
struct  UDMA_GC_Type
 
struct  PMU_CTRL_Type
 
struct  PORT_Type
 
struct  IO_ISO_Type
 
struct  SOCEU_Type
 
struct  PMU_DLC_Type
 
struct  EFUSE_REGS_Type
 
struct  FC_STDOUT_Type
 

Macros

#define _PMSIS_PERIPH_GAP8_H_
 
#define IRQn_Type
 
#define __MPU_PRESENT
 
#define __NVIC_PRIO_BITS
 
#define __Vendor_SysTickConfig
 
#define __FPU_PRESENT
 
#define fll(id)
 
#define gpio(id)
 
#define UDMA_BASE
 
#define UDMA_EVENTS_NUM
 
#define UDMA_CHANNEL_NUM
 
#define UDMA_GC_BASE
 
#define UDMA_GC
 
#define hyperbus(id)
 
#define uart(id)
 
#define i2c(id)
 
#define dmacpy(id)
 
#define i2s(id)
 
#define cpi(id)
 
#define soc_ctrl
 
#define SOC_CTRL_BASE
 
#define PMU_CTRL_BASE
 
#define PMU_CTRL
 
#define PMU_CTRL_BASE_ADDRS
 
#define PMU_CTRL_BASE_PTRS
 
#define GPIO_NUM
 
#define PORTA_BASE
 
#define PORTA
 
#define PORT_BASE_ADDRS
 
#define PORT_BASE_PTRS
 
#define IO_ISO_GPIO_ISO_MASK
 
#define IO_ISO_GPIO_ISO_SHIFT
 
#define IO_ISO_GPIO_ISO(x)
 
#define IO_ISO_CAM_ISO_MASK
 
#define IO_ISO_CAM_ISO_SHIFT
 
#define IO_ISO_CAM_ISO(x)
 
#define IO_ISO_LVDS_ISO_MASK
 
#define IO_ISO_LVDS_ISO_SHIFT
 
#define IO_ISO_LVDS_ISO(x)
 
#define IO_ISO_BASE
 
#define IO_ISO
 
#define IO_ISO_BASE_ADDRS
 
#define IO_ISO_BASE_PTRS
 
#define pwm(id)
 
#define pwm_ctrl
 
#define SOC_EVENTS_NUM
 
#define SOCEU_BASE
 
#define SOCEU
 
#define SOCEU_BASE_ADDRS
 
#define SOCEU_BASE_PTRS
 
#define EU_EVT_GETCLUSTERBASE(coreId)
 
#define pmu_dlc
 
#define PMU_DLC_BASE
 
#define PMU_DLC
 
#define PMU_DLC_BASE_ADDRS
 
#define PMU_DLC_BASE_PTRS
 
#define rtc(id)
 
#define EFUSE_CTRL_BASE
 
#define efuse_ctrl
 
#define EFUSE_CTRL_BASE_ADDRS
 
#define EFUSE_CTRL_BASE_PTRS
 
#define EFUSE_REGS_BASE
 
#define efuse_regs
 
#define efuse_regs_array
 
#define EFUSE_REGS_BASE_ADDRS
 
#define EFUSE_REGS_BASE_PTRS
 
#define EFUSE_REGS_BASE
 
#define EFUSE_REGS
 
#define EFUSE_REGS_BASE_ADDRS
 
#define EFUSE_REGS_BASE_PTRS
 
#define FC_STDOUT_BASE
 
#define FC_STDOUT
 
#define FC_STDOUT_BASE_ADDRS
 
#define FC_STDOUT_BASE_PTRS
 
RX_SADDR - RX TX UDMA buffer transfer address register
#define UDMA_SADDR_ADDR_MASK
 
#define UDMA_SADDR_ADDR_SHIFT
 
#define UDMA_SADDR_ADDR(x)
 
RX_SIZE - RX TX UDMA buffer transfer size register
#define UDMA_SIZE_SIZE_MASK
 
#define UDMA_SIZE_SIZE_SHIFT
 
#define UDMA_SIZE_SIZE(x)
 
RX_CFG - RX TX UDMA transfer configuration register
#define UDMA_CFG_CONTINOUS_MASK
 
#define UDMA_CFG_CONTINOUS_SHIFT
 
#define UDMA_CFG_CONTINOUS(x)
 
#define UDMA_CFG_DATA_SIZE_MASK
 
#define UDMA_CFG_DATA_SIZE_SHIFT
 
#define UDMA_CFG_DATA_SIZE(x)
 
#define UDMA_CFG_EN_MASK
 
#define UDMA_CFG_EN_SHIFT
 
#define UDMA_CFG_EN(x)
 
#define UDMA_CFG_PENDING_MASK
 
#define UDMA_CFG_PENDING_SHIFT
 
#define UDMA_CFG_PENDING(x)
 
#define UDMA_CFG_CLR_MASK
 
#define UDMA_CFG_CLR_SHIFT
 
#define UDMA_CFG_CLR(x)
 
UDMA_GC - UDMA event in register, User chooses which events can come to UDMA as reference events, support up to 4 choices
#define UDMA_GC_EVTIN_CHOICE0_MASK
 
#define UDMA_GC_EVTIN_CHOICE0_SHIFT
 
#define UDMA_GC_EVTIN_CHOICE0(x)
 
#define UDMA_GC_EVTIN_CHOICE1_MASK
 
#define UDMA_GC_EVTIN_CHOICE1_SHIFT
 
#define UDMA_GC_EVTIN_CHOICE1(x)
 
#define UDMA_GC_EVTIN_CHOICE2_MASK
 
#define UDMA_GC_EVTIN_CHOICE2_SHIFT
 
#define UDMA_GC_EVTIN_CHOICE2(x)
 
#define UDMA_GC_EVTIN_CHOICE3_MASK
 
#define UDMA_GC_EVTIN_CHOICE3_SHIFT
 
#define UDMA_GC_EVTIN_CHOICE3(x)
 
#define UDMA_GC_EVTIN_MASK(evt_in)
 
#define UDMA_GC_EVTIN_SHIFT_ID(id)
 
RAR_DCDC - PMU control register
#define PMU_CTRL_RAR_DCDC_NV_MASK
 
#define PMU_CTRL_RAR_DCDC_NV_SHIFT
 
#define PMU_CTRL_RAR_DCDC_NV(x)
 
#define READ_PMU_CTRL_RAR_DCDC_NV(x)
 
#define PMU_CTRL_RAR_DCDC_MV_MASK
 
#define PMU_CTRL_RAR_DCDC_MV_SHIFT
 
#define PMU_CTRL_RAR_DCDC_MV(x)
 
#define READ_PMU_CTRL_RAR_DCDC_MV(x)
 
#define PMU_CTRL_RAR_DCDC_LV_MASK
 
#define PMU_CTRL_RAR_DCDC_LV_SHIFT
 
#define PMU_CTRL_RAR_DCDC_LV(x)
 
#define READ_PMU_CTRL_RAR_DCDC_LV(x)
 
#define PMU_CTRL_RAR_DCDC_RV_MASK
 
#define PMU_CTRL_RAR_DCDC_RV_SHIFT
 
#define PMU_CTRL_RAR_DCDC_RV(x)
 
#define READ_PMU_CTRL_RAR_DCDC_RV(x)
 
SLEEP_CTRL - PMU control register
#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK
 
#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x)
 
#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK
 
#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET(x)
 
#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK
 
#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET(x)
 
#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK
 
#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL(x)
 
#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK
 
#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE(x)
 
#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK
 
#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN(x)
 
#define PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK
 
#define PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_WAKEUP(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_WAKEUP(x)
 
#define PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK
 
#define PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_BOOT_L2(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_BOOT_L2(x)
 
#define PMU_CTRL_SLEEP_CTRL_REBOOT_MASK
 
#define PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_REBOOT(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_REBOOT(x)
 
#define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK
 
#define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT
 
#define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP(x)
 
#define READ_PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP(x)
 
FORCE - PMU control register
#define PMU_CTRL_FORCE_MEM_RET_MASK
 
#define PMU_CTRL_FORCE_MEM_RET_SHIFT
 
#define PMU_CTRL_FORCE_MEM_RET(x)
 
#define PMU_CTRL_FORCE_MEM_PWD_MASK
 
#define PMU_CTRL_FORCE_MEM_PWD_SHIFT
 
#define PMU_CTRL_FORCE_MEM_PWD(x)
 
#define PMU_CTRL_FORCE_FLL_CLUSTER_RET_MASK
 
#define PMU_CTRL_FORCE_FLL_CLUSTER_RET_SHIFT
 
#define PMU_CTRL_FORCE_FLL_CLUSTER_RET(x)
 
#define PMU_CTRL_FORCE_FLL_CLUSTER_PWD_MASK
 
#define PMU_CTRL_FORCE_FLL_CLUSTER_PWD_SHIFT
 
#define PMU_CTRL_FORCE_FLL_CLUSTER_PWD(x)
 
PADFUN - GPIO pad mux registers
#define PORT_PADFUN_MUX_MASK
 
#define PORT_PADFUN_MUX_SHIFT
 
#define PORT_PADFUN_MUX(x)
 
PADCFG - GPIO pad configuration registers
#define PORT_PADCFG_PULL_EN_MASK
 
#define PORT_PADCFG_PULL_EN_SHIFT
 
#define PORT_PADCFG_PULL_EN(x)
 
#define PORT_PADCFG_DRIVE_STRENGTH_MASK
 
#define PORT_PADCFG_DRIVE_STRENGTH_SHIFT
 
#define PORT_PADCFG_DRIVE_STRENGTH(x)
 
PCTRL - PMU DLC PICL control register
#define PMU_DLC_PCTRL_START_MASK
 
#define PMU_DLC_PCTRL_START_SHIFT
 
#define PMU_DLC_PCTRL_START(x)
 
#define PMU_DLC_PCTRL_PADDR_MASK
 
#define PMU_DLC_PCTRL_PADDR_SHIFT
 
#define PMU_DLC_PCTRL_PADDR(x)
 
#define PMU_DLC_PCTRL_DIR_MASK
 
#define PMU_DLC_PCTRL_DIR_SHIFT
 
#define PMU_DLC_PCTRL_DIR(x)
 
#define PMU_DLC_PCTRL_PWDATA_MASK
 
#define PMU_DLC_PCTRL_PWDATA_SHIFT
 
#define PMU_DLC_PCTRL_PWDATA(x)
 
PRDATA - PMU DLC PICL data read register
#define PMU_DLC_PRDATA_PRDATA_MASK
 
#define PMU_DLC_PRDATA_PRDATA_SHIFT
 
#define PMU_DLC_PRDATA_PRDATA(x)
 
SR - PMU DLC DLC Status register
#define PMU_DLC_SR_PICL_BUSY_MASK
 
#define PMU_DLC_SR_PICL_BUSY_SHIFT
 
#define PMU_DLC_SR_PICL_BUSY(x)
 
#define PMU_DLC_SR_SCU_BUSY_MASK
 
#define PMU_DLC_SR_SCU_BUSY_SHIFT
 
#define PMU_DLC_SR_SCU_BUSY(x)
 
IMR - PMU DLC Interrupt mask register
#define PMU_DLC_IMR_ICU_OK_MASK_MASK
 
#define PMU_DLC_IMR_ICU_OK_MASK_SHIFT
 
#define PMU_DLC_IMR_ICU_OK_MASK(x)
 
#define PMU_DLC_IMR_ICU_DELAYED_MASK_MASK
 
#define PMU_DLC_IMR_ICU_DELAYED_MASK_SHIFT
 
#define PMU_DLC_IMR_ICU_DELAYED_MASK(x)
 
#define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK
 
#define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_SHIFT
 
#define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK(x)
 
#define PMU_DLC_IMR_PICL_OK_MASK_MASK
 
#define PMU_DLC_IMR_PICL_OK_MASK_SHIFT
 
#define PMU_DLC_IMR_PICL_OK_MASK(x)
 
#define PMU_DLC_IMR_SCU_OK_MASK_MASK
 
#define PMU_DLC_IMR_SCU_OK_MASK_SHIFT
 
#define PMU_DLC_IMR_SCU_OK_MASK(x)
 
IFR - PMU DLC Interrupt flag register
#define PMU_DLC_IFR_ICU_OK_FLAG_MASK
 
#define PMU_DLC_IFR_ICU_OK_FLAG_SHIFT
 
#define PMU_DLC_IFR_ICU_OK_FLAG(x)
 
#define PMU_DLC_IFR_ICU_DELAYED_FLAG_MASK
 
#define PMU_DLC_IFR_ICU_DELAYED_FLAG_SHIFT
 
#define PMU_DLC_IFR_ICU_DELAYED_FLAG(x)
 
#define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK
 
#define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_SHIFT
 
#define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG(x)
 
#define PMU_DLC_IFR_PICL_OK_FLAG_MASK
 
#define PMU_DLC_IFR_PICL_OK_FLAG_SHIFT
 
#define PMU_DLC_IFR_PICL_OK_FLAG(x)
 
#define PMU_DLC_IFR_SCU_OK_FLAG_MASK
 
#define PMU_DLC_IFR_SCU_OK_FLAG_SHIFT
 
#define PMU_DLC_IFR_SCU_OK_FLAG(x)
 
IOIFR - PMU DLC icu_ok interrupt flag register
#define PMU_DLC_IOIFR_ICU_OK_FLAG_MASK
 
#define PMU_DLC_IOIFR_ICU_OK_FLAG_SHIFT
 
#define PMU_DLC_IOIFR_ICU_OK_FLAG(x)
 
IDIFR - PMU DLC icu_delayed interrupt flag register
#define PMU_DLC_IDIFR_ICU_DELAYED_FLAG_MASK
 
#define PMU_DLC_IDIFR_ICU_DELAYED_FLAG_SHIFT
 
#define PMU_DLC_IDIFR_ICU_DELAYED_FLAG(x)
 
IMCIFR - PMU DLC icu_mode changed interrupt flag register
#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_MASK
 
#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_SHIFT
 
#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG(x)
 
PCTRL_PADDR The address to write in the DLC_PADDR register is CHIP_SEL_ADDR[4:0] concatenated with REG_ADDR[4:0].
#define PMU_DLC_PICL_REG_ADDR_MASK
 
#define PMU_DLC_PICL_REG_ADDR_SHIFT
 
#define PMU_DLC_PICL_REG_ADDR(x)
 
#define PMU_DLC_PICL_CHIP_SEL_ADDR_MASK
 
#define PMU_DLC_PICL_CHIP_SEL_ADDR_SHIFT
 
#define PMU_DLC_PICL_CHIP_SEL_ADDR(x)
 
#define PICL_WIU_ADDR
 
#define PICL_ICU_ADDR
 
INFO - EFUSE information register
#define EFUSE_INFO_PLT_MASK
 
#define EFUSE_INFO_PLT_SHIFT
 
#define EFUSE_INFO_PLT(x)
 
#define EFUSE_INFO_BOOT_MASK
 
#define EFUSE_INFO_BOOT_SHIFT
 
#define EFUSE_INFO_BOOT(x)
 
#define EFUSE_INFO_ENCRYPTED_MASK
 
#define EFUSE_INFO_ENCRYPTED_SHIFT
 
#define EFUSE_INFO_ENCRYPTED(x)
 
#define EFUSE_INFO_WAIT_XTAL_MASK
 
#define EFUSE_INFO_WAIT_XTAL_SHIFT
 
#define EFUSE_INFO_WAIT_XTAL(x)
 

Macro Definition Documentation

#define _PMSIS_PERIPH_GAP8_H_

Symbol preventing repeated inclusion

#define IRQn_Type