SOCEU_Type Struct Reference

Data Fields
__IO uint32_t	EVENT
__IO uint32_t	FC_MASK_MSB
__IO uint32_t	FC_MASK_LSB
__IO uint32_t	CL_MASK_MSB
__IO uint32_t	CL_MASK_LSB
__IO uint32_t	PR_MASK_MSB
__IO uint32_t	PR_MASK_LSB
__IO uint32_t	ERR_MASK_MSB
__IO uint32_t	ERR_MASK_LSB
__IO uint32_t	TIMER_SEL_HI
__IO uint32_t	TIMER_SEL_LO
__IO uint32_t	FC_MASK [8]
__IO uint32_t	CL_MASK [8]
__IO uint32_t	PR_MASK [8]
__IO uint32_t	ERR [8]
__IO uint32_t	TIMER1_SEL_HI
__IO uint32_t	TIMER1_SEL_LO
__IO uint32_t	TIMER2_SEL_HI
__IO uint32_t	TIMER2_SEL_LO

Description

SOCEU - Register Layout Typedef

Field Documentation

__IO uint32_t SOCEU_Type::CL_MASK[8]

SOCEU cluster mask registers, offset: 0x24

__IO uint32_t SOCEU_Type::ERR[8]

SOCEU error mask registers, offset: 0x64

__IO uint32_t SOCEU_Type::FC_MASK[8]

SOCEU fc mask registers, offset: 0x04

__IO uint32_t SOCEU_Type::PR_MASK[8]

SOCEU cluster mask registers, offset: 0x44

__IO uint32_t SOCEU_Type::TIMER1_SEL_HI

SOCEU timer 1 high register, offset: 0x84

__IO uint32_t SOCEU_Type::TIMER1_SEL_LO

SOCEU timer 1 low register, offset: 0x88

__IO uint32_t SOCEU_Type::TIMER2_SEL_HI

SOCEU timer 2 high register, offset: 0x8C

__IO uint32_t SOCEU_Type::TIMER2_SEL_LO

SOCEU timer 2 low register, offset: 0x90