Content
	EFUSE_REGS Register Masks

	FC_STDOUT Peripheral Access Layer

	SDK Compatibility

Data Structures
struct	efuse_regs_t

struct	EFUSE_REGS_Type

Macros
#define	EFUSE_REGS_BASE

#define	EFUSE_REGS

#define	EFUSE_REGS_BASE_ADDRS

#define	EFUSE_REGS_BASE_PTRS

Variables
__IO uint32_t	UDMA_Type::RX_SADDR

__IO uint32_t	UDMA_Type::RX_SIZE

__IO uint32_t	UDMA_Type::RX_CFG

__IO uint32_t	UDMA_Type::RX_INITCFG

__IO uint32_t	UDMA_Type::TX_SADDR

__IO uint32_t	UDMA_Type::TX_SIZE

__IO uint32_t	UDMA_Type::TX_CFG

__IO uint32_t	UDMA_Type::TX_INITCFG

__IO uint32_t	UDMA_GC_Type::CG

__IO uint32_t	UDMA_GC_Type::EVTIN

__IO uint32_t	PMU_CTRL_Type::RAR_DCDC

__IO uint32_t	PMU_CTRL_Type::SLEEP_CTRL

__IO uint32_t	PMU_CTRL_Type::FORCE

__IO uint32_t	PORT_Type::PADFUN [4]

__IO uint32_t	PORT_Type::SLEEP_PADCFG [4]

__IO uint32_t	PORT_Type::PAD_SLEEP

__IO uint32_t	PORT_Type::_reserved0 [7]

__IO uint32_t	PORT_Type::PADCFG [16]

__IO uint32_t	IO_ISO_Type::GPIO_ISO

__IO uint32_t	IO_ISO_Type::CAM_ISO

__IO uint32_t	IO_ISO_Type::LVDS_ISO

__IO uint32_t	SOCEU_Type::EVENT

__IO uint32_t	SOCEU_Type::FC_MASK_MSB

__IO uint32_t	SOCEU_Type::FC_MASK_LSB

__IO uint32_t	SOCEU_Type::CL_MASK_MSB

__IO uint32_t	SOCEU_Type::CL_MASK_LSB

__IO uint32_t	SOCEU_Type::PR_MASK_MSB

__IO uint32_t	SOCEU_Type::PR_MASK_LSB

__IO uint32_t	SOCEU_Type::ERR_MASK_MSB

__IO uint32_t	SOCEU_Type::ERR_MASK_LSB

__IO uint32_t	SOCEU_Type::TIMER_SEL_HI

__IO uint32_t	SOCEU_Type::TIMER_SEL_LO

__IO uint32_t	PMU_DLC_Type::PCTRL

__IO uint32_t	PMU_DLC_Type::PRDATA

__IO uint32_t	PMU_DLC_Type::DLC_SR

__IO uint32_t	PMU_DLC_Type::DLC_IMR

__IO uint32_t	PMU_DLC_Type::DLC_IFR

__IO uint32_t	PMU_DLC_Type::DLC_IOIFR

__IO uint32_t	PMU_DLC_Type::DLC_IDIFR

__IO uint32_t	PMU_DLC_Type::DLC_IMCIFR

__IO uint32_t	EFUSE_REGS_Type::INFO

__IO uint32_t	EFUSE_REGS_Type::INFO2

__IO uint32_t	EFUSE_REGS_Type::AES_KEY [16]

__IO uint32_t	EFUSE_REGS_Type::AES_IV [8]

__IO uint32_t	EFUSE_REGS_Type::WAIT_XTAL_DELTA_LSB

__IO uint32_t	EFUSE_REGS_Type::WAIT_XTAL_DELTA_MSB

__IO uint32_t	EFUSE_REGS_Type::WAIT_XTAL_MIN

__IO uint32_t	EFUSE_REGS_Type::WAIT_XTAL_MAX

__IO uint32_t	EFUSE_REGS_Type::HYPER_RDS_DELAY

__IO uint32_t	EFUSE_REGS_Type::FLL_FREQ

__IO uint32_t	EFUSE_REGS_Type::FLL_TOLERANCE

__IO uint32_t	EFUSE_REGS_Type::FLL_ASSERT_CYCLE

__IO uint32_t	EFUSE_REGS_Type::_reserved [6]

__IO uint32_t	EFUSE_REGS_Type::USER_REG [88]

__IO uint32_t	FC_STDOUT_Type::PUTC [16]

Description

Macro Definition Documentation

#define EFUSE_REGS

Peripheral EFUSE_REGS base pointer

#define EFUSE_REGS_BASE

Peripheral EFUSE_REGS base address

#define EFUSE_REGS_BASE_ADDRS

Array initializer of EFUSE_REGS base addresses

#define EFUSE_REGS_BASE_PTRS

Array initializer of EFUSE_REGS base pointers

Variable Documentation

__IO uint32_t EFUSE_REGS_Type::_reserved[6]

EFUSE_reserved registers, offset: 0x088

__IO uint32_t PORT_Type::_reserved0[7]

reserved, offset: 0x010

__IO uint32_t EFUSE_REGS_Type::AES_IV[8]

EFUSE_AES_IV registers, offset: 0x048

__IO uint32_t EFUSE_REGS_Type::AES_KEY[16]

EFUSE_AES_KEY registers, offset: 0x008

__IO uint32_t IO_ISO_Type::CAM_ISO

IO_ISO Cemera power domains isolation, offset: 0x004

__IO uint32_t UDMA_GC_Type::CG

UDMA_GC clock gating register, offset: 0x0

__IO uint32_t SOCEU_Type::CL_MASK_LSB

SOCEU cluster mask LSB register, offset: 0x10

__IO uint32_t SOCEU_Type::CL_MASK_MSB

SOCEU cluster mask MSB register, offset: 0x0C

__IO uint32_t PMU_DLC_Type::DLC_IDIFR

PMU DLC register, offset: 0x18

__IO uint32_t PMU_DLC_Type::DLC_IFR

PMU DLC register, offset: 0x10

__IO uint32_t PMU_DLC_Type::DLC_IMCIFR

PMU DLC register, offset: 0x1C

__IO uint32_t PMU_DLC_Type::DLC_IMR

PMU DLC register, offset: 0x0C

__IO uint32_t PMU_DLC_Type::DLC_IOIFR

PMU DLC register, offset: 0x14

__IO uint32_t PMU_DLC_Type::DLC_SR

PMU DLC register, offset: 0x08

__IO uint32_t SOCEU_Type::ERR_MASK_LSB

SOCEU error mask LSB register, offset: 0x20

__IO uint32_t SOCEU_Type::ERR_MASK_MSB

SOCEU error mask MSB register, offset: 0x1C

__IO uint32_t SOCEU_Type::EVENT

SOCEU event register, offset: 0x00

__IO uint32_t UDMA_GC_Type::EVTIN

UDMA_GC input event register, offset: 0x04

__IO uint32_t SOCEU_Type::FC_MASK_LSB

SOCEU fc mask LSB register, offset: 0x08

__IO uint32_t SOCEU_Type::FC_MASK_MSB

SOCEU fc mask MSB register, offset: 0x04

__IO uint32_t EFUSE_REGS_Type::FLL_ASSERT_CYCLE

EFUSE_FLL_ASSERT_CYCLE registers, offset: 0x084

__IO uint32_t EFUSE_REGS_Type::FLL_FREQ

EFUSE_FLL_FREQ registers, offset: 0x07C

__IO uint32_t EFUSE_REGS_Type::FLL_TOLERANCE

EFUSE_FLL_TOLERANCE registers, offset: 0x080

__IO uint32_t PMU_CTRL_Type::FORCE

PMU CTRL register, offset: 0x008

__IO uint32_t IO_ISO_Type::GPIO_ISO

IO_ISO GPIO power domains isolation, offset: 0x000

__IO uint32_t EFUSE_REGS_Type::HYPER_RDS_DELAY

EFUSE_WAIT_XTAL_MAX registers, offset: 0x078

__IO uint32_t EFUSE_REGS_Type::INFO

EFUSE INFO register, offset: 0x000

__IO uint32_t EFUSE_REGS_Type::INFO2

EFUSE_INFO2 register, offset: 0x004

__IO uint32_t IO_ISO_Type::LVDS_ISO

IO_ISO LVDS power domains isolation, offset: 0x008

__IO uint32_t PORT_Type::PAD_SLEEP

PORT pad sleep register, offset: 0x020

__IO uint32_t PORT_Type::PADCFG[16]

PORT pad configuration register 0, offset: 0x040

__IO uint32_t PORT_Type::PADFUN[4]

PORT pad function register 0, offset: 0x000

__IO uint32_t PMU_DLC_Type::PCTRL

PMU DLC control register, offset: 0x00

__IO uint32_t SOCEU_Type::PR_MASK_LSB

SOCEU propagate mask LSB register, offset: 0x18

__IO uint32_t SOCEU_Type::PR_MASK_MSB

SOCEU propagate mask MSB register, offset: 0x14

__IO uint32_t PMU_DLC_Type::PRDATA

PMU DLC data register, offset: 0x04

__IO uint32_t FC_STDOUT_Type::PUTC

FC_STDOUT INFO register, offset: 0x000

__IO uint32_t PMU_CTRL_Type::RAR_DCDC

PMU CTRL control register, offset: 0x000

__IO uint32_t UDMA_Type::RX_CFG

RX UDMA transfer configuration register, offset: 0x8

__IO uint32_t UDMA_Type::RX_INITCFG

Reserved, offset: 0xC

__IO uint32_t UDMA_Type::RX_SADDR

RX UDMA buffer transfer address register, offset: 0x0

__IO uint32_t UDMA_Type::RX_SIZE

RX UDMA buffer transfer size register, offset: 0x4

__IO uint32_t PMU_CTRL_Type::SLEEP_CTRL

PMU CTRL sleep control register, offset: 0x004

__IO uint32_t PORT_Type::SLEEP_PADCFG[4]

PORT sleep pad configuration register 0, offset: 0x010

__IO uint32_t SOCEU_Type::TIMER_SEL_HI

SOCEU timer high register, offset: 0x24

__IO uint32_t SOCEU_Type::TIMER_SEL_LO

SOCEU timer low register, offset: 0x28

__IO uint32_t UDMA_Type::TX_CFG

TX UDMA transfer configuration register, offset: 0x18

__IO uint32_t UDMA_Type::TX_INITCFG

Reserved, offset: 0x1C

__IO uint32_t UDMA_Type::TX_SADDR

TX UDMA buffer transfer address register, offset: 0x10

__IO uint32_t UDMA_Type::TX_SIZE

TX UDMA buffer transfer size register, offset: 0x14

__IO uint32_t EFUSE_REGS_Type::USER_REG[88]

EFUSE_USER_REG, offset: 0x0A0

__IO uint32_t EFUSE_REGS_Type::WAIT_XTAL_DELTA_LSB

EFUSE_WAIT_XTAL_DELTA_LSB register, offset: 0x068

__IO uint32_t EFUSE_REGS_Type::WAIT_XTAL_DELTA_MSB

EFUSE_WAIT_XTAL_DELTA_MSB register, offset: 0x06C

__IO uint32_t EFUSE_REGS_Type::WAIT_XTAL_MAX

EFUSE_WAIT_XTAL_MAX registers, offset: 0x074

__IO uint32_t EFUSE_REGS_Type::WAIT_XTAL_MIN

EFUSE_WAIT_XTAL_MIN registers, offset: 0x070

Content

Data Structures

Macros

Variables

Description

Macro Definition Documentation

Variable Documentation