EFUSE_REGS Register Masks

Macros
#define	EFUSE_REGS

Variables
volatile uint32_t	efuse_ctrl_t::cmd
volatile uint32_t	efuse_ctrl_t::cfg
__IO uint32_t	efuse_regs_t::info
__IO uint32_t	efuse_regs_t::info2
__IO uint32_t	efuse_regs_t::aes_key [16]
__IO uint32_t	efuse_regs_t::aes_iv [8]
__IO uint32_t	efuse_regs_t::wait_xtal_delta_lsb
__IO uint32_t	efuse_regs_t::wait_xtal_delta_msb
__IO uint32_t	efuse_regs_t::wait_xtal_min
__IO uint32_t	efuse_regs_t::wait_xtal_max
__IO uint32_t	efuse_regs_t::hyper_rds_delay
__IO uint32_t	efuse_regs_t::fll_freq
__IO uint32_t	efuse_regs_t::fll_tolerance
__IO uint32_t	efuse_regs_t::fll_assert_cycle
__IO uint32_t	efuse_regs_t::_reserved [6]
__IO uint32_t	efuse_regs_t::user_reg [88]

INFO - EFUSE information register
#define	EFUSE_INFO_PLT_MASK
#define	EFUSE_INFO_PLT_SHIFT
#define	EFUSE_INFO_PLT(x)
#define	EFUSE_INFO_BOOT_MASK
#define	EFUSE_INFO_BOOT_SHIFT
#define	EFUSE_INFO_BOOT(x)
#define	EFUSE_INFO_ENCRYPTED_MASK
#define	EFUSE_INFO_ENCRYPTED_SHIFT
#define	EFUSE_INFO_ENCRYPTED(x)
#define	EFUSE_INFO_WAIT_XTAL_MASK
#define	EFUSE_INFO_WAIT_XTAL_SHIFT
#define	EFUSE_INFO_WAIT_XTAL(x)

INFO - EFUSE information register
#define	EFUSE_INFO_PLT_MASK
#define	EFUSE_INFO_PLT_SHIFT
#define	EFUSE_INFO_PLT(x)
#define	EFUSE_INFO_BOOT_MASK
#define	EFUSE_INFO_BOOT_SHIFT
#define	EFUSE_INFO_BOOT(x)
#define	EFUSE_INFO_ENCRYPTED_MASK
#define	EFUSE_INFO_ENCRYPTED_SHIFT
#define	EFUSE_INFO_ENCRYPTED(x)
#define	EFUSE_INFO_WAIT_XTAL_MASK
#define	EFUSE_INFO_WAIT_XTAL_SHIFT
#define	EFUSE_INFO_WAIT_XTAL(x)

Description

Macro Definition Documentation

#define EFUSE_INFO_BOOT

(

x

)

#define EFUSE_INFO_BOOT

(

x

)

#define EFUSE_INFO_BOOT_MASK

#define EFUSE_INFO_BOOT_MASK

#define EFUSE_INFO_BOOT_SHIFT

#define EFUSE_INFO_BOOT_SHIFT

#define EFUSE_INFO_ENCRYPTED

(

x

)

#define EFUSE_INFO_ENCRYPTED

(

x

)

#define EFUSE_INFO_ENCRYPTED_MASK

#define EFUSE_INFO_ENCRYPTED_MASK

#define EFUSE_INFO_ENCRYPTED_SHIFT

#define EFUSE_INFO_ENCRYPTED_SHIFT

#define EFUSE_INFO_PLT

(

x

)

#define EFUSE_INFO_PLT

(

x

)

#define EFUSE_INFO_PLT_MASK

#define EFUSE_INFO_PLT_MASK

#define EFUSE_INFO_PLT_SHIFT

#define EFUSE_INFO_PLT_SHIFT

#define EFUSE_INFO_WAIT_XTAL

(

x

)

#define EFUSE_INFO_WAIT_XTAL

(

x

)

#define EFUSE_INFO_WAIT_XTAL_MASK

#define EFUSE_INFO_WAIT_XTAL_MASK

#define EFUSE_INFO_WAIT_XTAL_SHIFT

#define EFUSE_INFO_WAIT_XTAL_SHIFT

#define EFUSE_REGS

Peripheral EFUSE_REGS base pointer

Variable Documentation

__IO uint32_t efuse_regs_t::_reserved[6]

EFUSE_reserved registers, offset: 0x088

__IO uint32_t efuse_regs_t::aes_iv[8]

EFUSE_AES_IV registers, offset: 0x048

__IO uint32_t efuse_regs_t::aes_key[16]

EFUSE_AES_KEY registers, offset: 0x008

volatile uint32_t efuse_ctrl_t::cfg

EFUSE_Control register, offset: 0x04

volatile uint32_t efuse_ctrl_t::cmd

EFUSE_Control register, offset: 0x00

__IO uint32_t efuse_regs_t::fll_assert_cycle

EFUSE_FLL_ASSERT_CYCLE registers, offset: 0x084

__IO uint32_t efuse_regs_t::fll_freq

EFUSE_FLL_FREQ registers, offset: 0x07C

__IO uint32_t efuse_regs_t::fll_tolerance

EFUSE_FLL_TOLERANCE registers, offset: 0x080

__IO uint32_t efuse_regs_t::hyper_rds_delay

EFUSE_WAIT_XTAL_MAX registers, offset: 0x078

__IO uint32_t efuse_regs_t::info

EFUSE INFO register, offset: 0x000

__IO uint32_t efuse_regs_t::info2

EFUSE_INFO2 register, offset: 0x004

__IO uint32_t efuse_regs_t::user_reg[88]

EFUSE_USER_REG, offset: 0x0A0

__IO uint32_t efuse_regs_t::wait_xtal_delta_lsb

EFUSE_WAIT_XTAL_DELTA_LSB register, offset: 0x068

__IO uint32_t efuse_regs_t::wait_xtal_delta_msb

EFUSE_WAIT_XTAL_DELTA_MSB register, offset: 0x06C

__IO uint32_t efuse_regs_t::wait_xtal_max

EFUSE_WAIT_XTAL_MAX registers, offset: 0x074

__IO uint32_t efuse_regs_t::wait_xtal_min

EFUSE_WAIT_XTAL_MIN registers, offset: 0x070