GVSOC is functionally equivalent to the real chip. The compiled code that can run on the chip will also run as it is on the simulator.
To properly profile applications, it contains timing models to properly report performance within an error rate of below 20%.
We are also currently adding power models to report power consumption, also within an error rate below 20%.
The speed of the simulator is not sacrificed. Thanks to a good trade-off between accuracy and speed, it can still simulate at around 20 million instructions per second, about 10 times less speed than the actual chip.
Power features, frequency domains and power islands are modelled too and impact the timing and power consumption measurements.
Debug traces can also be activated to help in debugging applications. For example, DMA activity or core instruction traces can be generated.
To allow full applications to be simulated, a set of common devices that you can plug to our boards like cameras, microphones and flash are also simulated.
Now let’s see how to use it.