FreeRTOS port on GAP8/RISC-V
|
Macros | |
#define | PI_PMU_DLC_PCTRL_ADDR_CHIP_SEL_MASK |
#define | PI_PMU_DLC_PCTRL_ADDR_CHIP_SEL_SHIFT |
#define | PI_PMU_DLC_PCTRL_ADDR_CHIP_SEL(x) |
#define | PI_PMU_DLC_PCTRL_ADDR_REG_MASK |
#define | PI_PMU_DLC_PCTRL_ADDR_REG_SHIFT |
#define | PI_PMU_DLC_PCTRL_ADDR_REG(x) |
#define | PICL_ADDR_WIU |
#define | PICL_ADDR_ICU |
#define | WIU_ISPMR_0 |
#define | WIU_ISPMR_1 |
#define | WIU_IFR_0 |
#define | WIU_IFR_1 |
#define | WIU_ICR_0 |
#define | WIU_ICR_1 |
#define | WIU_ICR_2 |
#define | WIU_ICR_3 |
#define | WIU_ICR_4 |
#define | WIU_ICR_5 |
#define | WIU_ICR_6 |
#define | WIU_ICR_7 |
#define | WIU_ICR_8 |
#define | WIU_ICR_9 |
#define | WIU_ICR_10 |
#define | WIU_ICR_11 |
#define | WIU_ICR_12 |
#define | WIU_ICR_13 |
#define | WIU_ICR_14 |
#define | WIU_ICR_15 |
#define | ICU_CR |
#define | ICU_MR |
#define | ICU_ISMR |
#define | ICU_DMR_0 |
#define | ICU_DMA_1 |
Functions | |
static void | pmu_dlc_dlc_pctrl_set (uint32_t value) |
static uint32_t | pmu_dlc_dlc_pctrl_get (void) |
static uint32_t | pmu_dlc_dlc_prdata_get (void) |
static uint32_t | pmu_dlc_dlc_sr_get (void) |
static void | pmu_dlc_dlc_imr_set (uint32_t value) |
static uint32_t | pmu_dlc_dlc_imr_get (void) |
static void | pmu_dlc_dlc_ifr_set (uint32_t value) |
static uint32_t | pmu_dlc_dlc_ifr_get (void) |
static void | pmu_dlc_dlc_ioifr_set (uint32_t value) |
static uint32_t | pmu_dlc_dlc_ioifr_get (void) |
static void | pmu_dlc_dlc_idifr_set (uint32_t value) |
static uint32_t | pmu_dlc_dlc_idifr_get (void) |
static void | pmu_dlc_dlc_imcifr_set (uint32_t value) |
static uint32_t | pmu_dlc_dlc_imcifr_get (void) |
static void | hal_pmu_dlc_pctrl_set (uint16_t paddr, uint8_t is_read, uint16_t pwdata) |
static uint8_t | hal_pmu_dlc_pctrl_busy_get (void) |
static uint32_t | hal_pmu_dlc_prdata_get (void) |
static uint32_t | hal_pmu_dlc_status_get (void) |
static uint8_t | hal_pmu_dlc_picl_busy_get (void) |
static uint8_t | hal_pmu_dlc_scu_busy_get (void) |
static uint32_t | hal_pmu_dlc_imr_mask_get (void) |
static void | hal_pmu_dlc_imr_mask_set (uint32_t mask) |
static uint32_t | hal_pmu_dlc_ifr_get (void) |
static void | hal_pmu_dlc_ifr_mask_clear (uint32_t mask) |
static uint32_t | hal_pmu_dlc_ioifr_get (void) |
static uint32_t | hal_pmu_dlc_idifr_get (void) |
static uint32_t | hal_pmu_dlc_imcifr_get (void) |
#define ICU_CR |
#define ICU_DMA_1 |
#define ICU_DMR_0 |
#define ICU_ISMR |
#define ICU_MR |
#define PI_PMU_DLC_PCTRL_ADDR_CHIP_SEL | ( | x | ) |
#define PI_PMU_DLC_PCTRL_ADDR_CHIP_SEL_MASK |
addr[9:0] = [CHIP_SEL_ADDR[4:0] | REG_ADDR[4:0]] DLC_PCTRL.addr = addr
#define PI_PMU_DLC_PCTRL_ADDR_CHIP_SEL_SHIFT |
#define PI_PMU_DLC_PCTRL_ADDR_REG | ( | x | ) |
#define PI_PMU_DLC_PCTRL_ADDR_REG_MASK |
#define PI_PMU_DLC_PCTRL_ADDR_REG_SHIFT |
#define PICL_ADDR_ICU |
#define PICL_ADDR_WIU |
#define WIU_ICR_0 |
#define WIU_ICR_1 |
#define WIU_ICR_10 |
#define WIU_ICR_11 |
#define WIU_ICR_12 |
#define WIU_ICR_13 |
#define WIU_ICR_14 |
#define WIU_ICR_15 |
#define WIU_ICR_2 |
#define WIU_ICR_3 |
#define WIU_ICR_4 |
#define WIU_ICR_5 |
#define WIU_ICR_6 |
#define WIU_ICR_7 |
#define WIU_ICR_8 |
#define WIU_ICR_9 |
#define WIU_IFR_0 |
#define WIU_IFR_1 |
Referenced by __pi_pmu_regulator_state_change().
#define WIU_ISPMR_0 |
#define WIU_ISPMR_1 |
|
inlinestatic |
References pmu_dlc.
Referenced by __pi_pmu_regulator_state_change().
|
inlinestatic |
|
inlinestatic |
References pmu_dlc_dlc_ifr_set().
Referenced by __pi_pmu_init(), and __pi_pmu_regulator_state_change().
|
inlinestatic |
References pmu_dlc.
Referenced by __pi_pmu_regulator_state_change().
|
inlinestatic |
DLC_IMR.
References pmu_dlc_dlc_imr_get().
|
inlinestatic |
References pmu_dlc_dlc_imr_set().
Referenced by __pi_pmu_init().
|
inlinestatic |
References pmu_dlc.
Referenced by __pi_pmu_regulator_state_change().
|
inlinestatic |
|
inlinestatic |
DLC_PCTRL.
References PMU_DLC_DLC_PCTRL_DIR, PMU_DLC_DLC_PCTRL_PADDR, PMU_DLC_DLC_PCTRL_PWDATA, pmu_dlc_dlc_pctrl_set(), and PMU_DLC_DLC_PCTRL_START.
Referenced by __pi_pmu_regulator_state_change().
|
inlinestatic |
References pmu_dlc_dlc_sr_get(), PMU_DLC_DLC_SR_PICL_BUSY_MASK, and PMU_DLC_DLC_SR_PICL_BUSY_SHIFT.
|
inlinestatic |
DLC_PRDATA.
References pmu_dlc_dlc_prdata_get().
|
inlinestatic |
References pmu_dlc_dlc_sr_get(), PMU_DLC_DLC_SR_SCU_BUSY_MASK, and PMU_DLC_DLC_SR_SCU_BUSY_SHIFT.
|
inlinestatic |
DLC_SR.
References pmu_dlc_dlc_sr_get().
|
inlinestatic |
References hal_read32(), and pmu_dlc.
|
inlinestatic |
DLC_IDIFR register.
References hal_write32(), and pmu_dlc.
|
inlinestatic |
References hal_read32(), and pmu_dlc.
Referenced by hal_pmu_dlc_ifr_get().
|
inlinestatic |
DLC_IFR register.
References hal_write32(), and pmu_dlc.
Referenced by hal_pmu_dlc_ifr_mask_clear().
|
inlinestatic |
References hal_read32(), and pmu_dlc.
|
inlinestatic |
DLC_IMCIFR register.
References hal_write32(), and pmu_dlc.
|
inlinestatic |
References hal_read32(), and pmu_dlc.
Referenced by hal_pmu_dlc_imr_mask_get().
|
inlinestatic |
|
inlinestatic |
References hal_read32(), and pmu_dlc.
|
inlinestatic |
DLC_IOIFR register.
References hal_write32(), and pmu_dlc.
|
inlinestatic |
References hal_read32(), and pmu_dlc.
Referenced by hal_pmu_dlc_pctrl_busy_get().
|
inlinestatic |
|
inlinestatic |
|
inlinestatic |
DLC_SR register.
References hal_read32(), and pmu_dlc.
Referenced by hal_pmu_dlc_picl_busy_get(), hal_pmu_dlc_scu_busy_get(), and hal_pmu_dlc_status_get().