pmu_dlc_periph.h File Reference

Data Structures
struct	pmu_dlc_t
union	pmu_dlc_dlc_pctrl_t
union	pmu_dlc_dlc_prdata_t
union	pmu_dlc_dlc_sr_t
union	pmu_dlc_dlc_imr_t
union	pmu_dlc_dlc_ifr_t
union	pmu_dlc_dlc_ioifr_t
union	pmu_dlc_dlc_idifr_t
union	pmu_dlc_dlc_imcifr_t

Macros
DLC_PCTRL
#define	PMU_DLC_DLC_PCTRL_PWDATA_MASK
#define	PMU_DLC_DLC_PCTRL_PWDATA_SHIFT
#define	PMU_DLC_DLC_PCTRL_PWDATA(val)
#define	PMU_DLC_DLC_PCTRL_DIR_MASK
#define	PMU_DLC_DLC_PCTRL_DIR_SHIFT
#define	PMU_DLC_DLC_PCTRL_DIR(val)
#define	PMU_DLC_DLC_PCTRL_PADDR_MASK
#define	PMU_DLC_DLC_PCTRL_PADDR_SHIFT
#define	PMU_DLC_DLC_PCTRL_PADDR(val)
#define	PMU_DLC_DLC_PCTRL_START_MASK
#define	PMU_DLC_DLC_PCTRL_START_SHIFT
#define	PMU_DLC_DLC_PCTRL_START(val)
DLC_PRDATA
#define	PMU_DLC_DLC_PRDATA_PRDATA_MASK
#define	PMU_DLC_DLC_PRDATA_PRDATA_SHIFT
#define	PMU_DLC_DLC_PRDATA_PRDATA(val)
DLC_SR
#define	PMU_DLC_DLC_SR_SCU_BUSY_MASK
#define	PMU_DLC_DLC_SR_SCU_BUSY_SHIFT
#define	PMU_DLC_DLC_SR_SCU_BUSY(val)
#define	PMU_DLC_DLC_SR_PICL_BUSY_MASK
#define	PMU_DLC_DLC_SR_PICL_BUSY_SHIFT
#define	PMU_DLC_DLC_SR_PICL_BUSY(val)
DLC_IMR
#define	PMU_DLC_DLC_IMR_SCU_OK_MASK
#define	PMU_DLC_DLC_IMR_SCU_OK_SHIFT
#define	PMU_DLC_DLC_IMR_SCU_OK(val)
#define	PMU_DLC_DLC_IMR_PICL_OK_MASK
#define	PMU_DLC_DLC_IMR_PICL_OK_SHIFT
#define	PMU_DLC_DLC_IMR_PICL_OK(val)
#define	PMU_DLC_DLC_IMR_ICU_MD_CHG_MASK
#define	PMU_DLC_DLC_IMR_ICU_MD_CHG_SHIFT
#define	PMU_DLC_DLC_IMR_ICU_MD_CHG(val)
#define	PMU_DLC_DLC_IMR_ICU_DLYD_MASK
#define	PMU_DLC_DLC_IMR_ICU_DLYD_SHIFT
#define	PMU_DLC_DLC_IMR_ICU_DLYD(val)
#define	PMU_DLC_DLC_IMR_ICU_OK_MASK
#define	PMU_DLC_DLC_IMR_ICU_OK_SHIFT
#define	PMU_DLC_DLC_IMR_ICU_OK(val)
DLC_IFR
#define	PMU_DLC_DLC_IFR_SCU_OK_MASK
#define	PMU_DLC_DLC_IFR_SCU_OK_SHIFT
#define	PMU_DLC_DLC_IFR_SCU_OK(val)
#define	PMU_DLC_DLC_IFR_PICL_OK_MASK
#define	PMU_DLC_DLC_IFR_PICL_OK_SHIFT
#define	PMU_DLC_DLC_IFR_PICL_OK(val)
#define	PMU_DLC_DLC_IFR_ICU_MD_CHG_MASK
#define	PMU_DLC_DLC_IFR_ICU_MD_CHG_SHIFT
#define	PMU_DLC_DLC_IFR_ICU_MD_CHG(val)
#define	PMU_DLC_DLC_IFR_ICU_DLYD_MASK
#define	PMU_DLC_DLC_IFR_ICU_DLYD_SHIFT
#define	PMU_DLC_DLC_IFR_ICU_DLYD(val)
#define	PMU_DLC_DLC_IFR_ICU_OK_MASK
#define	PMU_DLC_DLC_IFR_ICU_OK_SHIFT
#define	PMU_DLC_DLC_IFR_ICU_OK(val)
DLC_IOIFR
#define	PMU_DLC_DLC_IOIFR_ICU_OK_FLGS_MASK
#define	PMU_DLC_DLC_IOIFR_ICU_OK_FLGS_SHIFT
#define	PMU_DLC_DLC_IOIFR_ICU_OK_FLGS(val)
DLC_IDIFR
#define	PMU_DLC_DLC_IDIFR_ICU_DLYD_FLGS_MASK
#define	PMU_DLC_DLC_IDIFR_ICU_DLYD_FLGS_SHIFT
#define	PMU_DLC_DLC_IDIFR_ICU_DLYD_FLGS(val)
DLC_IMCIFR
#define	PMU_DLC_DLC_IMCIFR_ICU_MD_CHNG_FLGS_MASK
#define	PMU_DLC_DLC_IMCIFR_ICU_MD_CHNG_FLGS_SHIFT
#define	PMU_DLC_DLC_IMCIFR_ICU_MD_CHNG_FLGS(val)

Macro Definition Documentation

#define PMU_DLC_DLC_IDIFR_ICU_DLYD_FLGS

(

val

)

#define PMU_DLC_DLC_IDIFR_ICU_DLYD_FLGS_MASK

#define PMU_DLC_DLC_IDIFR_ICU_DLYD_FLGS_SHIFT

#define PMU_DLC_DLC_IFR_ICU_DLYD

(

val

)

#define PMU_DLC_DLC_IFR_ICU_DLYD_MASK

#define PMU_DLC_DLC_IFR_ICU_DLYD_SHIFT

#define PMU_DLC_DLC_IFR_ICU_MD_CHG

(

val

)

#define PMU_DLC_DLC_IFR_ICU_MD_CHG_MASK

#define PMU_DLC_DLC_IFR_ICU_MD_CHG_SHIFT

#define PMU_DLC_DLC_IFR_ICU_OK

(

val

)

#define PMU_DLC_DLC_IFR_ICU_OK_MASK

#define PMU_DLC_DLC_IFR_ICU_OK_SHIFT

#define PMU_DLC_DLC_IFR_PICL_OK

(

val

)

#define PMU_DLC_DLC_IFR_PICL_OK_MASK

Referenced by __pi_pmu_init().

#define PMU_DLC_DLC_IFR_PICL_OK_SHIFT

#define PMU_DLC_DLC_IFR_SCU_OK

(

val

)

#define PMU_DLC_DLC_IFR_SCU_OK_MASK

Referenced by __pi_pmu_init().

#define PMU_DLC_DLC_IFR_SCU_OK_SHIFT

#define PMU_DLC_DLC_IMCIFR_ICU_MD_CHNG_FLGS

(

val

)

#define PMU_DLC_DLC_IMCIFR_ICU_MD_CHNG_FLGS_MASK

#define PMU_DLC_DLC_IMCIFR_ICU_MD_CHNG_FLGS_SHIFT

#define PMU_DLC_DLC_IMR_ICU_DLYD

(

val

)

#define PMU_DLC_DLC_IMR_ICU_DLYD_MASK

Referenced by __pi_pmu_init().

#define PMU_DLC_DLC_IMR_ICU_DLYD_SHIFT

#define PMU_DLC_DLC_IMR_ICU_MD_CHG

(

val

)

#define PMU_DLC_DLC_IMR_ICU_MD_CHG_MASK

Referenced by __pi_pmu_init().

#define PMU_DLC_DLC_IMR_ICU_MD_CHG_SHIFT

#define PMU_DLC_DLC_IMR_ICU_OK

(

val

)

#define PMU_DLC_DLC_IMR_ICU_OK_MASK

Referenced by __pi_pmu_init().

#define PMU_DLC_DLC_IMR_ICU_OK_SHIFT

#define PMU_DLC_DLC_IMR_PICL_OK

(

val

)

#define PMU_DLC_DLC_IMR_PICL_OK_MASK

#define PMU_DLC_DLC_IMR_PICL_OK_SHIFT

#define PMU_DLC_DLC_IMR_SCU_OK

(

val

)

#define PMU_DLC_DLC_IMR_SCU_OK_MASK

#define PMU_DLC_DLC_IMR_SCU_OK_SHIFT

#define PMU_DLC_DLC_IOIFR_ICU_OK_FLGS

(

val

)

#define PMU_DLC_DLC_IOIFR_ICU_OK_FLGS_MASK

#define PMU_DLC_DLC_IOIFR_ICU_OK_FLGS_SHIFT

#define PMU_DLC_DLC_PCTRL_DIR

(

val

)

Referenced by __pi_pmu_regulator_state_change(), and hal_pmu_dlc_pctrl_set().

#define PMU_DLC_DLC_PCTRL_DIR_MASK

#define PMU_DLC_DLC_PCTRL_DIR_SHIFT

#define PMU_DLC_DLC_PCTRL_PADDR

(

val

)

Referenced by __pi_pmu_regulator_state_change(), and hal_pmu_dlc_pctrl_set().

#define PMU_DLC_DLC_PCTRL_PADDR_MASK

#define PMU_DLC_DLC_PCTRL_PADDR_SHIFT

#define PMU_DLC_DLC_PCTRL_PWDATA

(

val

)

Referenced by __pi_pmu_regulator_state_change(), and hal_pmu_dlc_pctrl_set().

#define PMU_DLC_DLC_PCTRL_PWDATA_MASK

#define PMU_DLC_DLC_PCTRL_PWDATA_SHIFT

#define PMU_DLC_DLC_PCTRL_START

(

val

)

Referenced by __pi_pmu_regulator_state_change(), and hal_pmu_dlc_pctrl_set().

#define PMU_DLC_DLC_PCTRL_START_MASK

#define PMU_DLC_DLC_PCTRL_START_SHIFT

#define PMU_DLC_DLC_PRDATA_PRDATA

(

val

)

#define PMU_DLC_DLC_PRDATA_PRDATA_MASK

#define PMU_DLC_DLC_PRDATA_PRDATA_SHIFT

#define PMU_DLC_DLC_SR_PICL_BUSY

(

val

)

#define PMU_DLC_DLC_SR_PICL_BUSY_MASK

Referenced by hal_pmu_dlc_picl_busy_get().

#define PMU_DLC_DLC_SR_PICL_BUSY_SHIFT

Referenced by hal_pmu_dlc_picl_busy_get().

#define PMU_DLC_DLC_SR_SCU_BUSY

(

val

)

#define PMU_DLC_DLC_SR_SCU_BUSY_MASK

Referenced by hal_pmu_dlc_scu_busy_get().

#define PMU_DLC_DLC_SR_SCU_BUSY_SHIFT

Referenced by hal_pmu_dlc_scu_busy_get().