FreeRTOS port on GAP8/RISC-V
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Data Structures | Macros
gap9_periph.h File Reference

Data Structures

struct  SOCEU_Type
 
struct  FC_ICACHE_Type
 
struct  FC_STDOUT_Type
 

Macros

#define __MPU_PRESENT
 
#define __NVIC_PRIO_BITS
 
#define __FPU_PRESENT
 
#define fll(id)
 
#define gpio(id)
 
#define udma_ctrl
 
#define udma_core_lin(id)
 
#define udma_core_2d(id)
 
#define udma_core_fifo(id)
 
#define udma_spim(id)
 
#define udma_uart(id)
 
#define udma_i2c(id)
 
#define udma_hyper(id)
 
#define udma_sdio(id)
 
#define udma_i2s(id)
 
#define udma_aes(id)
 
#define udma_asrc(id)
 
#define udma_cpi(id)
 
#define udma_timestamp(id)
 
#define udma_ffc(id)
 
#define udma_mram(id)
 
#define soc_ctrl
 
#define apb_soc_ctrl
 
#define SOC_CTRL_OFFSET
 
#define SOC_CTRL_BASE
 
#define SOC_CTRL
 
#define SOC_CTRL_BASE_ADDRS
 
#define SOC_CTRL_BASE_PTRS
 
#define fc_timer(id)
 
#define SOC_EVENTS_REG_NUM
 
#define SOCEU_TIMER_SEL_ENABLE_SHIFT
 
#define SOCEU_TIMER_SEL_EVT_SHIFT
 
#define SOCEU_TIMER_SEL_EVT_MASK
 
#define SOCEU_TIMER_SEL_ENABLE_DIS
 
#define SOCEU_TIMER_SEL_ENABLE_ENA
 
#define SOCEU_TIMER_SEL_EVT_VAL(val)
 
#define SOCEU_OFFSET
 
#define SOCEU_BASE
 
#define SOCEU
 
#define SOCEU_BASE_ADDRS
 
#define SOCEU_BASE_PTRS
 
#define EU_EVT_GETCLUSTERBASE(coreId)
 
#define pmu(id)
 
#define pwm(id)
 
#define rtc(id)
 
#define FC_ICACHE_BASE
 
#define FC_ICACHE
 
#define FC_ICACHE_BASE_ADDRS
 
#define FC_ICACHE_BASE_PTRS
 
#define fc_itc
 
#define FC_STDOUT_BASE
 
#define FC_STDOUT
 
#define FC_STDOUT_BASE_ADDRS
 
#define FC_STDOUT_BASE_PTRS
 
#define quiddikey(id)
 

Macro Definition Documentation

#define __FPU_PRESENT

Defines if an FPU is present or not

#define __MPU_PRESENT

Defines if an MPU is present or not

#define __NVIC_PRIO_BITS

Number of priority bits implemented in the NVIC

#define apb_soc_ctrl

Referenced by hal_pad_drive_strength_set(), hal_pad_pad_function_set(), hal_pad_padcfg_config_get(), hal_pad_padcfg_config_set(), hal_pad_padfunc_get(), hal_pad_padfunc_set(), hal_pad_pull_set(), hal_soc_ctrl_corestatus_get(), and hal_soc_ctrl_corestatus_set().

#define EU_EVT_GETCLUSTERBASE (   coreId)
#define fc_itc

Referenced by __attribute__(), hal_itc_ack_clear(), hal_itc_ack_get(), hal_itc_ack_set(), hal_itc_event_fifo_pop(), hal_itc_irq_all_clear(), hal_itc_irq_clear(), hal_itc_irq_get(), hal_itc_irq_set(), hal_itc_irq_status_set(), hal_itc_mask_all_clear(), hal_itc_mask_clear(), hal_itc_mask_get(), hal_itc_mask_set(), and hal_itc_reset().

#define FC_STDOUT

Peripheral FC_STDOUT base pointer

#define FC_STDOUT_BASE

Peripheral FC_STDOUT base address

#define FC_STDOUT_BASE_ADDRS

Array initializer of FC_STDOUT base addresses

#define FC_STDOUT_BASE_PTRS

Array initializer of FC_STDOUT base pointers

#define fc_timer (   id)
#define fll (   id)
#define gpio (   id)
#define pmu (   id)

Referenced by hal_pmu_irq_flag_clear(), hal_pmu_irq_mask_clear(), hal_pmu_irq_mask_set(), and hal_pmu_sequence_set().

#define pwm (   id)
#define quiddikey (   id)
#define rtc (   id)
#define soc_ctrl
#define SOC_CTRL

Peripheral SOC_CTRL base pointer

#define SOC_CTRL_BASE
#define SOC_CTRL_BASE_ADDRS

Array initializer of SOC_CTRL base addresses

#define SOC_CTRL_BASE_PTRS

Array initializer of SOC_CTRL base pointers

#define SOC_CTRL_OFFSET

Peripheral SOC_CTRL base address

#define SOC_EVENTS_REG_NUM

Referenced by hal_soc_eu_reset_cl_mask(), hal_soc_eu_reset_fc_mask(), and hal_soc_eu_reset_pr_mask().

#define SOCEU

Peripheral SOCEU base pointer

#define SOCEU_BASE
#define SOCEU_BASE_ADDRS

Array initializer of SOCEU base addresses

#define SOCEU_BASE_PTRS

Array initializer of SOCEU base pointers

#define SOCEU_OFFSET

Peripheral SOCEU base address

#define SOCEU_TIMER_SEL_ENABLE_DIS
#define SOCEU_TIMER_SEL_ENABLE_ENA
#define SOCEU_TIMER_SEL_ENABLE_SHIFT

Referenced by hal_soc_eu_enable_timer().

#define SOCEU_TIMER_SEL_EVT_MASK

Referenced by hal_soc_eu_sel_timer().

#define SOCEU_TIMER_SEL_EVT_SHIFT

Referenced by hal_soc_eu_sel_timer().

#define SOCEU_TIMER_SEL_EVT_VAL (   val)
#define udma_aes (   id)

Referenced by __pi_aes_conf_apply(), and __pi_aes_crypt_start().

#define udma_asrc (   id)

Referenced by __pi_asrc_open(), hal_udma_asrc_ctrl_cfg_disable(), hal_udma_asrc_ctrl_cfg_enable(), hal_udma_asrc_ctrl_cfg_get(), hal_udma_asrc_ctrl_cfg_set(), hal_udma_asrc_lane_cfg_disable(), hal_udma_asrc_lane_cfg_enable(), hal_udma_asrc_lane_cfg_get(), and hal_udma_asrc_lane_cfg_set().

#define udma_core_2d (   id)

Referenced by hal_udma_core_2d_get().

#define udma_core_fifo (   id)

Referenced by hal_udma_core_fifo_get().

#define udma_core_lin (   id)

Referenced by hal_udma_core_lin_get().

#define udma_cpi (   id)

Referenced by hal_cpi_format_set(), hal_cpi_framedrop_set(), hal_cpi_frameslice_set(), hal_cpi_global_config_set(), hal_cpi_global_enable_set(), hal_cpi_ll_set(), hal_cpi_rgb_sequence_set(), hal_cpi_rowlen_set(), hal_cpi_rx_datasize_set(), hal_cpi_rx_dest_set(), hal_cpi_sync_polarity_set(), and hal_cpi_ur_set().

#define udma_ctrl

Referenced by __pi_asrc_open(), __pi_hyper_open(), __pi_i2s_open(), __pi_octospi_open(), __pi_uart_open(), hal_udma_ctrl_cg_disable(), hal_udma_ctrl_cg_enable(), hal_udma_ctrl_cg_get(), hal_udma_ctrl_reset_clear(), hal_udma_ctrl_reset_set(), hal_udma_ctrl_timeout_mode_set(), hal_udma_ctrl_timeout_prescaler_enabled(), hal_udma_ctrl_timeout_prescaler_reset(), hal_udma_ctrl_timeout_prescaler_set(), hal_udma_ctrl_timeout_timeout_set(), hal_udma_ctrl_timeout_timeout_start(), and hal_udma_ctrl_timeout_timeout_stop().

#define udma_ffc (   id)

Referenced by __pi_ffc_conf_apply(), __pi_ffc_conversion_start(), and __pi_ffc_event_handler().

#define udma_hyper (   id)

Referenced by __pi_hyper_copy_2d_exec(), __pi_hyper_open(), __pi_hyper_settings(), __pi_octospi_device_settings_set(), __pi_octospi_open(), __pi_octospi_ospi_config_set(), hal_udma_hyperbus_burst_cfg_set(), hal_udma_hyperbus_burst_disable(), hal_udma_hyperbus_burst_enable(), hal_udma_hyperbus_clk_div_set(), hal_udma_hyperbus_device_type_set(), hal_udma_hyperbus_ext_addr_set(), hal_udma_hyperbus_irq_disable(), hal_udma_hyperbus_irq_enable(), hal_udma_hyperbus_line_2d_set(), hal_udma_hyperbus_mba0_set(), hal_udma_hyperbus_mba1_set(), hal_udma_hyperbus_ospi_alter_set(), hal_udma_hyperbus_ospi_alter_xip_set(), hal_udma_hyperbus_ospi_cfg_mask_set(), hal_udma_hyperbus_ospi_cfg_mask_xip_set(), hal_udma_hyperbus_ospi_cfg_set(), hal_udma_hyperbus_ospi_cfg_xip_set(), hal_udma_hyperbus_ospi_cmd_set(), hal_udma_hyperbus_ospi_cmd_xip_set(), hal_udma_hyperbus_ospi_csn_get(), hal_udma_hyperbus_ospi_csn_mask_set(), hal_udma_hyperbus_ospi_csn_set(), hal_udma_hyperbus_ospi_jedec_reset_set(), hal_udma_hyperbus_ospi_ram_opt_get(), hal_udma_hyperbus_ospi_ram_opt_mask_set(), hal_udma_hyperbus_ospi_ram_opt_set(), hal_udma_hyperbus_rx_dest_get(), hal_udma_hyperbus_rx_dest_set(), hal_udma_hyperbus_status_get(), hal_udma_hyperbus_stride_2d_set(), hal_udma_hyperbus_timing_get(), hal_udma_hyperbus_timing_mask_set(), hal_udma_hyperbus_timing_set(), hal_udma_hyperbus_transfert_addr_set(), hal_udma_hyperbus_transfert_cfg_set(), hal_udma_hyperbus_transfert_mode_set(), hal_udma_hyperbus_transfert_size_set(), hal_udma_hyperbus_tx_dest_get(), and hal_udma_hyperbus_tx_dest_set().

#define udma_i2c (   id)

Referenced by hal_udma_i2c_clr_event_by_id(), hal_udma_i2c_clr_event_mask(), hal_udma_i2c_cmd_dest_get(), hal_udma_i2c_cmd_dest_set(), hal_udma_i2c_get_event(), hal_udma_i2c_get_event_by_id(), hal_udma_i2c_rx_dest_get(), hal_udma_i2c_rx_dest_set(), hal_udma_i2c_set_event_by_id(), hal_udma_i2c_slave_rx_dest_get(), hal_udma_i2c_slave_rx_dest_set(), hal_udma_i2c_slave_tx_dest_get(), hal_udma_i2c_slave_tx_dest_set(), hal_udma_i2c_tx_dest_get(), and hal_udma_i2c_tx_dest_set().

#define udma_i2s (   id)

Referenced by __pi_i2s_open(), hal_udma_i2s_clkcfg_reg_get(), hal_udma_i2s_clkcfg_reg_set(), hal_udma_i2s_clkcfg_set(), hal_udma_i2s_glb_reg_get(), hal_udma_i2s_glb_reg_set(), hal_udma_i2s_glb_set(), hal_udma_i2s_slot_cfg_get(), hal_udma_i2s_slot_cfg_rx_disable(), hal_udma_i2s_slot_cfg_rx_enable(), hal_udma_i2s_slot_cfg_rx_set(), hal_udma_i2s_slot_cfg_set(), hal_udma_i2s_slot_cfg_tx_disable(), hal_udma_i2s_slot_cfg_tx_enable(), hal_udma_i2s_slot_cfg_tx_set(), hal_udma_i2s_slot_en_get(), hal_udma_i2s_slot_en_set(), hal_udma_i2s_slot_rx_chan_id_get(), hal_udma_i2s_slot_tx_chan_id_get(), hal_udma_i2s_word_size_get(), hal_udma_i2s_word_size_rx_set(), and hal_udma_i2s_word_size_tx_set().

#define udma_mram (   id)
#define udma_sdio (   id)
#define udma_spim (   id)
#define udma_timestamp (   id)

Referenced by hal_timestamp_clk_gpio_sel(), hal_timestamp_clk_mux_set(), hal_timestamp_clk_prescaler_set(), hal_timestamp_clk_pwm_sel(), hal_timestamp_cnt_clr_set(), hal_timestamp_cnt_ext_en_set(), hal_timestamp_cnt_ext_sel_set(), hal_timestamp_cnt_ext_type_set(), hal_timestamp_cnt_stop_set(), hal_timestamp_input_en_ch0_set(), hal_timestamp_input_en_ch1_set(), hal_timestamp_input_en_ch2_set(), hal_timestamp_input_en_ch3_set(), hal_timestamp_input_en_ch4_set(), hal_timestamp_input_en_ch5_set(), hal_timestamp_input_en_ch6_set(), hal_timestamp_input_en_ch7_set(), hal_timestamp_input_sel_ch0_set(), hal_timestamp_input_sel_ch1_set(), hal_timestamp_input_sel_ch2_set(), hal_timestamp_input_sel_ch3_set(), hal_timestamp_input_sel_ch4_set(), hal_timestamp_input_sel_ch5_set(), hal_timestamp_input_sel_ch6_set(), hal_timestamp_input_sel_ch7_set(), hal_timestamp_input_type_ch0_set(), hal_timestamp_input_type_ch1_set(), hal_timestamp_input_type_ch2_set(), hal_timestamp_input_type_ch3_set(), hal_timestamp_input_type_ch4_set(), hal_timestamp_input_type_ch5_set(), hal_timestamp_input_type_ch6_set(), hal_timestamp_input_type_ch7_set(), and hal_timestamp_rx_dest_set().

#define udma_uart (   id)

Referenced by __pi_uart_open(), hal_udma_uart_clk_div_set(), hal_udma_uart_error_get(), hal_udma_uart_flow_control_disable(), hal_udma_uart_flow_control_enable(), hal_udma_uart_irq_disable(), hal_udma_uart_irq_enable(), hal_udma_uart_rts_limit_get(), hal_udma_uart_rts_limit_set(), hal_udma_uart_rx_dest_get(), hal_udma_uart_rx_dest_set(), hal_udma_uart_rx_disable(), hal_udma_uart_rx_enable(), hal_udma_uart_rx_status_get(), hal_udma_uart_setup_get(), hal_udma_uart_setup_mask_set(), hal_udma_uart_setup_set(), hal_udma_uart_status_get(), hal_udma_uart_tx_dest_get(), hal_udma_uart_tx_dest_set(), hal_udma_uart_tx_disable(), hal_udma_uart_tx_enable(), and hal_udma_uart_tx_status_get().