gap9/pmsis/include/pmsis/implem/hal/pmu/pmu.h File Reference

Macros
#define	COLD_BOOT
#define	DEEP_SLEEP_BOOT
#define	RETENTIVE_BOOT
#define	PI_PMU_SWU_ID
#define	PI_PMU_MRAM_ID
#define	PI_PMU_CSI_ID
#define	PI_PMU_CLUSTER_ID
#define	PI_PMU_CHIP_ID
#define	PI_PMU_STATE_OFF
#define	PI_PMU_STATE_ON
#define	PI_PMU_FLAGS_NO_RET
#define	PI_PMU_FLAGS_RET
#define	PI_PMU_FLAGS_PADS_OFF
#define	PI_PMU_FLAGS_PADS_ON
#define	PI_PMU_CR_WRITE
#define	PI_PMU_CR_READ
#define	PI_PMU_BLOCK_WIU_ADDR
#define	PI_PMU_BLOCK_ICU_ADDR(id)
#define	PI_PMU_BLOCK_DMU_ADDR(id)
#define	PI_PMU_WIU_REG_ISPMR
#define	PI_PMU_WIU_REG_IFR
#define	PI_PMU_WIU_REG_ICR(id)
#define	PI_PMU_PICL_BUS_ADDR(addr, reg)

Functions
static void	hal_pmu_sequence_set (uint16_t addr, uint8_t read, uint16_t data)
static void	hal_pmu_irq_mask_set (uint32_t mask)
static void	hal_pmu_irq_mask_clear (uint32_t mask)
static void	hal_pmu_irq_flag_clear (uint32_t flag)

Macro Definition Documentation

#define COLD_BOOT

#define DEEP_SLEEP_BOOT

#define PI_PMU_BLOCK_DMU_ADDR

(

id

)

#define PI_PMU_BLOCK_ICU_ADDR

(

id

)

#define PI_PMU_BLOCK_WIU_ADDR

WIU(Wake-up Interrupt Unit), ICU(Island Control Unit) and DMU(Dependency Mediator Unit) access on PICL bus.

PICL bus access from DLC : ** Write -> data in DLCPD_MPADR register. ** Read -> data in DLCPD_MPADR register.

• Write in DLCPD_MPACR register(set start bit).
• At the end of the transfer, the PICL_BUSY field of the DLCPD_MSR register becomes low and the PICL_OK interrupt is generated.

PICL bus 16b address :

1. BLOCK_ADDR (DLCPD_MPACR.PAA[15:8]): 8-bit PICL block selection offset;
2. REG_ADDR (DLCPD_MPACR.PAA[7:0]): 8-bit PICL block register offset.

Referenced by __pi_maestro_sequence_trigger().

#define PI_PMU_CHIP_ID

Referenced by __pi_pmu_state_apply(), and pi_pmu_init().

#define PI_PMU_CLUSTER_ID

Referenced by __pi_pmu_wait_end_of_sequence().

#define PI_PMU_CR_READ

#define PI_PMU_CR_WRITE

Maestro 2.3 DLC Access Registers.

Referenced by __pi_maestro_sequence_trigger().

#define PI_PMU_CSI_ID

#define PI_PMU_FLAGS_NO_RET

Referenced by __pi_pmu_state_apply().

#define PI_PMU_FLAGS_PADS_OFF

#define PI_PMU_FLAGS_PADS_ON

Referenced by __pi_pmu_state_apply().

#define PI_PMU_FLAGS_RET

#define PI_PMU_MRAM_ID

Referenced by pi_pmu_mram_poweron().

#define PI_PMU_PICL_BUS_ADDR	(		addr,
			reg
	)

Referenced by __pi_maestro_sequence_trigger().

#define PI_PMU_STATE_OFF

#define PI_PMU_STATE_ON

Referenced by pi_pmu_init(), and pi_pmu_mram_poweron().

#define PI_PMU_SWU_ID

#define PI_PMU_WIU_REG_ICR

(

id

)

#define PI_PMU_WIU_REG_IFR

Referenced by __pi_maestro_sequence_trigger().

#define PI_PMU_WIU_REG_ISPMR

#define RETENTIVE_BOOT

Function Documentation

static void hal_pmu_irq_flag_clear ( uint32_t  flag )

inlinestatic

DLCPD_IFR

References pmu, and power_manager_dlcpd_ifr_set().

Referenced by __pi_pmu_handler(), __pi_pmu_wait_end_of_sequence(), and pi_pmu_init().

static void hal_pmu_irq_mask_clear ( uint32_t  mask )

inlinestatic

References pmu, power_manager_dlcpd_imr_get(), power_manager_dlcpd_imr_set(), and Catch::Generators::value().

static void hal_pmu_irq_mask_set ( uint32_t  mask )

inlinestatic

DLCPD_IMR

References pmu, power_manager_dlcpd_imr_get(), power_manager_dlcpd_imr_set(), and Catch::Generators::value().

Referenced by pi_pmu_init(), and pi_pmu_mram_poweron().

static void hal_pmu_sequence_set ( uint16_t  addr, uint8_t  read, uint16_t  data  )

inlinestatic

DLCPD_MPACR, DLCPD_MPADR.

References pmu, POWER_MANAGER_DLCPD_MPACR_PAADDR, POWER_MANAGER_DLCPD_MPACR_PADIR, POWER_MANAGER_DLCPD_MPACR_PASTART, power_manager_dlcpd_mpacr_set(), POWER_MANAGER_DLCPD_MPADR_PRWDATA, and power_manager_dlcpd_mpadr_set().

Referenced by __pi_maestro_sequence_trigger().