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FreeRTOS port on GAP8/RISC-V
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Definitions for base addresses, unions, and structures. More...
Content | |
| Functions and Instructions Reference | |
| NVIC Functions | |
| Functions that manage interrupts and exceptions via the NVIC. | |
| ID Functions | |
| Functions that manage Cluster and Core ID. | |
| Performance Functions | |
| Functions that manage Core performance. | |
Data Structures | |
| struct | SCB_Type |
| Structure type to access the System Control Block (SCB). More... | |
| struct | DMAMCHAN_Type |
| Structure type to access the direct memory access (DMAMCHAN). More... | |
| struct | DMAMCHAN_COMPRESSOR_Type |
| Structure type to access the direct memory access compressor (DMAMCHAN). More... | |
| struct | decompressor_t |
| #define CL_PERI_BASE |
| #define CL_PERI_BASE |
| #define CORE_EU_BARRIER_BASE |
RISC Core Event Unit HW Barrier Base Address
| #define CORE_EU_BARRIER_BASE |
RISC Core Event Unit HW Barrier Base Address
| #define CORE_EU_BARRIER_DEMUX_BASE |
RISC Core Event Unit HW Barrier Demux Base Address
Referenced by cl_cluster_exec_loop().
| #define CORE_EU_BARRIER_DEMUX_BASE |
RISC Core Event Unit HW Barrier Demux Base Address
| #define CORE_EU_BASE |
RISC Core Event Unit Base Address
| #define CORE_EU_BASE |
RISC Core Event Unit Base Address
| #define CORE_EU_CORE_DEMUX_BASE |
RISC Core Event Unit Core Demux Base Address
Referenced by cl_cluster_exec_loop().
| #define CORE_EU_CORE_DEMUX_BASE |
RISC Core Event Unit Core Demux Base Address
| #define CORE_EU_DEMUX_BASE |
RISC Core Event Unit Demux Base Address
| #define CORE_EU_DEMUX_BASE |
RISC Core Event Unit Demux Base Address
| #define CORE_EU_DISPATCH_DEMUX_BASE |
RISC Core Event Unit Dispatch Demux Base Address
Referenced by cl_cluster_exec_loop().
| #define CORE_EU_DISPATCH_DEMUX_BASE |
RISC Core Event Unit Dispatch Demux Base Address
| #define CORE_EU_EXT_EVENTS_BASE |
RISC Core Event Unit External Events Base Address
| #define CORE_EU_EXT_EVENTS_BASE |
RISC Core Event Unit External Events Base Address
| #define CORE_EU_LOOP_DEMUX_BASE |
RISC Core Event Unit Loop Demux Base Address
Referenced by hal_eu_loop_addr().
| #define CORE_EU_LOOP_DEMUX_BASE |
RISC Core Event Unit Loop Demux Base Address
| #define CORE_EU_MUTEX_DEMUX_BASE |
RISC Core Event Unit Mutex Demux Base Address
| #define CORE_EU_MUTEX_DEMUX_BASE |
RISC Core Event Unit Mutex Demux Base Address
| #define CORE_EU_SEC_DEMUX_BASE |
RISC Core Event Unit Security Demux Base Address
| #define CORE_EU_SEC_DEMUX_BASE |
RISC Core Event Unit Security Demux Base Address
| #define CORE_EU_SOC_EVENTS_BASE |
RISC Core Event Unit SOC Events Base Address
| #define CORE_EU_SOC_EVENTS_BASE |
RISC Core Event Unit SOC Events Base Address
| #define CORE_EU_SW_EVENTS_BASE |
RISC Core Event Unit SW Events Base Address
| #define CORE_EU_SW_EVENTS_BASE |
RISC Core Event Unit SW Events Base Address
| #define CORE_EU_SW_EVENTS_DEMUX_BASE |
RISC Core Event Unit SW Event Demux Base Address
| #define CORE_EU_SW_EVENTS_DEMUX_BASE |
RISC Core Event Unit SW Event Demux Base Address
| #define CORE_MCHAN_BASE |
RISC Core DMAMCHAN Base Address between L2 and Cluster TCDM
| #define CORE_MCHAN_BASE |
| #define CORE_MCHAN_CL_BASE |
RISC Core DMAMCHAN Cluster control Base Address between L2 and Cluster TCDM
| #define CORE_MCHAN_COMPRESSOR_BASE |
RISC Core DMAMCHAN Compressor control Base Address between L2 and Cluster TCDM
| #define CORE_MCHAN_FC_BASE |
RISC Core DMAMCHAN FC control Base Address between L2 and Cluster TCDM
| #define CORE_PERI_BASE |
RISC Core Peripheral Base Address
| #define CORE_PERI_BASE |
RISC Core Peripheral Base Address
| #define CORE_SCB_BASE |
RISC Core System Control Block Base Address
| #define CORE_SCB_BASE |
RISC Core System Control Block Base Address
| #define CORE_SCBC_BASE |
RISC Core System Control Block Cache Base Address
| #define CORE_SCBC_BASE |
RISC Core System Control Block Cache Base Address
| #define CORE_SysTick_BASE |
RISC Core SysTick Base Address
| #define CORE_SysTick_BASE |
RISC Core SysTick Base Address
| #define DMAMCHAN |
MCHAN DMA configuration struct
Referenced by cl_dma_cmd_get(), cl_dma_cmd_set(), cl_dma_status_get(), and cl_dma_status_set().
| #define DMAMCHAN |
MCHAN DMA configuration struct
| #define DMAMCHAN_CMD_2D_COUNT_Msk |
DMAMCHAN CMD 2D COUNT Mask
| #define DMAMCHAN_CMD_2D_COUNT_Msk |
DMAMCHAN CMD 2D COUNT Mask
| #define DMAMCHAN_CMD_2D_COUNT_Pos |
DMAMCHAN CMD 2D COUNT Position
Referenced by hal_cl_dma_2d_transfer_push().
| #define DMAMCHAN_CMD_2D_COUNT_Pos |
DMAMCHAN CMD 2D COUNT Position
| #define DMAMCHAN_CMD_2D_Msk |
DMAMCHAN CMD 2D transfer Mask
| #define DMAMCHAN_CMD_2D_Msk |
DMAMCHAN CMD 2D transfer Mask
| #define DMAMCHAN_CMD_2D_Pos |
DMAMCHAN CMD 2D transfer Position
Referenced by hal_cl_dma_cmd_make().
| #define DMAMCHAN_CMD_2D_Pos |
DMAMCHAN CMD 2D transfer Position
| #define DMAMCHAN_CMD_2D_STRIDE_Msk |
DMAMCHAN CMD 2D STRIDE Mask
| #define DMAMCHAN_CMD_2D_STRIDE_Msk |
DMAMCHAN CMD 2D STRIDE Mask
| #define DMAMCHAN_CMD_2D_STRIDE_Pos |
DMAMCHAN CMD 2D STRIDE Position
Referenced by hal_cl_dma_2d_transfer_push().
| #define DMAMCHAN_CMD_2D_STRIDE_Pos |
DMAMCHAN CMD 2D STRIDE Position
| #define DMAMCHAN_CMD_BLE_Msk |
DMAMCHAN CMD Broadcast Lines Enable Mask
| #define DMAMCHAN_CMD_BLE_Msk |
DMAMCHAN CMD Broadcast Lines Enable Mask
| #define DMAMCHAN_CMD_BLE_Pos |
DMAMCHAN Broadcast Lines Enable Position
Referenced by hal_cl_dma_cmd_make().
| #define DMAMCHAN_CMD_BLE_Pos |
DMAMCHAN Broadcast Lines Enable Position
| #define DMAMCHAN_CMD_ELE_Msk |
DMAMCHAN CMD Event Line Enable Mask
| #define DMAMCHAN_CMD_ELE_Msk |
DMAMCHAN CMD Event Line Enable Mask
| #define DMAMCHAN_CMD_ELE_Pos |
DMAMCHAN CMD Event Line Enable Position
Referenced by hal_cl_dma_cmd_make().
| #define DMAMCHAN_CMD_ELE_Pos |
DMAMCHAN CMD Event Line Enable Position
| #define DMAMCHAN_CMD_ILE_Msk |
DMAMCHAN Intrrupt Line Enable Mask
| #define DMAMCHAN_CMD_ILE_Msk |
DMAMCHAN Intrrupt Line Enable Mask
| #define DMAMCHAN_CMD_ILE_Pos |
DMAMCHAN Intrrupt Line EnableID Position
Referenced by hal_cl_dma_cmd_make().
| #define DMAMCHAN_CMD_ILE_Pos |
DMAMCHAN Intrrupt Line EnableID Position
| #define DMAMCHAN_CMD_INC_Msk |
DMAMCHAN CMD Increment Mask
| #define DMAMCHAN_CMD_INC_Msk |
DMAMCHAN CMD Increment Mask
| #define DMAMCHAN_CMD_INC_Pos |
DMAMCHAN CMD Increment Position
Referenced by hal_cl_dma_cmd_make().
| #define DMAMCHAN_CMD_INC_Pos |
DMAMCHAN CMD Increment Position
| #define DMAMCHAN_CMD_LEN_Msk |
DMAMCHAN CMD Length Mask
| #define DMAMCHAN_CMD_LEN_Msk |
DMAMCHAN CMD Length Mask
| #define DMAMCHAN_CMD_LEN_Pos |
DMAMCHAN CMD Length Position
Referenced by hal_cl_dma_cmd_make().
| #define DMAMCHAN_CMD_LEN_Pos |
DMAMCHAN CMD Length Position
| #define DMAMCHAN_CMD_TID_Msk |
DMAMCHAN TID Mask
| #define DMAMCHAN_CMD_TID_Msk |
DMAMCHAN TID Mask
| #define DMAMCHAN_CMD_TID_Pos |
DMAMCHAN TID Position
| #define DMAMCHAN_CMD_TID_Pos |
DMAMCHAN TID Position
| #define DMAMCHAN_CMD_TYP_Msk |
DMAMCHAN CMD Type Mask
| #define DMAMCHAN_CMD_TYP_Msk |
DMAMCHAN CMD Type Mask
| #define DMAMCHAN_CMD_TYP_Pos |
DMAMCHAN CMD Type Position
Referenced by hal_cl_dma_cmd_make().
| #define DMAMCHAN_CMD_TYP_Pos |
DMAMCHAN CMD Type Position
| #define DMAMCHAN_COMPRESSOR |
| #define DMAMCHAN_COMPRESSOR |
| #define EU_BARRIER_DEMUX | ( | id | ) |
EU_BARRIER_DEMUX configuration struct
Referenced by hal_eu_barrier_setup(), hal_eu_barrier_team_get(), hal_eu_barrier_trigger(), and hal_eu_barrier_trigger_wait_clear().
| #define EU_BARRIER_DEMUX | ( | id | ) |
EU_BARRIER_DEMUX configuration struct
| #define EU_CORE_DEMUX |
EU_CORE_DEMUX configuration struct
Referenced by __attribute__(), hal_eu_evt_clr(), hal_eu_evt_mask(), hal_eu_evt_mask_clr(), hal_eu_evt_mask_set(), hal_eu_evt_status(), hal_eu_evt_status_irq_masked(), hal_eu_evt_status_masked(), hal_eu_evt_wait(), hal_eu_evt_wait_and_clr(), hal_eu_irq_mask(), hal_eu_irq_mask_clr(), hal_eu_irq_mask_set(), hal_eu_irq_sec_mask(), and hal_eu_irq_status().
| #define EU_CORE_DEMUX |
EU_CORE_DEMUX configuration struct
| #define EU_DISPATCH_DEMUX |
EU_DISPATCH_DEMUX configuration struct
Referenced by hal_eu_dispatch_pop(), hal_eu_dispatch_push(), and hal_eu_dispatch_team_config().
| #define EU_DISPATCH_DEMUX |
EU_DISPATCH_DEMUX configuration struct
| #define EU_LOOP_DEMUX |
EU_LOOP_DEMUX configuration struct
Referenced by hal_eu_loop_get_chunk(), hal_eu_loop_get_single(), hal_eu_loop_get_start(), hal_eu_loop_get_state(), hal_eu_loop_init_epoch(), hal_eu_loop_set_chunk(), hal_eu_loop_set_end(), hal_eu_loop_set_incr(), and hal_eu_loop_set_start().
| #define EU_LOOP_DEMUX |
EU_LOOP_DEMUX configuration struct
| #define EU_MUTEX_DEMUX |
EU_MUTEX_DEMUX configuration struct
Referenced by hal_eu_mutex_init(), hal_eu_mutex_lock(), and hal_eu_mutex_unlock().
| #define EU_MUTEX_DEMUX |
EU_MUTEX_DEMUX configuration struct
| #define EU_SEC_DEMUX |
EU_SEC_DEMUX configuration struct
Referenced by hal_eu_irq_sec_mask_clr(), and hal_eu_irq_sec_mask_set().
| #define EU_SEC_DEMUX |
EU_SEC_DEMUX configuration struct
| #define EU_SOC_EVENTS |
EU_SW_EVENTS_DEMUX configuration struct
Referenced by __attribute__(), hal_eu_soc_events_pop(), and hal_fc_eu_soc_events_pop().
| #define EU_SOC_EVENTS |
EU_SW_EVENTS_DEMUX configuration struct
| #define EU_SW_EVENTS |
EU_SW_EVENTS_DEMUX configuration struct
| #define EU_SW_EVENTS |
EU_SW_EVENTS_DEMUX configuration struct
| #define EU_SW_EVENTS_DEMUX |
EU_SW_EVENTS_DEMUX configuration struct
Referenced by hal_eu_fc_evt_demux_trig_set().
| #define EU_SW_EVENTS_DEMUX |
EU_SW_EVENTS_DEMUX configuration struct
| #define FC_BASE |
FC Base Address
| #define FC_BASE |
FC Base Address
| #define FC_CLUSTER_ID |
FC_CLUSTER_ID Definitions FC CLuster ID
Referenced by hal_soc_eu_configure().
| #define FC_CLUSTER_ID |
FC_CLUSTER_ID Definitions FC CLuster ID
| #define FC_CORE_ID |
FC CLuster ID
| #define FC_EU_BARRIER_BASE |
FC Event Unit HW Barrier Base Address
| #define FC_EU_BARRIER_BASE |
FC Event Unit HW Barrier Base Address
| #define FC_EU_BARRIER_DEMUX_BASE |
FC Event Unit Barrier Demux Base Address
| #define FC_EU_BARRIER_DEMUX_BASE |
FC Event Unit Barrier Demux Base Address
| #define FC_EU_CORE_DEMUX_BASE |
FC Event Unit Core Demux Base Address
| #define FC_EU_CORE_DEMUX_BASE |
FC Event Unit Core Demux Base Address
| #define FC_EU_DISPATCH_DEMUX_BASE |
FC Event Unit Dispatch Demux Base Address
| #define FC_EU_DISPATCH_DEMUX_BASE |
FC Event Unit Dispatch Demux Base Address
| #define FC_EU_EXT_EVENTS_BASE |
FC Event Unit EXT Events Base Address
| #define FC_EU_EXT_EVENTS_BASE |
FC Event Unit EXT Events Base Address
| #define FC_EU_LOOP_DEMUX_BASE |
FC Event Unit Loop Demux Base Address
| #define FC_EU_LOOP_DEMUX_BASE |
FC Event Unit Loop Demux Base Address
| #define FC_EU_MUTEX_DEMUX_BASE |
FC Event Unit Mutex Demux Base Address
| #define FC_EU_MUTEX_DEMUX_BASE |
FC Event Unit Mutex Demux Base Address
| #define FC_EU_SEC_DEMUX_BASE |
FC Event Unit Security Demux Base Address
| #define FC_EU_SEC_DEMUX_BASE |
FC Event Unit Security Demux Base Address
| #define FC_EU_SOC_EVENTS_BASE |
FC Event Unit SOC Events Base Address
| #define FC_EU_SOC_EVENTS_BASE |
FC Event Unit SOC Events Base Address
| #define FC_EU_SW_EVENTS |
EU_SW_EVENTS_DEMUX configuration struct
Referenced by hal_eu_fc_evt_trig_set().
| #define FC_EU_SW_EVENTS |
EU_SW_EVENTS_DEMUX configuration struct
| #define FC_EU_SW_EVENTS_BASE |
FC Event Unit SW Events Base Address
| #define FC_EU_SW_EVENTS_BASE |
FC Event Unit SW Events Base Address
| #define FC_EU_SW_EVENTS_DEMUX_BASE |
FC Event Unit SW Events Demux Base Address
| #define FC_EU_SW_EVENTS_DEMUX_BASE |
FC Event Unit SW Events Demux Base Address
| #define FC_MCHAN_BASE |
FC DMAMCHAN Base Address between L2 and Cluster TCDM
| #define FC_MCHAN_BASE |
FC DMAMCHAN Base Address between L2 and Cluster TCDM
| #define FC_SCBC_BASE |
FC System Control Block Cache Base Address
| #define FC_SCBC_BASE |
FC System Control Block Cache Base Address
| #define FC_SysTick_BASE |
FC SysTick Base Address
| #define FC_SysTick_BASE |
FC SysTick Base Address
| #define NVIC |
NVIC configuration struct
Referenced by __NVIC_DisableIRQ(), __NVIC_EnableIRQ(), __NVIC_GetActive(), __NVIC_GetEnableIRQ(), and system_init().
| #define NVIC |
NVIC configuration struct
Referenced by __NVIC_DisableIRQ(), __NVIC_EnableIRQ(), __NVIC_GetActive(), and __NVIC_GetEnableIRQ().
| #define NVIC_BASE |
RISC NVIC Base Address
| #define NVIC_BASE |
RISC NVIC Base Address
| #define SCB_EOC_Msk |
SCB EOC Mask
| #define SCB_EOC_Msk |
SCB EOC Mask
| #define SCB_EOC_Pos |
SCB EOC Position
| #define SCB_EOC_Pos |
SCB EOC Position
| #define SCB_FETCH_EN_Msk |
SCB FETCH_EN Mask
| #define SCB_FETCH_EN_Msk |
SCB FETCH_EN Mask
| #define SCB_FETCH_EN_Pos |
SCB FETCH_EN Position
| #define SCB_FETCH_EN_Pos |
SCB FETCH_EN Position
| #define SCBC |
Icache SCBC configuration struct
Referenced by cl_cluster_exec_loop(), and system_init().
| #define SCBC |
Icache SCBC configuration struct
| #define SOC_PERI_BASE |
SOC Peripherals Base Address
| #define SOC_PERI_BASE |
SOC Peripherals Base Address
| #define SOC_ROM_BASE |
SOC ROM Base Address
| #define SOC_ROM_BASE |
SOC ROM Base Address
| #define SysTick |
SysTick configuration struct
| #define SysTick |
SysTick configuration struct
| #define TIMER0_BASE |
RISC Peripheral TIMER0 Base Address
| #define TIMER1_BASE |
RISC Peripheral TIMER1 Base Address
| #define TIMERH |
SysTick configuration struct
| #define TIMERH |
SysTick configuration struct
| #define TIMERL |
SysTick configuration struct
| #define TIMERL |
SysTick configuration struct
| uint32_t CPRIV_Type::_reserved0 |
bit: 2..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 2..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 2..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 2..31 Reserved
| uint32_t PCMR_Type::_reserved0 |
bit: 2..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 2..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 17..31 Reserved
| uint32_t PCER_Type::_reserved0 |
bit: 17..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 17..31 Reserved
| __IOM uint32_t SCB_Type::_reserved0 |
Offset: 0x004 (R/W) reserved Register
| uint32_t TimerL_Type::_reserved0 |
Offset: 0x004 (R/W) Empty Registers
| uint32_t TimerH_Type::_reserved0 |
Offset: 0x000 (R/W) Empty Registers
| __IOM uint32_t EU_SW_EVENTS_DEMUX_Type::_reserved0 |
Offset: 0x20 (R/W) Empty Registers
| __IOM uint32_t SCB_Type::_reserved1 |
Offset: 0x00C (R/W) reserved Register
| uint32_t TimerL_Type::_reserved1 |
Offset: 0x00C (R/W) Empty Registers
| uint32_t TimerH_Type::_reserved1 |
Offset: 0x008 (R/W) Empty Registers
| __IOM uint32_t EU_SW_EVENTS_DEMUX_Type::_reserved1 |
Offset: 0x60 (R/W) Empty Registers
| __IOM uint32_t SCB_Type::_reserved2 |
Offset: 0x014 (R/W) reserved Register
| uint32_t TimerL_Type::_reserved2 |
Offset: 0x014 (R/W) Empty Registers
| uint32_t TimerH_Type::_reserved2 |
Offset: 0x010 (R/W) Empty Registers
| __IOM uint32_t SCB_Type::_reserved3 |
Offset: 0x024 (R/W) reserved Registers
| uint32_t TimerL_Type::_reserved3 |
Offset: 0x014 (R/W) Empty Registers
| uint32_t TimerH_Type::_reserved3 |
Offset: 0x014 (R/W) Empty Registers
| uint32_t TimerH_Type::_reserved4 |
Offset: 0x014 (R/W) Empty Registers
| __IO uint32_t NVIC_Type::ACK |
FC_ITC ACK register, offset: 0x18
| __IO uint32_t NVIC_Type::ACK_CLR |
FC_ITC ACK clean register, offset: 0x20
| __IO uint32_t NVIC_Type::ACK_SET |
FC_ITC ACK set register, offset: 0x1C
| struct { ... } MVENDORID_Type::b |
Structure used for bit access
| struct { ... } MVENDORID_Type::b |
Structure used for bit access
| struct { ... } MHARTID_Type::b |
Structure used for bit access
| struct { ... } MHARTID_Type::b |
Structure used for bit access
| struct { ... } MISA_Type::b |
Structure used for bit access
| struct { ... } MISA_Type::b |
Structure used for bit access
| struct { ... } MSTATUS_Type::b |
Structure used for bit access
| struct { ... } MSTATUS_Type::b |
Structure used for bit access
| struct { ... } MTVEC_Type::b |
Structure used for bit access
| struct { ... } MTVEC_Type::b |
Structure used for bit access
| struct { ... } MCAUSE_Type::b |
Structure used for bit access
| struct { ... } MCAUSE_Type::b |
Structure used for bit access
| struct { ... } CPRIV_Type::b |
Structure used for bit access
| struct { ... } CPRIV_Type::b |
Structure used for bit access
| struct { ... } PCMR_Type::b |
Structure used for bit access
| struct { ... } PCMR_Type::b |
Structure used for bit access
| struct { ... } PCER_Type::b |
Structure used for bit access
| struct { ... } PCER_Type::b |
Structure used for bit access
| uint32_t MVENDORID_Type::BANK |
bit: 7..31
| uint32_t { ... } ::BANK |
bit: 7..31
| uint32_t { ... } ::BANK |
bit: 7..31
| uint32_t MHARTID_Type::BANK |
bit: 5..31 Reserved
| uint32_t { ... } ::BANK |
bit: 5..31 Reserved
| uint32_t { ... } ::BANK |
bit: 5..31 Reserved
| uint32_t { ... } ::BASE |
bit: 2..31 vector base address
| uint32_t MTVEC_Type::BASE |
bit: 2..31 vector base address
| uint32_t { ... } ::BASE |
bit: 2..31 vector base address
| __I uint32_t DMAMCHAN_COMPRESSOR_Type::BIT_READ |
Offset: 0x1C (W ) Compressor transfer direction Register
| __O uint32_t decompressor_t::BIT_READ_REG |
| __IOM uint32_t SCB_Type::BOOT_ADDR |
Offset: 0x040 (R/W) Vector Table Offset Register
| uint32_t { ... } ::BRANCH |
bit: 10 BRANCH
| uint32_t PCER_Type::BRANCH |
bit: 10 BRANCH
| uint32_t { ... } ::BRANCH |
bit: 10 BRANCH
| __IOM uint32_t EU_CORE_DEMUX_Type::BUFFER |
EU_DEMUX buffer register, offset: 0x1C
| __IOM uint32_t EU_CORE_DEMUX_Type::BUFFER_CLEAR |
EU_DEMUX buffer clear register, offset: 0x28
| __IOM uint32_t EU_CORE_DEMUX_Type::BUFFER_IRQ_MASKED |
EU_DEMUX buffer irq masked register, offset: 0x24
| __IOM uint32_t EU_CORE_DEMUX_Type::BUFFER_MASKED |
EU_DEMUX buffer masked register, offset: 0x20
| __IOM uint32_t SysTick_Type::CFG_REG_HI |
Offset: 0x004 (R/W) SysTick Configuration Register for high 32-bits
| __IOM uint32_t SysTick_Type::CFG_REG_LO |
Offset: 0x000 (R/W) SysTick Configuration Register for lower 32-bits
| __IOM uint32_t EU_LOOP_DEMUX_Type::CHUNK |
EU_LOOP_DEMUX chunk register, offset: 0x10
| __O uint32_t decompressor_t::CLKEN_REG |
| __OM uint32_t SCB_Type::CLUSTER_CG |
Offset: 0x020 (R/W) Event out Register
| __IOM uint32_t DMAMCHAN_Type::CMD |
Offset: 0x00 (R/W ) DMAMCHAN Command Base Register
| __IOM uint32_t SysTick_Type::CMP_HI |
Offset: 0x014 (R/W) SysTick Timer comparator Register for high 32-bits
| __IOM uint32_t SysTick_Type::CMP_LO |
Offset: 0x010 (R/W) SysTick Timer comparator Register for low 32-bits
| __IOM uint32_t TimerL_Type::COMPARE |
Offset: 0x010 (R/W) TIMERL Timer comparator Register for low 32-bits
| __IOM uint32_t TimerH_Type::COMPARE |
Offset: 0x014 (R/W) TIMERH Timer comparator Register for high 32-bits
| __O uint32_t decompressor_t::CONF_REG |
| __O uint32_t DMAMCHAN_COMPRESSOR_Type::CONFIG |
| __IOM uint32_t TimerL_Type::CTRL |
Offset: 0x000 (R/W) TIMERL Configuration Register for lower 32-bits
| __IOM uint32_t TimerH_Type::CTRL |
Offset: 0x004 (R/W) TIMERH Configuration Register for high 32-bits
| __IM uint32_t EU_SOC_EVENTS_Type::CURRENT_EVENT |
EU_SOC_EVENTS current event register, offset: 0x00
| uint32_t { ... } ::CYCLE |
bit: 0 CYCLE
| uint32_t PCER_Type::CYCLE |
bit: 0 CYCLE
| uint32_t { ... } ::CYCLE |
bit: 0 CYCLE
| uint32_t { ... } ::DELAY_SLOT |
bit: 11 DELAY_SLOT
| uint32_t { ... } ::DELAY_SLOT |
bit: 11 DELAY_SLOT
| uint32_t PCER_Type::DELAY_SLOT |
bit: 11 DELAY_SLOT
| __O uint32_t DMAMCHAN_COMPRESSOR_Type::DIRECTION |
| uint32_t MCAUSE_Type::EC |
bit: 0..30 Exception code
| uint32_t { ... } ::EC |
bit: 0..30 Exception code
| uint32_t { ... } ::EC |
bit: 0..30 Exception code
| __IOM uint32_t EU_LOOP_DEMUX_Type::END |
EU_LOOP_DEMUX end register, offset: 0x08
| __OM uint32_t SCB_Type::EOC |
Offset: 0x000 (R/W ) CPUID Base Register
| __IOM uint32_t EU_LOOP_DEMUX_Type::EPOCH |
EU_LOOP_DEMUX epoch register, offset: 0x14
| __OM uint32_t SCB_Type::EVENT |
Offset: 0x010 (W) Event out Register
| __IOM uint32_t EU_CORE_DEMUX_Type::EVENT_WAIT |
EU_DEMUX event wait register, offset: 0x38
| __IOM uint32_t EU_CORE_DEMUX_Type::EVENT_WAIT_CLEAR |
EU_DEMUX event wait clear register, offset: 0x3C
| uint32_t { ... } ::EXTENSION |
bit: 0.. 25 ISA Extension
| uint32_t MISA_Type::EXTENSION |
bit: 0.. 25 ISA Extension
| uint32_t { ... } ::EXTENSION |
bit: 0.. 25 ISA Extension
| __IOM uint32_t SCB_Type::FETCH_EN |
Offset: 0x008 (R/W) Interrupt Control and State Register
| __IO uint32_t NVIC_Type::FIFO |
FC_ITC FIFO register, offset: 024
| __IOM uint32_t EU_DISPATCH_DEMUX_Type::FIFO_ACCESS |
EU_DISPATCH_DEMUX fifo access register, offset: 0x00
| uint32_t { ... } ::FS |
bit: 13, 14 Reserved
| uint32_t MSTATUS_Type::FS |
bit: 13, 14 Reserved
| uint32_t { ... } ::FS |
bit: 13, 14 Reserved
| uint32_t { ... } ::GLBEN |
bit: 0 Enbable all Performance counter
| uint32_t PCMR_Type::GLBEN |
bit: 0 Enbable all Performance counter
| uint32_t { ... } ::GLBEN |
bit: 0 Enbable all Performance counter
| __IOM uint32_t SCBC_Type::ICACHE_CNTS_CLEAR |
Offset: 0x10 (R/W) Cluster Icache is private Icache
| __IOM uint32_t SCBC_Type::ICACHE_CNTS_ENABLE |
Offset: 0x10 (R/W) Cluster Icache is private Icache
| __IOM uint32_t SCBC_Type::ICACHE_ENABLE |
Offset: 0x00 (R/W ) Cluster Icache Enable Register
| __IOM uint32_t SCBC_Type::ICACHE_FLUSH |
Offset: 0x04 (R/W) Cluster Icache Flush Register
| __IOM uint32_t SCBC_Type::ICACHE_LX_SEL_FLUSH |
Offset: 0x08 (R/W) Cluster Icache Level-X Flush Register or FC Flush Selected Address Register
| __IOM uint32_t SCBC_Type::ICACHE_SEL_FLUSH_STATUS |
Offset: 0x0C (R/W) Cluster Icache Flush Selected Address Register or FC ICACHE status
| uint32_t { ... } ::IMISS |
bit: 4 IMISS
| uint32_t { ... } ::IMISS |
bit: 4 IMISS
| uint32_t PCER_Type::IMISS |
bit: 4 IMISS
| __IOM uint32_t EU_LOOP_DEMUX_Type::INCR |
EU_LOOP_DEMUX increment register, offset: 0x0C
| uint32_t { ... } ::INSTR |
bit: 1 INSTR
| uint32_t PCER_Type::INSTR |
bit: 1 INSTR
| uint32_t { ... } ::INSTR |
bit: 1 INSTR
| uint32_t { ... } ::IRQ |
bit: 31 Interrupt flag
| uint32_t { ... } ::IRQ |
bit: 31 Interrupt flag
| uint32_t MCAUSE_Type::IRQ |
bit: 31 Interrupt flag
| uint32_t { ... } ::JMP_STALL |
bit: 3 JMP_STALL
| uint32_t { ... } ::JMP_STALL |
bit: 3 JMP_STALL
| uint32_t PCER_Type::JMP_STALL |
bit: 3 JMP_STALL
| uint32_t { ... } ::JUMP |
bit: 9 JUMP
| uint32_t PCER_Type::JUMP |
bit: 9 JUMP
| uint32_t { ... } ::JUMP |
bit: 9 JUMP
| __O uint32_t decompressor_t::L2_ADDR |
| __O uint32_t DMAMCHAN_COMPRESSOR_Type::L2_ADDRESS |
Offset: 0x08 (W ) Compressor configuration Register
| __O uint32_t decompressor_t::L2_COUNT_REG |
| __O uint32_t decompressor_t::L2_STRIDE_REG |
| uint32_t { ... } ::LD |
bit: 7 LD
| uint32_t { ... } ::LD |
bit: 7 LD
| uint32_t PCER_Type::LD |
bit: 7 LD
| uint32_t { ... } ::LD_EXT |
bit: 12 LD_EXT
| uint32_t PCER_Type::LD_EXT |
bit: 12 LD_EXT
| uint32_t { ... } ::LD_EXT |
bit: 12 LD_EXT
| uint32_t { ... } ::LD_EXT_CYC |
bit: 14 LD_EXT_CYC
| uint32_t PCER_Type::LD_EXT_CYC |
bit: 14 LD_EXT_CYC
| uint32_t { ... } ::LD_EXT_CYC |
bit: 14 LD_EXT_CYC
| uint32_t { ... } ::LD_STALL |
bit: 2 LD_STALL
| uint32_t PCER_Type::LD_STALL |
bit: 2 LD_STALL
| uint32_t { ... } ::LD_STALL |
bit: 2 LD_STALL
| __O uint32_t DMAMCHAN_COMPRESSOR_Type::LUT |
Offset: 0x14 (W ) Compressor compression special value Register
| __O uint32_t decompressor_t::LUT_REG |
| __IO uint32_t NVIC_Type::MASK |
FC_ITC Mask register, offset: 0x00
| __IOM uint32_t NVIC_Type::MASK |
EU_DEMUX mask register, offset: 0x00
| __IOM uint32_t EU_CORE_DEMUX_Type::MASK |
EU_DEMUX mask register, offset: 0x00
| __IOM uint32_t EU_SEC_DEMUX_Type::MASK |
EU_SEC_DEMUX mask register, offset: 0x00
| __IOM uint32_t NVIC_Type::MASK_AND |
EU_DEMUX mask and register, offset: 0x04
| __IOM uint32_t EU_CORE_DEMUX_Type::MASK_AND |
EU_DEMUX mask and register, offset: 0x04
| __IOM uint32_t EU_SEC_DEMUX_Type::MASK_AND |
EU_SEC_DEMUX mask and register, offset: 0x04
| __IO uint32_t NVIC_Type::MASK_CLR |
FC_ITC Mask clean register, offset: 0x08
| __IOM uint32_t NVIC_Type::MASK_IRQ |
EU_DEMUX mask irq register, offset: 0x0C
| __IOM uint32_t EU_CORE_DEMUX_Type::MASK_IRQ |
EU_DEMUX mask irq register, offset: 0x0C
| __IOM uint32_t NVIC_Type::MASK_IRQ_AND |
EU_DEMUX mask irq and register, offset: 0x10
| __IOM uint32_t EU_CORE_DEMUX_Type::MASK_IRQ_AND |
EU_DEMUX mask irq and register, offset: 0x10
| __IOM uint32_t NVIC_Type::MASK_IRQ_OR |
EU_DEMUX mask irq or register, offset: 0x14
| __IOM uint32_t EU_CORE_DEMUX_Type::MASK_IRQ_OR |
EU_DEMUX mask irq or register, offset: 0x14
| __IOM uint32_t NVIC_Type::MASK_OR |
EU_DEMUX mask or register, offset: 0x08
| __IOM uint32_t EU_CORE_DEMUX_Type::MASK_OR |
EU_DEMUX mask or register, offset: 0x08
| __IOM uint32_t EU_SEC_DEMUX_Type::MASK_OR |
EU_SEC_DEMUX mask or register, offset: 0x08
| __IOM uint32_t EU_CORE_DEMUX_Type::MASK_SEC_IRQ |
EU_DEMUX mask sec irq register, offset: 0x40
| __IO uint32_t NVIC_Type::MASK_SET |
FC_ITC Mask set register, offset: 0x04
| uint32_t { ... } ::MIE |
bit: 3 Machine Interrupt-enable bit
| uint32_t MSTATUS_Type::MIE |
bit: 3 Machine Interrupt-enable bit
| uint32_t { ... } ::MIE |
bit: 3 Machine Interrupt-enable bit
| uint32_t { ... } ::MODE |
bit: 0..1 vector mode
| uint32_t { ... } ::MODE |
bit: 0..1 vector mode
| uint32_t MTVEC_Type::MODE |
bit: 0..1 vector mode
| __O uint32_t decompressor_t::MODE_REG |
| uint32_t MSTATUS_Type::MPIE |
bit: 7 Prior Machine Interrupt-enable bit on trap
| uint32_t { ... } ::MPIE |
bit: 7 Prior Machine Interrupt-enable bit on trap
| uint32_t { ... } ::MPIE |
bit: 7 Prior Machine Interrupt-enable bit on trap
| uint32_t { ... } ::MPP |
bit: 11, 12 Supervise previous privilege value, up to machine mode
| uint32_t MSTATUS_Type::MPP |
bit: 11, 12 Supervise previous privilege value, up to machine mode
| uint32_t { ... } ::MPP |
bit: 11, 12 Supervise previous privilege value, up to machine mode
| uint32_t { ... } ::MPRV |
bit: 17 Reserved
| uint32_t MSTATUS_Type::MPRV |
bit: 17 Reserved
| uint32_t { ... } ::MPRV |
bit: 17 Reserved
| __IOM uint32_t EU_MUTEX_DEMUX_Type::MUTEX |
EU_MUTEX_DEMUX mutex register, offset: 0x00
| uint32_t { ... } ::MXL |
bit: 30..31 Machine XLEN
| uint32_t MISA_Type::MXL |
bit: 30..31 Machine XLEN
| uint32_t { ... } ::MXL |
bit: 30..31 Machine XLEN
| uint32_t { ... } ::MXR |
bit: 19 Reserved
| uint32_t MSTATUS_Type::MXR |
bit: 19 Reserved
| uint32_t { ... } ::MXR |
bit: 19 Reserved
| uint32_t { ... } ::OFFSET |
bit: 0..6
| uint32_t MVENDORID_Type::OFFSET |
bit: 0..6
| uint32_t { ... } ::OFFSET |
bit: 0..6
| uint32_t { ... } ::OFFSET |
bit: 0..4 Hardware thread id
| uint32_t MHARTID_Type::OFFSET |
bit: 0..4 Hardware thread id
| uint32_t { ... } ::OFFSET |
bit: 0..4 Hardware thread id
| __IOM uint32_t DMAMCHAN_COMPRESSOR_Type::PAD0 |
Offset: 0x10 (W ) Compressor LUT patterns Register
| __IOM uint32_t decompressor_t::PAD0 |
| uint32_t { ... } ::PRIV |
bit: 0..1 Current privilege level
| uint32_t CPRIV_Type::PRIV |
bit: 0..1 Current privilege level
| uint32_t { ... } ::PRIV |
bit: 0..1 Current privilege level
| __OM uint32_t TimerL_Type::RESET |
Offset: 0x014 (R/W) SysTick Timer reset Register for low 32-bits
| __OM uint32_t TimerH_Type::RESET |
Offset: 0x014 (R/W) SysTick Timer reset Register for high 32-bits
| __OM uint32_t SysTick_Type::RESET_HI |
Offset: 0x014 (R/W) SysTick Timer reset Register for high 32-bits
| __OM uint32_t SysTick_Type::RESET_LO |
Offset: 0x014 (R/W) SysTick Timer reset Register for low 32-bits
| uint32_t { ... } ::SATU |
bit: 1 Use saturating arithmetic
| uint32_t PCMR_Type::SATU |
bit: 1 Use saturating arithmetic
| uint32_t { ... } ::SATU |
bit: 1 Use saturating arithmetic
| uint32_t { ... } ::SD |
bit: 31 Reserved
| uint32_t MSTATUS_Type::SD |
bit: 31 Reserved
| uint32_t { ... } ::SD |
bit: 31 Reserved
| uint32_t { ... } ::SIE |
bit: 1 Supervisor Interrupt-enable bit
| uint32_t MSTATUS_Type::SIE |
bit: 1 Supervisor Interrupt-enable bit
| uint32_t { ... } ::SIE |
bit: 1 Supervisor Interrupt-enable bit
| __IOM uint32_t EU_LOOP_DEMUX_Type::SINGLE |
EU_LOOP_DEMUX single register, offset: 0x18
| __O uint32_t DMAMCHAN_COMPRESSOR_Type::SPECIAL |
Offset: 0x18 (R ) Compressor readen bits Register
| uint32_t { ... } ::SPIE |
bit: 5 Prior Supervisor Interrupt-enable bit on trap
| uint32_t { ... } ::SPIE |
bit: 5 Prior Supervisor Interrupt-enable bit on trap
| uint32_t MSTATUS_Type::SPIE |
bit: 5 Prior Supervisor Interrupt-enable bit on trap
| uint32_t MSTATUS_Type::SPP |
bit: 8 Supervisor previous privilege value, up to supervisor mode
| uint32_t { ... } ::SPP |
bit: 8 Supervisor previous privilege value, up to supervisor mode
| uint32_t { ... } ::SPP |
bit: 8 Supervisor previous privilege value, up to supervisor mode
| uint32_t { ... } ::ST |
bit: 8 ST
| uint32_t PCER_Type::ST |
bit: 8 ST
| uint32_t { ... } ::ST |
bit: 8 ST
| uint32_t { ... } ::ST_EXT |
bit: 13 ST_EXT
| uint32_t { ... } ::ST_EXT |
bit: 13 ST_EXT
| uint32_t PCER_Type::ST_EXT |
bit: 13 ST_EXT
| uint32_t { ... } ::ST_EXT_CYC |
bit: 15 ST_EXT_CYC
| uint32_t PCER_Type::ST_EXT_CYC |
bit: 15 ST_EXT_CYC
| uint32_t { ... } ::ST_EXT_CYC |
bit: 15 ST_EXT_CYC
| __OM uint32_t TimerL_Type::START |
Offset: 0x014 (R/W) SysTick Timer start Register for low 32-bits
| __OM uint32_t TimerH_Type::START |
Offset: 0x014 (R/W) SysTick Timer start Register for high 32-bits
| __IOM uint32_t EU_LOOP_DEMUX_Type::START |
EU_LOOP_DEMUX start register, offset: 0x04
| __OM uint32_t SysTick_Type::START_HI |
Offset: 0x014 (R/W) SysTick Timer start Register for high 32-bits
| __OM uint32_t SysTick_Type::START_LO |
Offset: 0x014 (R/W) SysTick Timer start Register for low 32-bits
| __I uint32_t decompressor_t::STAT_REG |
| __IOM uint32_t EU_LOOP_DEMUX_Type::STATE |
EU_LOOP_DEMUX state register, offset: 0x00
| __IO uint32_t NVIC_Type::STATUS |
FC_ITC Status register, offset: 0x0C
| __IOM uint32_t NVIC_Type::STATUS |
EU_DEMUX Status register, offset: 0x18
| __IOM uint32_t EU_CORE_DEMUX_Type::STATUS |
EU_DEMUX Status register, offset: 0x18
| __IOM uint32_t EU_BARRIER_DEMUX_Type::STATUS |
EU_BARRIER_DEMUX status register, offset: 0x04
| __IOM uint32_t DMAMCHAN_Type::STATUS |
Offset: 0x04 (R/W) DMAMCHAN Channle Status Register
| __IO uint32_t NVIC_Type::STATUS_CLR |
FC_ITC Status clean register, offset: 0x14
| __IO uint32_t NVIC_Type::STATUS_SET |
FC_ITC Status set register, offset: 0x10
| __IOM uint32_t EU_BARRIER_DEMUX_Type::STATUS_SUMMRY |
EU_BARRIER_DEMUX status summary register, offset: 0x08
| uint32_t { ... } ::SUM |
bit: 18 Reserved
| uint32_t { ... } ::SUM |
bit: 18 Reserved
| uint32_t MSTATUS_Type::SUM |
bit: 18 Reserved
| __IOM uint32_t EU_CORE_DEMUX_Type::SW_EVENTS_MASK |
EU_DEMUX software event mask register, offset: 0x2C
| __IOM uint32_t EU_CORE_DEMUX_Type::SW_EVENTS_MASK_AND |
EU_DEMUX software event mask and register, offset: 0x30
| __IOM uint32_t EU_CORE_DEMUX_Type::SW_EVENTS_MASK_OR |
EU_DEMUX software event mask or register, offset: 0x34
| __O uint32_t decompressor_t::SW_RST_REG |
| __O uint32_t decompressor_t::SYMBOL_REG |
| __IOM uint32_t EU_BARRIER_DEMUX_Type::TARGET_MASK |
EU_BARRIER_DEMUX target mask register, offset: 0x0C
| __O uint32_t decompressor_t::TCDM_ADDR |
| __O uint32_t DMAMCHAN_COMPRESSOR_Type::TCDM_ADDRESS |
< Offset: 0x00 (W ) Compressor TCDM Address Register Offset: 0x04 (W ) Compressor L2 Address Register
| uint32_t { ... } ::TCDM_CONT |
bit: 16 TCDM_CONT
| uint32_t PCER_Type::TCDM_CONT |
bit: 16 TCDM_CONT
| uint32_t { ... } ::TCDM_CONT |
bit: 16 TCDM_CONT
| __O uint32_t decompressor_t::TCDM_COUNT_REG |
| __O uint32_t decompressor_t::TCDM_STRIDE_REG |
| __IOM uint32_t EU_DISPATCH_DEMUX_Type::TEAM_CONFIG |
EU_DISPATCH_DEMUX team config register, offset: 0x04
| __IOM uint32_t EU_BARRIER_DEMUX_Type::TRIGGER |
EU_BARRIER_DEMUX trigger register, offset: 0x10
| __IOM uint32_t EU_SW_EVENTS_DEMUX_Type::TRIGGER_CLR |
EU_SW_EVENTS_DEMUX trigger clear register, offset: 0x80
| __IOM uint32_t EU_BARRIER_DEMUX_Type::TRIGGER_MASK |
EU_BARRIER_DEMUX triger mask register, offset: 0x00
| __O uint32_t decompressor_t::TRIGGER_REG |
| __IOM uint32_t EU_SW_EVENTS_DEMUX_Type::TRIGGER_SET |
EU_SW_EVENTS_DEMUX trigger set register, offset: 0x00
| __IOM uint32_t EU_BARRIER_DEMUX_Type::TRIGGER_SET |
EU_BARRIER_DEMUX trigger set register, offset: 0x14
| __IOM uint32_t EU_SW_EVENTS_DEMUX_Type::TRIGGER_WAIT |
EU_SW_EVENTS_DEMUX trigger wait register, offset: 0x40
| __IOM uint32_t EU_BARRIER_DEMUX_Type::TRIGGER_WAIT |
EU_BARRIER_DEMUX trigger wait register, offset: 0x18
| __IOM uint32_t EU_BARRIER_DEMUX_Type::TRIGGER_WAIT_CLEAR |
EU_BARRIER_DEMUX trigger clear register, offset: 0x1C
| uint32_t MSTATUS_Type::TSR |
bit: 22 Reserved
| uint32_t { ... } ::TSR |
bit: 22 Reserved
| uint32_t { ... } ::TSR |
bit: 22 Reserved
| uint32_t MSTATUS_Type::TVM |
bit: 20 Reserved
| uint32_t { ... } ::TVM |
bit: 20 Reserved
| uint32_t { ... } ::TVM |
bit: 20 Reserved
| uint32_t { ... } ::TW |
bit: 21 Reserved
| uint32_t MSTATUS_Type::TW |
bit: 21 Reserved
| uint32_t { ... } ::TW |
bit: 21 Reserved
| uint32_t MSTATUS_Type::UIE |
bit: 0 User Interrupt-enable bit
| uint32_t { ... } ::UIE |
bit: 0 User Interrupt-enable bit
| uint32_t { ... } ::UIE |
bit: 0 User Interrupt-enable bit
| uint32_t { ... } ::UPIE |
bit: 4 Prior User Interrupt-enable bit on trap
| uint32_t { ... } ::UPIE |
bit: 4 Prior User Interrupt-enable bit on trap
| uint32_t MSTATUS_Type::UPIE |
bit: 4 Prior User Interrupt-enable bit on trap
| __IOM uint32_t TimerL_Type::VALUE |
Offset: 0x008 (R/W) TIMERL Timer Value Register for low 32-bits
| __IOM uint32_t TimerH_Type::VALUE |
Offset: 0x00C (R/W) TIMERH Timer Value Register for high 32-bits
| __IOM uint32_t SysTick_Type::VALUE_HI |
Offset: 0x00C (R/W) SysTick Timer Value Register for high 32-bits
| __IOM uint32_t SysTick_Type::VALUE_LO |
Offset: 0x008 (R/W) SysTick Timer Value Register for low 32-bits
| uint32_t MVENDORID_Type::w |
Type used for word access
| uint32_t MHARTID_Type::w |
Type used for word access
| uint32_t MISA_Type::w |
Type used for word access
| uint32_t MSTATUS_Type::w |
Type used for word access
| uint32_t MTVEC_Type::w |
Type used for word access
| uint32_t MCAUSE_Type::w |
Type used for word access
| uint32_t CPRIV_Type::w |
Type used for word access
| uint32_t PCMR_Type::w |
Type used for word access
| uint32_t PCER_Type::w |
Type used for word access
| uint32_t { ... } ::WBRANCH |
bit: 5 WBRANCH
| uint32_t { ... } ::WBRANCH |
bit: 5 WBRANCH
| uint32_t PCER_Type::WBRANCH |
bit: 5 WBRANCH
| uint32_t { ... } ::WBRANCH_CYC |
bit: 6 WBRANCH_CYC
| uint32_t { ... } ::WBRANCH_CYC |
bit: 6 WBRANCH_CYC
| uint32_t PCER_Type::WBRANCH_CYC |
bit: 6 WBRANCH_CYC
| uint32_t MISA_Type::WIRI |
bit: 26..29 Reserved
| uint32_t { ... } ::WIRI |
bit: 26..29 Reserved
| uint32_t { ... } ::WIRI |
bit: 26..29 Reserved
| uint32_t { ... } ::WPRI0 |
bit: 2 Reserved
| uint32_t MSTATUS_Type::WPRI0 |
bit: 2 Reserved
| uint32_t { ... } ::WPRI0 |
bit: 2 Reserved
| uint32_t { ... } ::WPRI1 |
bit: 6 Reserved
| uint32_t { ... } ::WPRI1 |
bit: 6 Reserved
| uint32_t MSTATUS_Type::WPRI1 |
bit: 6 Reserved
| uint32_t { ... } ::WPRI2 |
bit: 9, 10 Reserved
| uint32_t { ... } ::WPRI2 |
bit: 9, 10 Reserved
| uint32_t MSTATUS_Type::WPRI2 |
bit: 9, 10 Reserved
| uint32_t MSTATUS_Type::WPRI3 |
bit: 23..30 Reserved
| uint32_t { ... } ::WPRI3 |
bit: 23..30 Reserved
| uint32_t { ... } ::WPRI3 |
bit: 23..30 Reserved
| uint32_t { ... } ::XS |
bit: 15, 16 Reserved
| uint32_t MSTATUS_Type::XS |
bit: 15, 16 Reserved
| uint32_t { ... } ::XS |
bit: 15, 16 Reserved
