Core Register type definitions. More...

Data Structures
union	MVENDORID_Type
	Union type to access the Vendor ID Register (MVENDORID). More...

union	MHARTID_Type
	Union type to access the Hart ID Register (MHARTID). More...

union	MISA_Type
	Union type to access the ISA and Extensions Register (MISA). More...

union	MSTATUS_Type
	Union type to access the Machine Mode Status Register (MSTATUS). More...

union	MTVEC_Type
	Union type to access the Machine Trap-Vector Baser-Address Register (MTVEC). More...

union	MCAUSE_Type
	Union type to access the Machine Trap Cause Register (MCAUSE). More...

union	CPRIV_Type
	Union type to access the Current Privilege Level Register (CPRIV). More...

union	PCMR_Type
	Union type to access the Performance Counter Mode Register (PCMR). More...

union	PCER_Type
	Union type to access the Performance Counter Event Register (PCER). More...

Macros
#define	MSTATUS_ADDR

#define	MISA_ADDR

#define	MTVEC_ADDR

#define	MEPC_ADDR

#define	MCAUSE_ADDR

#define	MVENDORID_ADDR

#define	MARCHID_ADDR

#define	MIMPID_ADDR

#define	MHARTID_ADDR

#define	PCER_ADDR

#define	PCMR_ADDR

#define	PERF_CYCLE_OFFSET

#define	PERF_INSTR_OFFSET

#define	PERF_LD_STALL_OFFSET

#define	PERF_JR_STALL_OFFSET

#define	PERF_IMISS_OFFSET

#define	PERF_LD_OFFSET

#define	PERF_ST_OFFSET

#define	PERF_JUMP_OFFSET

#define	PERF_BRANCH_OFFSET

#define	PERF_BTAKEN_OFFSET

#define	PERF_RVC_OFFSET

#define	PERF_LD_EXT_OFFSET

#define	PERF_ST_EXT_OFFSET

#define	PERF_LD_EXT_CYC_OFFSET

#define	PERF_ST_EXT_CYC_OFFSET

#define	PERF_TCDM_COUNT_OFFSET

#define	PERF_ALL_OFFSET

#define	PCCR_ADDR(x)

#define	HWLP_S0_ADDR

#define	HWLP_E0_ADDR

#define	HWLP_C0_ADDR

#define	HWLP_S1_ADDR

#define	HWLP_E1_ADDR

#define	HWLP_C1_ADDR

#define	DMHARTID_ADDR

#define	UEPC_ADDR

#define	CPRIV_ADDR

#define	USTATUS_FC_ADDR

#define	UTVEC_FC_ADDR

#define	UCAUSE_FC_ADDR

#define	MVENDORID_BANK_Pos

#define	MVENDORID_BANK_Msk

#define	MVENDORID_OFFSET_Pos

#define	MVENDORID_OFFSET_Msk

#define	MHARTID_BANK_Pos

#define	MHARTID_BANK_Msk

#define	MISA_MXL_Pos

#define	MISA_MXL_Msk

#define	MISA_EXTENSION_Pos

#define	MISA_EXTENSION_Msk

#define	MSTATUS_SD_Pos

#define	MSTATUS_SD_Msk

#define	MSTATUS_TSR_Pos

#define	MSTATUS_TSR_Msk

#define	MSTATUS_TW_Pos

#define	MSTATUS_TW_Msk

#define	MSTATUS_TVM_Pos

#define	MSTATUS_TVM_Msk

#define	MSTATUS_MXR_Pos

#define	MSTATUS_MXR_Msk

#define	MSTATUS_SUM_Pos

#define	MSTATUS_SUM_Msk

#define	MSTATUS_MPRV_Pos

#define	MSTATUS_MPRV_Msk

#define	MSTATUS_XS_Pos

#define	MSTATUS_XS_Msk

#define	MSTATUS_FS_Pos

#define	MSTATUS_FS_Msk

#define	MSTATUS_MPP_Pos

#define	MSTATUS_MPP_Msk

#define	MSTATUS_SPP_Pos

#define	MSTATUS_SPP_Msk

#define	MSTATUS_MPIE_Pos

#define	MSTATUS_MPIE_Msk

#define	MSTATUS_SPIE_Pos

#define	MSTATUS_SPIE_Msk

#define	MSTATUS_UPIE_Pos

#define	MSTATUS_UPIE_Msk

#define	MSTATUS_MIE_Pos

#define	MSTATUS_MIE_Msk

#define	MSTATUS_SIE_Pos

#define	MSTATUS_SIE_Msk

#define	MSTATUS_UIE_Pos

#define	MSTATUS_UIE_Msk

#define	MTVEC_BASE_Pos

#define	MTVEC_BASE_Msk

#define	MTVEC_MODE_Pos

#define	MTVEC_MODE_Msk

#define	MCAUSE_IRQ_Pos

#define	MCAUSE_IRQ_Msk

#define	MCAUSE_EC_Pos

#define	MCAUSE_EC_Msk

#define	CPRIV_PRIV_Pos

#define	CPRIV_PRIV_Msk

#define	PCMR_GLBEN_Pos

#define	PCMR_GLBEN_Msk

#define	PCMR_SATU_Pos

#define	PCMR_SATU_Msk

#define	PCER_CYCLE_Pos

#define	PCER_CYCLE_Msk

#define	PCER_INSTR_Pos

#define	PCER_INSTR_Msk

#define	PCER_LD_STALL_Pos

#define	PCER_LD_STALL_Msk

#define	PCER_JMP_STALL_Pos

#define	PCER_JMP_STALL_Msk

#define	PCER_IMISS_Pos

#define	PCER_IMISS_Msk

#define	PCER_WBRANCH_Pos

#define	PCER_WBRANCH_Msk

#define	PCER_WBRANCH_CYC_Pos

#define	PCER_WBRANCH_CYC_Msk

#define	PCER_LD_Pos

#define	PCER_LD_Msk

#define	PCER_ST_Pos

#define	PCER_ST_Msk

#define	PCER_JUMP_Pos

#define	PCER_JUMP_Msk

#define	PCER_BRANCH_Pos

#define	PCER_BRANCH_Msk

#define	PCER_DELAY_SLOT_Pos

#define	PCER_DELAY_SLOT_Msk

#define	PCER_LD_EXT_Pos

#define	PCER_LD_EXT_Msk

#define	PCER_ST_EXT_Pos

#define	PCER_ST_EXT_Msk

#define	PCER_LD_EXT_CYC_Pos

#define	PCER_LD_EXT_CYC_Msk

#define	PCER_ST_EXT_CYC_Pos

#define	PCER_ST_EXT_CYC_Msk

#define	PCER_TCDM_CONT_Pos

#define	PCER_TCDM_CONT_Msk

#define	PCER_EVENTS_NUM

#define	MSTATUS_ADDR

#define	MISA_ADDR

#define	MTVEC_ADDR

#define	MEPC_ADDR

#define	MCAUSE_ADDR

#define	MVENDORID_ADDR

#define	MARCHID_ADDR

#define	MIMPID_ADDR

#define	MHARTID_ADDR

#define	PCER_ADDR

#define	PCMR_ADDR

#define	PERF_CYCLE_OFFSET

#define	PERF_INSTR_OFFSET

#define	PERF_LD_STALL_OFFSET

#define	PERF_JR_STALL_OFFSET

#define	PERF_IMISS_OFFSET

#define	PERF_LD_OFFSET

#define	PERF_ST_OFFSET

#define	PERF_JUMP_OFFSET

#define	PERF_BRANCH_OFFSET

#define	PERF_BTAKEN_OFFSET

#define	PERF_RVC_OFFSET

#define	PERF_LD_EXT_OFFSET

#define	PERF_ST_EXT_OFFSET

#define	PERF_LD_EXT_CYC_OFFSET

#define	PERF_ST_EXT_CYC_OFFSET

#define	PERF_TCDM_COUNT_OFFSET

#define	PERF_ALL_OFFSET

#define	PCCR_ADDR(x)

#define	HWLP_S0_ADDR

#define	HWLP_E0_ADDR

#define	HWLP_C0_ADDR

#define	HWLP_S1_ADDR

#define	HWLP_E1_ADDR

#define	HWLP_C1_ADDR

#define	DMHARTID_ADDR

#define	UEPC_ADDR

#define	CPRIV_ADDR

#define	USTATUS_FC_ADDR

#define	UTVEC_FC_ADDR

#define	UCAUSE_FC_ADDR

#define	MVENDORID_BANK_Pos

#define	MVENDORID_BANK_Msk

#define	MVENDORID_OFFSET_Pos

#define	MVENDORID_OFFSET_Msk

#define	MHARTID_BANK_Pos

#define	MHARTID_BANK_Msk

#define	MISA_MXL_Pos

#define	MISA_MXL_Msk

#define	MISA_EXTENSION_Pos

#define	MISA_EXTENSION_Msk

#define	MSTATUS_SD_Pos

#define	MSTATUS_SD_Msk

#define	MSTATUS_TSR_Pos

#define	MSTATUS_TSR_Msk

#define	MSTATUS_TW_Pos

#define	MSTATUS_TW_Msk

#define	MSTATUS_TVM_Pos

#define	MSTATUS_TVM_Msk

#define	MSTATUS_MXR_Pos

#define	MSTATUS_MXR_Msk

#define	MSTATUS_SUM_Pos

#define	MSTATUS_SUM_Msk

#define	MSTATUS_MPRV_Pos

#define	MSTATUS_MPRV_Msk

#define	MSTATUS_XS_Pos

#define	MSTATUS_XS_Msk

#define	MSTATUS_FS_Pos

#define	MSTATUS_FS_Msk

#define	MSTATUS_MPP_Pos

#define	MSTATUS_MPP_Msk

#define	MSTATUS_SPP_Pos

#define	MSTATUS_SPP_Msk

#define	MSTATUS_MPIE_Pos

#define	MSTATUS_MPIE_Msk

#define	MSTATUS_SPIE_Pos

#define	MSTATUS_SPIE_Msk

#define	MSTATUS_UPIE_Pos

#define	MSTATUS_UPIE_Msk

#define	MSTATUS_MIE_Pos

#define	MSTATUS_MIE_Msk

#define	MSTATUS_SIE_Pos

#define	MSTATUS_SIE_Msk

#define	MSTATUS_UIE_Pos

#define	MSTATUS_UIE_Msk

#define	MTVEC_BASE_Pos

#define	MTVEC_BASE_Msk

#define	MTVEC_MODE_Pos

#define	MTVEC_MODE_Msk

#define	MCAUSE_IRQ_Pos

#define	MCAUSE_IRQ_Msk

#define	MCAUSE_EC_Pos

#define	MCAUSE_EC_Msk

#define	CPRIV_PRIV_Pos

#define	CPRIV_PRIV_Msk

#define	PCMR_GLBEN_Pos

#define	PCMR_GLBEN_Msk

#define	PCMR_SATU_Pos

#define	PCMR_SATU_Msk

#define	PCER_CYCLE_Pos

#define	PCER_CYCLE_Msk

#define	PCER_INSTR_Pos

#define	PCER_INSTR_Msk

#define	PCER_LD_STALL_Pos

#define	PCER_LD_STALL_Msk

#define	PCER_JMP_STALL_Pos

#define	PCER_JMP_STALL_Msk

#define	PCER_IMISS_Pos

#define	PCER_IMISS_Msk

#define	PCER_WBRANCH_Pos

#define	PCER_WBRANCH_Msk

#define	PCER_WBRANCH_CYC_Pos

#define	PCER_WBRANCH_CYC_Msk

#define	PCER_LD_Pos

#define	PCER_LD_Msk

#define	PCER_ST_Pos

#define	PCER_ST_Msk

#define	PCER_JUMP_Pos

#define	PCER_JUMP_Msk

#define	PCER_BRANCH_Pos

#define	PCER_BRANCH_Msk

#define	PCER_DELAY_SLOT_Pos

#define	PCER_DELAY_SLOT_Msk

#define	PCER_LD_EXT_Pos

#define	PCER_LD_EXT_Msk

#define	PCER_ST_EXT_Pos

#define	PCER_ST_EXT_Msk

#define	PCER_LD_EXT_CYC_Pos

#define	PCER_LD_EXT_CYC_Msk

#define	PCER_ST_EXT_CYC_Pos

#define	PCER_ST_EXT_CYC_Msk

#define	PCER_TCDM_CONT_Pos

#define	PCER_TCDM_CONT_Msk

#define	PCER_EVENTS_NUM

Description

Macro Definition Documentation

#define CPRIV_ADDR

Current Privilege Level Register

#define CPRIV_ADDR

Current Privilege Level Register

#define CPRIV_PRIV_Msk

CPRIV: PRIV Mask

Referenced by __NVIC_GetVector(), and __NVIC_SetVector().

#define CPRIV_PRIV_Msk

CPRIV: PRIV Mask

Referenced by __NVIC_GetVector(), and __NVIC_SetVector().

#define CPRIV_PRIV_Pos

CPRIV: PRIV Position

#define CPRIV_PRIV_Pos

CPRIV: PRIV Position

#define DMHARTID_ADDR

User Unique Hardware Thread ID Register

#define DMHARTID_ADDR

User Unique Hardware Thread ID Register

#define HWLP_C0_ADDR

Hardware Loop Count0 Register

#define HWLP_C0_ADDR

Hardware Loop Count0 Register

#define HWLP_C1_ADDR

Hardware Loop Count1 Register

#define HWLP_C1_ADDR

Hardware Loop Count1 Register

#define HWLP_E0_ADDR

Hardware Loop End0 Register

#define HWLP_E0_ADDR

Hardware Loop End0 Register

#define HWLP_E1_ADDR

Hardware Loop End1 Register

#define HWLP_E1_ADDR

Hardware Loop End1 Register

#define HWLP_S0_ADDR

Hardware Loop Start0 Register

#define HWLP_S0_ADDR

Hardware Loop Start0 Register

#define HWLP_S1_ADDR

Hardware Loop Start1 Register

#define HWLP_S1_ADDR

Hardware Loop Start1 Register

#define MARCHID_ADDR

Architecture ID Register

#define MARCHID_ADDR

Architecture ID Register

#define MCAUSE_ADDR

Machine Trap Cause Register

#define MCAUSE_ADDR

Machine Trap Cause Register

#define MCAUSE_EC_Msk

MCAUSE: EC Mask

#define MCAUSE_EC_Msk

MCAUSE: EC Mask

#define MCAUSE_EC_Pos

MCAUSE: EC Position

#define MCAUSE_EC_Pos

MCAUSE: EC Position

#define MCAUSE_IRQ_Msk

MCAUSE: IRQ Mask

Referenced by __is_irq_mode(), and __os_native_api_sem_take().

#define MCAUSE_IRQ_Msk

MCAUSE: IRQ Mask

#define MCAUSE_IRQ_Pos

MCAUSE: IRQ Position

#define MCAUSE_IRQ_Pos

MCAUSE: IRQ Position

#define MEPC_ADDR

Machine Exception Program Counter Register

#define MEPC_ADDR

Machine Exception Program Counter Register

#define MHARTID_ADDR

Hardware Thread ID Register

#define MHARTID_ADDR

Hardware Thread ID Register

#define MHARTID_BANK_Msk

MHARTID: BANK Mask

#define MHARTID_BANK_Msk

MHARTID: BANK Mask

#define MHARTID_BANK_Pos

MHARTID: BANK Position

#define MHARTID_BANK_Pos

MHARTID: BANK Position

#define MIMPID_ADDR

Implementation ID Register

#define MIMPID_ADDR

Implementation ID Register

#define MISA_ADDR

ISA and Extensions Register

#define MISA_ADDR

ISA and Extensions Register

#define MISA_EXTENSION_Msk

MISA: EXTENSION Mask

#define MISA_EXTENSION_Msk

MISA: EXTENSION Mask

#define MISA_EXTENSION_Pos

MISA: EXTENSION Position

#define MISA_EXTENSION_Pos

MISA: EXTENSION Position

#define MISA_MXL_Msk

MISA: MXL Mask

#define MISA_MXL_Msk

MISA: MXL Mask

#define MISA_MXL_Pos

MISA: MXL Position

#define MISA_MXL_Pos

MISA: MXL Position

#define MSTATUS_ADDR

Mahcine Status Register

#define MSTATUS_ADDR

Mahcine Status Register

#define MSTATUS_FS_Msk

MSTATUS: FS Mask

#define MSTATUS_FS_Msk

MSTATUS: FS Mask

#define MSTATUS_FS_Pos

MSTATUS: FS Position

#define MSTATUS_FS_Pos

MSTATUS: FS Position

#define MSTATUS_MIE_Msk

MSTATUS: MIE Mask

#define MSTATUS_MIE_Msk

MSTATUS: MIE Mask

#define MSTATUS_MIE_Pos

MSTATUS: MIE Position

#define MSTATUS_MIE_Pos

MSTATUS: MIE Position

#define MSTATUS_MPIE_Msk

MSTATUS: MPIE Mask

#define MSTATUS_MPIE_Msk

MSTATUS: MPIE Mask

#define MSTATUS_MPIE_Pos

MSTATUS: MPIE Position

#define MSTATUS_MPIE_Pos

MSTATUS: MPIE Position

#define MSTATUS_MPP_Msk

MSTATUS: MPP Mask

#define MSTATUS_MPP_Msk

MSTATUS: MPP Mask

#define MSTATUS_MPP_Pos

MSTATUS: MPP Position

#define MSTATUS_MPP_Pos

MSTATUS: MPP Position

#define MSTATUS_MPRV_Msk

MSTATUS: MPRV Mask

#define MSTATUS_MPRV_Msk

MSTATUS: MPRV Mask

#define MSTATUS_MPRV_Pos

MSTATUS: MPRV Position

#define MSTATUS_MPRV_Pos

MSTATUS: MPRV Position

#define MSTATUS_MXR_Msk

MSTATUS: MXR Mask

#define MSTATUS_MXR_Msk

MSTATUS: MXR Mask

#define MSTATUS_MXR_Pos

MSTATUS: MXR Position

#define MSTATUS_MXR_Pos

MSTATUS: MXR Position

#define MSTATUS_SD_Msk

MSTATUS: SD Mask

#define MSTATUS_SD_Msk

MSTATUS: SD Mask

#define MSTATUS_SD_Pos

MSTATUS: SD Position

#define MSTATUS_SD_Pos

MSTATUS: SD Position

#define MSTATUS_SIE_Msk

MSTATUS: SIE Mask

#define MSTATUS_SIE_Msk

MSTATUS: SIE Mask

#define MSTATUS_SIE_Pos

MSTATUS: SIE Position

#define MSTATUS_SIE_Pos

MSTATUS: SIE Position

#define MSTATUS_SPIE_Msk

MSTATUS: SPIE Mask

#define MSTATUS_SPIE_Msk

MSTATUS: SPIE Mask

#define MSTATUS_SPIE_Pos

MSTATUS: SPIE Position

#define MSTATUS_SPIE_Pos

MSTATUS: SPIE Position

#define MSTATUS_SPP_Msk

MSTATUS: SPP Mask

#define MSTATUS_SPP_Msk

MSTATUS: SPP Mask

#define MSTATUS_SPP_Pos

MSTATUS: SPP Position

#define MSTATUS_SPP_Pos

MSTATUS: SPP Position

#define MSTATUS_SUM_Msk

MSTATUS: SUM Mask

#define MSTATUS_SUM_Msk

MSTATUS: SUM Mask

#define MSTATUS_SUM_Pos

MSTATUS: SUM Position

#define MSTATUS_SUM_Pos

MSTATUS: SUM Position

#define MSTATUS_TSR_Msk

MSTATUS: TSR Mask

#define MSTATUS_TSR_Msk

MSTATUS: TSR Mask

#define MSTATUS_TSR_Pos

MSTATUS: TSR Position

#define MSTATUS_TSR_Pos

MSTATUS: TSR Position

#define MSTATUS_TVM_Msk

MSTATUS: TVM Mask

#define MSTATUS_TVM_Msk

MSTATUS: TVM Mask

#define MSTATUS_TVM_Pos

MSTATUS: TVM Position

#define MSTATUS_TVM_Pos

MSTATUS: TVM Position

#define MSTATUS_TW_Msk

MSTATUS: TW Mask

#define MSTATUS_TW_Msk

MSTATUS: TW Mask

#define MSTATUS_TW_Pos

MSTATUS: TW Position

#define MSTATUS_TW_Pos

MSTATUS: TW Position

#define MSTATUS_UIE_Msk

MSTATUS: UIE Mask

#define MSTATUS_UIE_Msk

MSTATUS: UIE Mask

#define MSTATUS_UIE_Pos

MSTATUS: UIE Position

#define MSTATUS_UIE_Pos

MSTATUS: UIE Position

#define MSTATUS_UPIE_Msk

MSTATUS: UPIE Mask

#define MSTATUS_UPIE_Msk

MSTATUS: UPIE Mask

#define MSTATUS_UPIE_Pos

MSTATUS: UPIE Position

#define MSTATUS_UPIE_Pos

MSTATUS: UPIE Position

#define MSTATUS_XS_Msk

MSTATUS: XS Mask

#define MSTATUS_XS_Msk

MSTATUS: XS Mask

#define MSTATUS_XS_Pos

MSTATUS: XS Position

#define MSTATUS_XS_Pos

MSTATUS: XS Position

#define MTVEC_ADDR

Machine Trap-handler Base Address Register

#define MTVEC_ADDR

Machine Trap-handler Base Address Register

#define MTVEC_BASE_Msk

MTVEC: BASE Mask

#define MTVEC_BASE_Msk

MTVEC: BASE Mask

#define MTVEC_BASE_Pos

MTVEC: BASE Position

#define MTVEC_BASE_Pos

MTVEC: BASE Position

#define MTVEC_MODE_Msk

MTVEC: MODE Mask

#define MTVEC_MODE_Msk

MTVEC: MODE Mask

#define MTVEC_MODE_Pos

MTVEC: MODE Position

#define MTVEC_MODE_Pos

MTVEC: MODE Position

#define MVENDORID_ADDR

Vendor ID Register

#define MVENDORID_ADDR

Vendor ID Register

#define MVENDORID_BANK_Msk

MVENDORID: BANK Mask

#define MVENDORID_BANK_Msk

MVENDORID: BANK Mask

#define MVENDORID_BANK_Pos

MVENDORID: BANK Position

#define MVENDORID_BANK_Pos

MVENDORID: BANK Position

#define MVENDORID_OFFSET_Msk

MVENDORID: OFFSET Mask

#define MVENDORID_OFFSET_Msk

MVENDORID: OFFSET Mask

#define MVENDORID_OFFSET_Pos

MVENDORID: OFFSET Position

#define MVENDORID_OFFSET_Pos

MVENDORID: OFFSET Position

#define PCCR_ADDR ( x )

Performance Counter Counter access

#define PCCR_ADDR ( x )

Performance Counter Counter access

#define PCER_ADDR

Performance Counter Mode Register

#define PCER_ADDR

Performance Counter Mode Register

#define PCER_BRANCH_Msk

PCER: BRANCH Mask

#define PCER_BRANCH_Msk

PCER: BRANCH Mask

#define PCER_BRANCH_Pos

PCER: BRANCH Position

#define PCER_BRANCH_Pos

PCER: BRANCH Position

#define PCER_CYCLE_Msk

PCER: CYCLE Mask

#define PCER_CYCLE_Msk

PCER: CYCLE Mask

#define PCER_CYCLE_Pos

PCER: CYCLE Position

#define PCER_CYCLE_Pos

PCER: CYCLE Position

#define PCER_DELAY_SLOT_Msk

PCER: DELAY_SLOT Mask

#define PCER_DELAY_SLOT_Msk

PCER: DELAY_SLOT Mask

#define PCER_DELAY_SLOT_Pos

PCER: DELAY_SLOT Position

#define PCER_DELAY_SLOT_Pos

PCER: DELAY_SLOT Position

#define PCER_EVENTS_NUM

PCER: All events number

#define PCER_EVENTS_NUM

PCER: All events number

#define PCER_IMISS_Msk

PCER: IMISS Mask

#define PCER_IMISS_Msk

PCER: IMISS Mask

#define PCER_IMISS_Pos

PCER: IMISS Position

#define PCER_IMISS_Pos

PCER: IMISS Position

#define PCER_INSTR_Msk

PCER: _INSTR Mask

#define PCER_INSTR_Msk

PCER: _INSTR Mask

#define PCER_INSTR_Pos

PCER: _INSTR Position

#define PCER_INSTR_Pos

PCER: _INSTR Position

#define PCER_JMP_STALL_Msk

PCER: JMP_STALL Mask

#define PCER_JMP_STALL_Msk

PCER: JMP_STALL Mask

#define PCER_JMP_STALL_Pos

PCER: JMP_STALL Position

#define PCER_JMP_STALL_Pos

PCER: JMP_STALL Position

#define PCER_JUMP_Msk

PCER: JUMP Mask

#define PCER_JUMP_Msk

PCER: JUMP Mask

#define PCER_JUMP_Pos

PCER: JUMP Position

#define PCER_JUMP_Pos

PCER: JUMP Position

#define PCER_LD_EXT_CYC_Msk

PCER: LD_EXT_CYC Mask

#define PCER_LD_EXT_CYC_Msk

PCER: LD_EXT_CYC Mask

#define PCER_LD_EXT_CYC_Pos

PCER: LD_EXT_CYC Position

#define PCER_LD_EXT_CYC_Pos

PCER: LD_EXT_CYC Position

#define PCER_LD_EXT_Msk

PCER: LD_EXT Mask

#define PCER_LD_EXT_Msk

PCER: LD_EXT Mask

#define PCER_LD_EXT_Pos

PCER: LD_EXT Position

#define PCER_LD_EXT_Pos

PCER: LD_EXT Position

#define PCER_LD_Msk

PCER: LD Mask

#define PCER_LD_Msk

PCER: LD Mask

#define PCER_LD_Pos

PCER: LD Position

#define PCER_LD_Pos

PCER: LD Position

#define PCER_LD_STALL_Msk

PCER: LD_STALL Mask

#define PCER_LD_STALL_Msk

PCER: LD_STALL Mask

#define PCER_LD_STALL_Pos

PCER: LD_STALL Position

#define PCER_LD_STALL_Pos

PCER: LD_STALL Position

#define PCER_ST_EXT_CYC_Msk

PCER: ST_EXT_CYC Mask

#define PCER_ST_EXT_CYC_Msk

PCER: ST_EXT_CYC Mask

#define PCER_ST_EXT_CYC_Pos

PCER: ST_EXT_CYC Position

#define PCER_ST_EXT_CYC_Pos

PCER: ST_EXT_CYC Position

#define PCER_ST_EXT_Msk

PCER: ST_EXT Mask

#define PCER_ST_EXT_Msk

PCER: ST_EXT Mask

#define PCER_ST_EXT_Pos

PCER: ST_EXT Position

#define PCER_ST_EXT_Pos

PCER: ST_EXT Position

#define PCER_ST_Msk

PCER: ST Mask

#define PCER_ST_Msk

PCER: ST Mask

#define PCER_ST_Pos

PCER: ST Position

#define PCER_ST_Pos

PCER: ST Position

#define PCER_TCDM_CONT_Msk

PCER: TCDM_CONT Mask

#define PCER_TCDM_CONT_Msk

PCER: TCDM_CONT Mask

#define PCER_TCDM_CONT_Pos

PCER: TCDM_CONT Position

#define PCER_TCDM_CONT_Pos

PCER: TCDM_CONT Position

#define PCER_WBRANCH_CYC_Msk

PCER: WBRANCH_CYC Mask

#define PCER_WBRANCH_CYC_Msk

PCER: WBRANCH_CYC Mask

#define PCER_WBRANCH_CYC_Pos

PCER: WBRANCH_CYC Position

#define PCER_WBRANCH_CYC_Pos

PCER: WBRANCH_CYC Position

#define PCER_WBRANCH_Msk

PCER: WBRANCH Mask

#define PCER_WBRANCH_Msk

PCER: WBRANCH Mask

#define PCER_WBRANCH_Pos

PCER: WBRANCH Position

#define PCER_WBRANCH_Pos

PCER: WBRANCH Position

#define PCMR_ADDR

Performance Counter Event Register

#define PCMR_ADDR

Performance Counter Event Register

#define PCMR_GLBEN_Msk

PCMR: GLBEN Mask

#define PCMR_GLBEN_Msk

PCMR: GLBEN Mask

#define PCMR_GLBEN_Pos

PCMR: GLBEN Position

#define PCMR_GLBEN_Pos

PCMR: GLBEN Position

#define PCMR_SATU_Msk

PCMR: SATU Mask

#define PCMR_SATU_Msk

PCMR: SATU Mask

#define PCMR_SATU_Pos

PCMR: SATU Position

#define PCMR_SATU_Pos

PCMR: SATU Position

#define PERF_ALL_OFFSET

Performance Counter Counter ALL Register, used to reset all counters

#define PERF_ALL_OFFSET

Performance Counter Counter ALL Register, used to reset all counters

#define PERF_BRANCH_OFFSET

Performance Counter Counter BRANCH Register

#define PERF_BRANCH_OFFSET

Performance Counter Counter BRANCH Register

#define PERF_BTAKEN_OFFSET

Performance Counter Counter BTAKEN Register

#define PERF_BTAKEN_OFFSET

Performance Counter Counter BTAKEN Register

#define PERF_CYCLE_OFFSET

Performance Counter Counter CYCLE Register

#define PERF_CYCLE_OFFSET

Performance Counter Counter CYCLE Register

#define PERF_IMISS_OFFSET

Performance Counter Counter IMISS Register

#define PERF_IMISS_OFFSET

Performance Counter Counter IMISS Register

#define PERF_INSTR_OFFSET

Performance Counter Counter INSTR Register

#define PERF_INSTR_OFFSET

Performance Counter Counter INSTR Register

#define PERF_JR_STALL_OFFSET

Performance Counter Counter JR_STALL Register

#define PERF_JR_STALL_OFFSET

Performance Counter Counter JR_STALL Register

#define PERF_JUMP_OFFSET

Performance Counter Counter JUMP Register

#define PERF_JUMP_OFFSET

Performance Counter Counter JUMP Register

#define PERF_LD_EXT_CYC_OFFSET

Performance Counter Counter LD_EXT_CYC Register

#define PERF_LD_EXT_CYC_OFFSET

Performance Counter Counter LD_EXT_CYC Register

#define PERF_LD_EXT_OFFSET

Performance Counter Counter LD_EXT Register

#define PERF_LD_EXT_OFFSET

Performance Counter Counter LD_EXT Register

#define PERF_LD_OFFSET

Performance Counter Counter LD Register

#define PERF_LD_OFFSET

Performance Counter Counter LD Register

#define PERF_LD_STALL_OFFSET

Performance Counter Counter LD_STALL Register

#define PERF_LD_STALL_OFFSET

Performance Counter Counter LD_STALL Register

#define PERF_RVC_OFFSET

Performance Counter Counter RVC Register

#define PERF_RVC_OFFSET

Performance Counter Counter RVC Register

#define PERF_ST_EXT_CYC_OFFSET

Performance Counter Counter ST_EXT_CYC Register

#define PERF_ST_EXT_CYC_OFFSET

Performance Counter Counter ST_EXT_CYC Register

#define PERF_ST_EXT_OFFSET

Performance Counter Counter ST_EXT Register

#define PERF_ST_EXT_OFFSET

Performance Counter Counter ST_EXT Register

#define PERF_ST_OFFSET

Performance Counter Counter ST Register

#define PERF_ST_OFFSET

Performance Counter Counter ST Register

#define PERF_TCDM_COUNT_OFFSET

Performance Counter Counter TCDM_CONT Register

#define PERF_TCDM_COUNT_OFFSET

Performance Counter Counter TCDM_CONT Register

#define UCAUSE_FC_ADDR

FC User Trap Cause Register

#define UCAUSE_FC_ADDR

FC User Trap Cause Register

#define UEPC_ADDR

User Exception Program Counter Register

#define UEPC_ADDR

User Exception Program Counter Register

#define USTATUS_FC_ADDR

FC User Status Register

#define USTATUS_FC_ADDR

FC User Status Register

#define UTVEC_FC_ADDR

FC User Trap-handler Base Address Register

#define UTVEC_FC_ADDR

FC User Trap-handler Base Address Register

Data Structures

Macros

Description

Macro Definition Documentation