 |
FreeRTOS port on GAP8/RISC-V
|
 |
Macros | |
| #define | GAP_WRITE_VOL(base, offset, value) |
| #define | GAP_WRITE(base, offset, value) |
| #define | GAP_READ(base, offset) |
| #define | GAP_BINSERT(dst, src, size, off) |
| #define | GAP_BINSERT_R(dst, src, size, off) |
| #define | GAP_BEXTRACTU(src, size, off) |
| #define | GAP_BEXTRACT(src, size, off) |
Functions | |
| static unsigned int | __attribute__ ((always_inline)) ExtInsMaskFast_archi(unsigned int Size |
Variables | |
| static unsigned int unsigned int | Offset |
| #define GAP_BEXTRACT | ( | src, | |
| size, | |||
| off | |||
| ) |
Referenced by adv_timer_cg_ena_gets(), adv_timer_ch_mux_ch_sel_0_gets(), adv_timer_ch_mux_ch_sel_1_gets(), adv_timer_ch_mux_ch_sel_2_gets(), adv_timer_ch_mux_ch_sel_3_gets(), adv_timer_ch_mux_ch_sel_4_gets(), adv_timer_ch_mux_ch_sel_5_gets(), adv_timer_ch_mux_ch_sel_6_gets(), adv_timer_ch_mux_ch_sel_7_gets(), adv_timer_event_cfg_ena_gets(), adv_timer_event_cfg_sel0_gets(), adv_timer_event_cfg_sel1_gets(), adv_timer_event_cfg_sel2_gets(), adv_timer_event_cfg_sel3_gets(), adv_timer_t0_cmd_arm_gets(), adv_timer_t0_cmd_reset_gets(), adv_timer_t0_cmd_rfu_gets(), adv_timer_t0_cmd_start_gets(), adv_timer_t0_cmd_stop_gets(), adv_timer_t0_cmd_update_gets(), adv_timer_t0_config_clksel_gets(), adv_timer_t0_config_insel_gets(), adv_timer_t0_config_mode_gets(), adv_timer_t0_config_presc_gets(), adv_timer_t0_config_updownsel_gets(), adv_timer_t0_counter_counter_gets(), adv_timer_t0_th_channel0_mode_gets(), adv_timer_t0_th_channel0_th_gets(), adv_timer_t0_th_channel1_mode_gets(), adv_timer_t0_th_channel1_th_gets(), adv_timer_t0_th_channel2_mode_gets(), adv_timer_t0_th_channel2_th_gets(), adv_timer_t0_th_channel3_mode_gets(), adv_timer_t0_th_channel3_th_gets(), adv_timer_t0_threshold_th_hi_gets(), adv_timer_t0_threshold_th_lo_gets(), adv_timer_t1_cmd_arm_gets(), adv_timer_t1_cmd_reset_gets(), adv_timer_t1_cmd_start_gets(), adv_timer_t1_cmd_stop_gets(), adv_timer_t1_cmd_update_gets(), adv_timer_t1_config_clksel_gets(), adv_timer_t1_config_insel_gets(), adv_timer_t1_config_mode_gets(), adv_timer_t1_config_presc_gets(), adv_timer_t1_config_updownsel_gets(), adv_timer_t1_counter_counter_gets(), adv_timer_t1_th_channel0_mode_gets(), adv_timer_t1_th_channel0_th_gets(), adv_timer_t1_th_channel1_mode_gets(), adv_timer_t1_th_channel1_th_gets(), adv_timer_t1_th_channel2_mode_gets(), adv_timer_t1_th_channel2_th_gets(), adv_timer_t1_th_channel3_mode_gets(), adv_timer_t1_th_channel3_th_gets(), adv_timer_t1_threshold_th_hi_gets(), adv_timer_t1_threshold_th_lo_gets(), adv_timer_t2_cmd_arm_gets(), adv_timer_t2_cmd_reset_gets(), adv_timer_t2_cmd_start_gets(), adv_timer_t2_cmd_stop_gets(), adv_timer_t2_cmd_update_gets(), adv_timer_t2_config_clksel_gets(), adv_timer_t2_config_insel_gets(), adv_timer_t2_config_mode_gets(), adv_timer_t2_config_presc_gets(), adv_timer_t2_config_updownsel_gets(), adv_timer_t2_counter_counter_gets(), adv_timer_t2_th_channel0_mode_gets(), adv_timer_t2_th_channel0_th_gets(), adv_timer_t2_th_channel1_mode_gets(), adv_timer_t2_th_channel1_th_gets(), adv_timer_t2_th_channel2_mode_gets(), adv_timer_t2_th_channel2_th_gets(), adv_timer_t2_th_channel3_mode_gets(), adv_timer_t2_th_channel3_th_gets(), adv_timer_t2_threshold_th_hi_gets(), adv_timer_t2_threshold_th_lo_gets(), adv_timer_t3_cmd_arm_gets(), adv_timer_t3_cmd_reset_gets(), adv_timer_t3_cmd_start_gets(), adv_timer_t3_cmd_stop_gets(), adv_timer_t3_cmd_update_gets(), adv_timer_t3_config_clksel_gets(), adv_timer_t3_config_insel_gets(), adv_timer_t3_config_mode_gets(), adv_timer_t3_config_presc_gets(), adv_timer_t3_config_updownsel_gets(), adv_timer_t3_counter_counter_gets(), adv_timer_t3_th_channel0_mode_gets(), adv_timer_t3_th_channel0_th_gets(), adv_timer_t3_th_channel1_mode_gets(), adv_timer_t3_th_channel1_th_gets(), adv_timer_t3_th_channel2_mode_gets(), adv_timer_t3_th_channel2_th_gets(), adv_timer_t3_th_channel3_mode_gets(), adv_timer_t3_th_channel3_th_gets(), adv_timer_t3_threshold_th_hi_gets(), adv_timer_t3_threshold_th_lo_gets(), decompressor_clock_enable_reg_clock_enable_gets(), decompressor_conf_reg_decompr_direction_gets(), decompressor_conf_reg_decompr_mode_gets(), decompressor_conf_reg_extension_type_gets(), decompressor_conf_reg_item_bit_width_gets(), decompressor_conf_reg_item_to_decompress_gets(), decompressor_conf_reg_sign_extension_gets(), decompressor_conf_reg_start_bit_gets(), decompressor_conf_reg_start_byte_gets(), decompressor_l2_count_reg_l2_linear_count_gets(), decompressor_l2_stride_reg_l2_stride_count_gets(), decompressor_lut_write_reg_lut_addr_gets(), decompressor_lut_write_reg_lut_data_gets(), decompressor_mode_reg_transf_mode_gets(), decompressor_push_cmd_reg_trigger_gets(), decompressor_soft_reset_reg_soft_reset_gets(), decompressor_status_reg_status_gets(), decompressor_tcdm_count_reg_tcdm_linear_count_gets(), decompressor_tcdm_stride_reg_tcdm_stride_count_gets(), fll_ccr1_clk0_div_gets(), fll_ccr1_clk1_div_gets(), fll_ccr1_clk2_div_gets(), fll_ccr1_clk3_div_gets(), fll_ccr2_ckg0_gets(), fll_ccr2_ckg1_gets(), fll_ccr2_ckg2_gets(), fll_ccr2_ckg3_gets(), fll_ccr2_clk0_sel_gets(), fll_ccr2_clk1_sel_gets(), fll_ccr2_clk2_sel_gets(), fll_ccr2_clk3_sel_gets(), fll_drr_dco_max_gets(), fll_drr_dco_min_gets(), fll_f0cr1_dco_en_gets(), fll_f0cr1_itg_per_gets(), fll_f0cr1_lock_tol_gets(), fll_f0cr1_loop_gain_gets(), fll_f0cr1_op_mode_gets(), fll_f0cr1_stbl_gets(), fll_f0cr1_ttm_en_gets(), fll_f0cr2_dco_code_gets(), fll_f0cr2_mfi_gets(), fll_f1cr1_dco_en_gets(), fll_f1cr1_itg_per_gets(), fll_f1cr1_lock_tol_gets(), fll_f1cr1_loop_gain_gets(), fll_f1cr1_op_mode_gets(), fll_f1cr1_stbl_gets(), fll_f1cr1_ttm_en_gets(), fll_f1cr2_dco_code_gets(), fll_f1cr2_mfi_gets(), fll_f2cr1_dco_en_gets(), fll_f2cr1_itg_per_gets(), fll_f2cr1_lock_tol_gets(), fll_f2cr1_loop_gain_gets(), fll_f2cr1_op_mode_gets(), fll_f2cr1_stbl_gets(), fll_f2cr1_ttm_en_gets(), fll_f2cr2_dco_code_gets(), fll_f2cr2_mfi_gets(), fll_f3cr1_dco_en_gets(), fll_f3cr1_itg_per_gets(), fll_f3cr1_lock_tol_gets(), fll_f3cr1_loop_gain_gets(), fll_f3cr1_op_mode_gets(), fll_f3cr1_stbl_gets(), fll_f3cr1_ttm_en_gets(), fll_f3cr2_dco_code_gets(), fll_f3cr2_mfi_gets(), fll_fsr_clmp_hi_err0_gets(), fll_fsr_clmp_hi_err1_gets(), fll_fsr_clmp_hi_err2_gets(), fll_fsr_clmp_hi_err3_gets(), fll_fsr_clmp_lo_err0_gets(), fll_fsr_clmp_lo_err1_gets(), fll_fsr_clmp_lo_err2_gets(), fll_fsr_clmp_lo_err3_gets(), fll_fsr_fdc_sat_err0_gets(), fll_fsr_fdc_sat_err1_gets(), fll_fsr_fdc_sat_err2_gets(), fll_fsr_fdc_sat_err3_gets(), fll_fsr_lock0_gets(), fll_fsr_lock1_gets(), fll_fsr_lock2_gets(), fll_fsr_lock3_gets(), fll_ttr_refresh_gets(), gpio_padcfg_00_03_padcfg_gets(), gpio_padcfg_04_07_padcfg_gets(), gpio_padcfg_08_11_padcfg_gets(), gpio_padcfg_12_15_padcfg_gets(), gpio_padcfg_16_19_padcfg_gets(), gpio_padcfg_20_23_padcfg_gets(), gpio_padcfg_24_27_padcfg_gets(), gpio_padcfg_28_31_padcfg_gets(), gpio_padcfg_32_35_padcfg_gets(), gpio_padcfg_36_39_padcfg_gets(), gpio_padcfg_40_43_padcfg_gets(), gpio_padcfg_44_47_padcfg_gets(), gpio_padcfg_48_51_padcfg_gets(), gpio_padcfg_52_55_padcfg_gets(), gpio_padcfg_56_59_padcfg_gets(), gpio_padcfg_60_63_padcfg_gets(), gpio_padcfg_64_67_padcfg_gets(), gpio_padcfg_68_71_padcfg_gets(), gpio_padcfg_72_75_padcfg_gets(), gpio_padcfg_76_79_padcfg_gets(), gpio_padcfg_80_83_padcfg_gets(), gpio_padcfg_84_87_padcfg_gets(), gpio_padcfg_88_91_padcfg_gets(), gpio_padcfg_92_95_padcfg_gets(), udma_aes_cfg_mode_gets(), udma_aes_dest_rx_dest_gets(), udma_aes_dest_tx_dest_gets(), udma_aes_setup_block_rst_gets(), udma_aes_setup_ecb_cbc_gets(), udma_aes_setup_enc_dec_gets(), udma_aes_setup_fifo_clr_gets(), udma_aes_setup_key_init_gets(), udma_aes_setup_key_type_gets(), udma_aes_setup_reserved_gets(), udma_asrc_ctrl_cfg_0_clk_en_gets(), udma_asrc_ctrl_cfg_0_fs_in_gets(), udma_asrc_ctrl_cfg_0_fs_out_gets(), udma_asrc_ctrl_cfg_0_lock_wnd_gets(), udma_asrc_ctrl_cfg_0_rstn_gets(), udma_asrc_ctrl_cfg_1_clk_en_gets(), udma_asrc_ctrl_cfg_1_fs_in_gets(), udma_asrc_ctrl_cfg_1_fs_out_gets(), udma_asrc_ctrl_cfg_1_lock_wnd_gets(), udma_asrc_ctrl_cfg_1_rstn_gets(), udma_asrc_lane_cfg_0_ch_en_gets(), udma_asrc_lane_cfg_0_clk_en_gets(), udma_asrc_lane_cfg_0_ctrl_mux_gets(), udma_asrc_lane_cfg_0_drop_on_wait_gets(), udma_asrc_lane_cfg_0_rstn_gets(), udma_asrc_lane_cfg_0_use_stream_in_gets(), udma_asrc_lane_cfg_0_use_stream_out_gets(), udma_asrc_lane_cfg_0_wait_lock_in_gets(), udma_asrc_lane_cfg_0_wait_lock_out_gets(), udma_asrc_lane_cfg_1_ch_en_gets(), udma_asrc_lane_cfg_1_clk_en_gets(), udma_asrc_lane_cfg_1_ctrl_mux_gets(), udma_asrc_lane_cfg_1_drop_on_wait_gets(), udma_asrc_lane_cfg_1_rstn_gets(), udma_asrc_lane_cfg_1_use_stream_in_gets(), udma_asrc_lane_cfg_1_use_stream_out_gets(), udma_asrc_lane_cfg_1_wait_lock_in_gets(), udma_asrc_lane_cfg_1_wait_lock_out_gets(), udma_asrc_lane_cfg_2_ch_en_gets(), udma_asrc_lane_cfg_2_clk_en_gets(), udma_asrc_lane_cfg_2_ctrl_mux_gets(), udma_asrc_lane_cfg_2_drop_on_wait_gets(), udma_asrc_lane_cfg_2_rstn_gets(), udma_asrc_lane_cfg_2_use_stream_in_gets(), udma_asrc_lane_cfg_2_use_stream_out_gets(), udma_asrc_lane_cfg_2_wait_lock_in_gets(), udma_asrc_lane_cfg_2_wait_lock_out_gets(), udma_asrc_lane_cfg_3_ch_en_gets(), udma_asrc_lane_cfg_3_clk_en_gets(), udma_asrc_lane_cfg_3_ctrl_mux_gets(), udma_asrc_lane_cfg_3_drop_on_wait_gets(), udma_asrc_lane_cfg_3_rstn_gets(), udma_asrc_lane_cfg_3_use_stream_in_gets(), udma_asrc_lane_cfg_3_use_stream_out_gets(), udma_asrc_lane_cfg_3_wait_lock_in_gets(), udma_asrc_lane_cfg_3_wait_lock_out_gets(), udma_asrc_lane_idin_0_id_ch0_gets(), udma_asrc_lane_idin_0_id_ch1_gets(), udma_asrc_lane_idin_0_id_ch2_gets(), udma_asrc_lane_idin_0_id_ch3_gets(), udma_asrc_lane_idin_1_id_ch0_gets(), udma_asrc_lane_idin_1_id_ch1_gets(), udma_asrc_lane_idin_1_id_ch2_gets(), udma_asrc_lane_idin_1_id_ch3_gets(), udma_asrc_lane_idin_2_id_ch0_gets(), udma_asrc_lane_idin_2_id_ch1_gets(), udma_asrc_lane_idin_2_id_ch2_gets(), udma_asrc_lane_idin_2_id_ch3_gets(), udma_asrc_lane_idin_3_id_ch0_gets(), udma_asrc_lane_idin_3_id_ch1_gets(), udma_asrc_lane_idin_3_id_ch2_gets(), udma_asrc_lane_idin_3_id_ch3_gets(), udma_asrc_lane_idout_0_id_ch0_gets(), udma_asrc_lane_idout_0_id_ch1_gets(), udma_asrc_lane_idout_0_id_ch2_gets(), udma_asrc_lane_idout_0_id_ch3_gets(), udma_asrc_lane_idout_1_id_ch0_gets(), udma_asrc_lane_idout_1_id_ch1_gets(), udma_asrc_lane_idout_1_id_ch2_gets(), udma_asrc_lane_idout_1_id_ch3_gets(), udma_asrc_lane_idout_2_id_ch0_gets(), udma_asrc_lane_idout_2_id_ch1_gets(), udma_asrc_lane_idout_2_id_ch2_gets(), udma_asrc_lane_idout_2_id_ch3_gets(), udma_asrc_lane_idout_3_id_ch0_gets(), udma_asrc_lane_idout_3_id_ch1_gets(), udma_asrc_lane_idout_3_id_ch2_gets(), udma_asrc_lane_idout_3_id_ch3_gets(), udma_asrc_mem2mem_cfg_ch_en_gets(), udma_asrc_mem2mem_cfg_clk_en_gets(), udma_asrc_mem2mem_cfg_ctx_id_gets(), udma_asrc_mem2mem_cfg_fs_in_gets(), udma_asrc_mem2mem_cfg_fs_out_gets(), udma_asrc_mem2mem_cfg_restore_gets(), udma_asrc_mem2mem_cfg_rstn_gets(), udma_asrc_mem2mem_cfg_store_gets(), udma_asrc_mem2mem_id_m2m_in_ch0_gets(), udma_asrc_mem2mem_id_m2m_in_ch1_gets(), udma_asrc_mem2mem_id_m2m_out_ch0_gets(), udma_asrc_mem2mem_id_m2m_out_ch1_gets(), udma_asrc_mem2mem_ratio_m2m_ratio_en_gets(), udma_asrc_mem2mem_ratio_m2m_ratio_gets(), udma_asrc_status_lock_gets(), udma_core_2d_addrgen_cfg_ctrl_cont_gets(), udma_core_2d_addrgen_cfg_ctrl_en_gets(), udma_core_2d_addrgen_cfg_ctrl_stop_gets(), udma_core_fifo_cfg_ctrl_en_gets(), udma_core_fifo_cfg_ctrl_stop_gets(), udma_core_fifo_cfg_ctrl_timeout_mon_gets(), udma_core_fifo_cfg_evt_en_gets(), udma_core_fifo_cfg_evt_num_bytes_gets(), udma_cpi_cam_cfg_glob_en_gets(), udma_cpi_cam_cfg_glob_format_gets(), udma_cpi_cam_cfg_glob_framedrop_en_gets(), udma_cpi_cam_cfg_glob_framedrop_val_gets(), udma_cpi_cam_cfg_glob_frameslice_en_gets(), udma_cpi_cam_cfg_ll_frameslice_llx_gets(), udma_cpi_cam_cfg_ll_frameslice_lly_gets(), udma_cpi_cam_cfg_rgb_sequence_gets(), udma_cpi_cam_cfg_size_rowlen_gets(), udma_cpi_cam_cfg_ur_frameslice_urx_gets(), udma_cpi_cam_cfg_ur_frameslice_ury_gets(), udma_cpi_cam_hsync_polarity_hsync_polarity_gets(), udma_cpi_cam_rx_datasize_rx_datasize_gets(), udma_cpi_cam_rx_dest_rx_dest_gets(), udma_cpi_cam_vsync_polarity_vsync_polarity_gets(), udma_ctrl_cfg_event_cmp_evt0_gets(), udma_ctrl_cfg_event_cmp_evt1_gets(), udma_ctrl_cfg_event_cmp_evt2_gets(), udma_ctrl_cfg_event_cmp_evt3_gets(), udma_ctrl_datamove0_size_en_gets(), udma_ctrl_datamove0_size_size_gets(), udma_ctrl_datamove0_size_stop_gets(), udma_ctrl_datamove1_size_en_gets(), udma_ctrl_datamove1_size_size_gets(), udma_ctrl_datamove1_size_stop_gets(), udma_ctrl_datamove_cfg_dest_id_0_gets(), udma_ctrl_datamove_cfg_dest_id_1_gets(), udma_ctrl_datamove_cfg_source_id_0_gets(), udma_ctrl_datamove_cfg_source_id_1_gets(), udma_ctrl_fifo_cfg_pop_id_gets(), udma_ctrl_fifo_cfg_push_id_gets(), udma_ctrl_timeout_ch0_cnt_gets(), udma_ctrl_timeout_ch0_en_gets(), udma_ctrl_timeout_ch0_mode_gets(), udma_ctrl_timeout_ch0_source_id_gets(), udma_ctrl_timeout_ch1_cnt_gets(), udma_ctrl_timeout_ch1_en_gets(), udma_ctrl_timeout_ch1_mode_gets(), udma_ctrl_timeout_ch1_source_id_gets(), udma_ctrl_timeout_ch2_cnt_gets(), udma_ctrl_timeout_ch2_en_gets(), udma_ctrl_timeout_ch2_mode_gets(), udma_ctrl_timeout_ch2_source_id_gets(), udma_ctrl_timeout_ch3_cnt_gets(), udma_ctrl_timeout_ch3_en_gets(), udma_ctrl_timeout_ch3_mode_gets(), udma_ctrl_timeout_ch3_source_id_gets(), udma_ctrl_timeout_ch4_cnt_gets(), udma_ctrl_timeout_ch4_en_gets(), udma_ctrl_timeout_ch4_mode_gets(), udma_ctrl_timeout_ch4_source_id_gets(), udma_ctrl_timeout_ch5_cnt_gets(), udma_ctrl_timeout_ch5_en_gets(), udma_ctrl_timeout_ch5_mode_gets(), udma_ctrl_timeout_ch5_source_id_gets(), udma_ctrl_timeout_ch6_cnt_gets(), udma_ctrl_timeout_ch6_en_gets(), udma_ctrl_timeout_ch6_mode_gets(), udma_ctrl_timeout_ch6_source_id_gets(), udma_ctrl_timeout_ch7_cnt_gets(), udma_ctrl_timeout_ch7_en_gets(), udma_ctrl_timeout_ch7_mode_gets(), udma_ctrl_timeout_ch7_source_id_gets(), udma_ctrl_timeout_pre0_clr_gets(), udma_ctrl_timeout_pre0_cnt_gets(), udma_ctrl_timeout_pre0_en_gets(), udma_ctrl_timeout_pre1_clr_gets(), udma_ctrl_timeout_pre1_cnt_gets(), udma_ctrl_timeout_pre1_en_gets(), udma_ctrl_timeout_pre2_clr_gets(), udma_ctrl_timeout_pre2_cnt_gets(), udma_ctrl_timeout_pre2_en_gets(), udma_ctrl_timeout_pre3_clr_gets(), udma_ctrl_timeout_pre3_cnt_gets(), udma_ctrl_timeout_pre3_en_gets(), udma_ctrl_timeout_pre4_clr_gets(), udma_ctrl_timeout_pre4_cnt_gets(), udma_ctrl_timeout_pre4_en_gets(), udma_ctrl_timeout_pre5_clr_gets(), udma_ctrl_timeout_pre5_cnt_gets(), udma_ctrl_timeout_pre5_en_gets(), udma_ctrl_timeout_pre6_clr_gets(), udma_ctrl_timeout_pre6_cnt_gets(), udma_ctrl_timeout_pre6_en_gets(), udma_ctrl_timeout_pre7_clr_gets(), udma_ctrl_timeout_pre7_cnt_gets(), udma_ctrl_timeout_pre7_en_gets(), udma_hyper_burst_enable_2d_enable_gets(), udma_hyper_burst_enable_2d_mode_gets(), udma_hyper_burst_enable_cs0_auto_burst_enable_gets(), udma_hyper_burst_enable_cs0_maximum_check_enable_gets(), udma_hyper_burst_enable_cs1_auto_burst_enable_gets(), udma_hyper_burst_enable_cs1_maximum_check_enable_gets(), udma_hyper_clk_div_data_gets(), udma_hyper_clk_div_valid_gets(), udma_hyper_device_dt0_gets(), udma_hyper_device_dt1_gets(), udma_hyper_device_sdio_gets(), udma_hyper_device_type_gets(), udma_hyper_ext_addr_reg_access_gets(), udma_hyper_ext_addr_saddr_gets(), udma_hyper_irq_en_en_gets(), udma_hyper_irq_en_xip_en_gets(), udma_hyper_mba0_mba0_gets(), udma_hyper_mba0_reserved_gets(), udma_hyper_mba1_mba1_gets(), udma_hyper_mba1_reserved_gets(), udma_hyper_ospi_alter_mode0_gets(), udma_hyper_ospi_alter_mode1_gets(), udma_hyper_ospi_alter_xip_mode0_gets(), udma_hyper_ospi_alter_xip_mode1_gets(), udma_hyper_ospi_cfg_addr_dtr_str_gets(), udma_hyper_ospi_cfg_addr_size_gets(), udma_hyper_ospi_cfg_cmd_dtr_str_gets(), udma_hyper_ospi_cfg_cmd_size_gets(), udma_hyper_ospi_cfg_data_dtr_msb_gets(), udma_hyper_ospi_cfg_data_dtr_str_gets(), udma_hyper_ospi_cfg_line_gets(), udma_hyper_ospi_cfg_xip_addr_dtr_str_gets(), udma_hyper_ospi_cfg_xip_addr_size_gets(), udma_hyper_ospi_cfg_xip_cmd_dtr_str_gets(), udma_hyper_ospi_cfg_xip_cmd_size_gets(), udma_hyper_ospi_cfg_xip_data_dtr_msb_gets(), udma_hyper_ospi_cfg_xip_data_dtr_str_gets(), udma_hyper_ospi_cfg_xip_line_gets(), udma_hyper_ospi_cmd_cmd_gets(), udma_hyper_ospi_cmd_sdio_cmd_op_gets(), udma_hyper_ospi_cmd_sdio_cmd_rsp_type_gets(), udma_hyper_ospi_cmd_xip_cmd_gets(), udma_hyper_ospi_cmd_xip_sdio_cmd_op_gets(), udma_hyper_ospi_cmd_xip_sdio_cmd_rsp_type_gets(), udma_hyper_ospi_csn_auto_en_gets(), udma_hyper_ospi_csn_direct_ctrl_gets(), udma_hyper_ospi_csn_index_gets(), udma_hyper_ospi_csn_reserved_gets(), udma_hyper_ospi_csn_sdio_auto_stop_gets(), udma_hyper_ospi_csn_sdio_block_num_gets(), udma_hyper_ospi_csn_sdio_block_size_gets(), udma_hyper_ospi_csn_sdio_data_quad_ddr_gets(), udma_hyper_ospi_csn_sdio_data_quad_gets(), udma_hyper_ospi_csn_value_gets(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_en_gets(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_value_gets(), udma_hyper_ospi_ram_opt_opt_read_en_cs_gets(), udma_hyper_ospi_ram_opt_psram_addr_even_gets(), udma_hyper_ospi_ram_opt_psram_cmd_en_gets(), udma_hyper_ospi_ram_opt_psram_cross_boundary_en_gets(), udma_hyper_ospi_ram_opt_psram_read_bit_gets(), udma_hyper_ospi_ram_opt_real_addr_en_gets(), udma_hyper_ospi_reg_xip_xip_latency0_gets(), udma_hyper_ospi_reg_xip_xip_latency1_gets(), udma_hyper_rx_dest_dest_gets(), udma_hyper_rx_dest_dest_stream_gets(), udma_hyper_status_reserved_gets(), udma_hyper_status_rx_error_gets(), udma_hyper_status_rx_tx_end_gets(), udma_hyper_status_sdio_error_status_gets(), udma_hyper_status_sdio_rx_tx_end_gets(), udma_hyper_status_sdio_rx_tx_error_gets(), udma_hyper_status_tx_error_gets(), udma_hyper_timing_cfg_additional_latency_autocheck_en_gets(), udma_hyper_timing_cfg_cs_max_gets(), udma_hyper_timing_cfg_latency0_gets(), udma_hyper_timing_cfg_latency1_gets(), udma_hyper_timing_cfg_rw_recovery_gets(), udma_hyper_timing_cfg_rwds_delay_gets(), udma_hyper_trans_cfg_rxtx_gets(), udma_hyper_trans_cfg_valid_gets(), udma_hyper_trans_mode_auto_ena_gets(), udma_hyper_trans_mode_stream_en_gets(), udma_hyper_trans_mode_stream_xip_en_gets(), udma_hyper_trans_mode_xip_en_gets(), udma_hyper_trans_mode_xip_halted_gets(), udma_hyper_tx_dest_dest_gets(), udma_hyper_tx_dest_dest_stream_gets(), udma_i2c_status_reg_idx_status_foll_eof_rcv_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_eof_snd_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_error_arlo_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_error_framing_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_purge_event_o_idx_gets(), udma_i2c_status_reg_idx_status_foll_sof_rcv_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_sof_snd_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_unlock_event_o_idx_gets(), udma_i2c_status_reg_idx_status_i2c_prescaler_set_div10_event_o_idx_gets(), udma_i2c_status_reg_idx_status_i2c_soft_reset_event_o_idx_gets(), udma_i2c_status_reg_idx_status_lead_command_event_i_idx_gets(), udma_i2c_status_reg_idx_status_lead_error_arlo_event_i_idx_gets(), udma_i2c_status_reg_idx_status_lead_error_framing_event_i_idx_gets(), udma_i2c_status_reg_idx_status_lead_error_nack_event_i_idx_gets(), udma_i2c_status_reg_idx_status_lead_purge_event_o_idx_gets(), udma_i2c_status_reg_idx_status_lead_unlock_event_o_idx_gets(), udma_mram_clk_div_data_gets(), udma_mram_clk_div_enable_gets(), udma_mram_clk_div_valid_gets(), udma_mram_enable_2d_enable_gets(), udma_mram_erase_addr_addr_lsb_gets(), udma_mram_erase_addr_addr_msb_gets(), udma_mram_erase_size_size_gets(), udma_mram_ier_erase_en_gets(), udma_mram_ier_program_en_gets(), udma_mram_ier_rx_done_en_gets(), udma_mram_ier_rx_xip_done_en_gets(), udma_mram_ier_trim_config_en_gets(), udma_mram_ier_xip_erase_en_gets(), udma_mram_ier_xip_program_en_gets(), udma_mram_ier_xip_trim_config_en_gets(), udma_mram_isr_erase_done_gets(), udma_mram_isr_program_done_gets(), udma_mram_isr_rx_done_gets(), udma_mram_isr_trim_config_done_gets(), udma_mram_mode_dpd_gets(), udma_mram_mode_eccbyps_gets(), udma_mram_mode_nvr_gets(), udma_mram_mode_operation_gets(), udma_mram_mode_porb_gets(), udma_mram_mode_retb_gets(), udma_mram_mode_rstb_gets(), udma_mram_mode_tmen_gets(), udma_mram_rx_dest_dest_gets(), udma_mram_status_ec_err_gets(), udma_mram_status_erase_busy_gets(), udma_mram_status_rx_busy_gets(), udma_mram_status_tx_busy_gets(), udma_mram_status_ue_err_gets(), udma_mram_timing_cfg_ads_time_cnt_gets(), udma_mram_timing_cfg_go_sup_time_cnt_gets(), udma_mram_timing_cfg_men_time_cnt_gets(), udma_mram_timing_cfg_pgs_time_cnt_gets(), udma_mram_timing_cfg_prog_time_cnt_gets(), udma_mram_timing_cfg_rw_time_cnt_gets(), udma_mram_timing_cfg_strobe_time_cnt_gets(), udma_mram_trans_cfg_rxtx_gets(), udma_mram_trans_cfg_valid_gets(), udma_mram_trans_mode_auto_ena_gets(), udma_mram_trans_mode_reserved_gets(), udma_mram_trans_mode_xip_en_gets(), udma_mram_trans_mode_xip_halted_gets(), udma_mram_trans_size_size_gets(), udma_mram_tx_dest_dest_gets(), udma_timestamp_reg_clk_cfg_clk_mux_en_gets(), udma_timestamp_reg_clk_cfg_clk_mux_gets(), udma_timestamp_reg_clk_cfg_gpio_sel_gets(), udma_timestamp_reg_clk_cfg_prescaler_gets(), udma_timestamp_reg_clk_cfg_pwm_sel_gets(), udma_timestamp_reg_cmd_cnt_clr_gets(), udma_timestamp_reg_cmd_cnt_stop_gets(), udma_timestamp_reg_dest_rx_dest_gets(), udma_timestamp_reg_setup_ch0_1_input_en_ch0_gets(), udma_timestamp_reg_setup_ch0_1_input_en_ch1_gets(), udma_timestamp_reg_setup_ch0_1_input_sel_ch0_gets(), udma_timestamp_reg_setup_ch0_1_input_sel_ch1_gets(), udma_timestamp_reg_setup_ch0_1_input_type_ch0_gets(), udma_timestamp_reg_setup_ch0_1_input_type_ch1_gets(), udma_timestamp_reg_setup_ch2_3_input_en_ch2_gets(), udma_timestamp_reg_setup_ch2_3_input_en_ch3_gets(), udma_timestamp_reg_setup_ch2_3_input_sel_ch2_gets(), udma_timestamp_reg_setup_ch2_3_input_sel_ch3_gets(), udma_timestamp_reg_setup_ch2_3_input_type_ch2_gets(), udma_timestamp_reg_setup_ch2_3_input_type_ch3_gets(), udma_timestamp_reg_setup_ch4_5_input_en_ch4_gets(), udma_timestamp_reg_setup_ch4_5_input_en_ch5_gets(), udma_timestamp_reg_setup_ch4_5_input_sel_ch4_gets(), udma_timestamp_reg_setup_ch4_5_input_sel_ch5_gets(), udma_timestamp_reg_setup_ch4_5_input_type_ch4_gets(), udma_timestamp_reg_setup_ch4_5_input_type_ch5_gets(), udma_timestamp_reg_setup_ch6_7_input_en_ch6_gets(), udma_timestamp_reg_setup_ch6_7_input_en_ch7_gets(), udma_timestamp_reg_setup_ch6_7_input_sel_ch6_gets(), udma_timestamp_reg_setup_ch6_7_input_sel_ch7_gets(), udma_timestamp_reg_setup_ch6_7_input_type_ch6_gets(), udma_timestamp_reg_setup_ch6_7_input_type_ch7_gets(), udma_timestamp_reg_setup_cnt_cnt_ext_en_gets(), udma_timestamp_reg_setup_cnt_cnt_ext_sel_gets(), and udma_timestamp_reg_setup_cnt_cnt_ext_type_gets().
| #define GAP_BEXTRACTU | ( | src, | |
| size, | |||
| off | |||
| ) |
Referenced by adv_timer_cg_ena_get(), adv_timer_ch_mux_ch_sel_0_get(), adv_timer_ch_mux_ch_sel_1_get(), adv_timer_ch_mux_ch_sel_2_get(), adv_timer_ch_mux_ch_sel_3_get(), adv_timer_ch_mux_ch_sel_4_get(), adv_timer_ch_mux_ch_sel_5_get(), adv_timer_ch_mux_ch_sel_6_get(), adv_timer_ch_mux_ch_sel_7_get(), adv_timer_event_cfg_ena_get(), adv_timer_event_cfg_sel0_get(), adv_timer_event_cfg_sel1_get(), adv_timer_event_cfg_sel2_get(), adv_timer_event_cfg_sel3_get(), adv_timer_t0_cmd_arm_get(), adv_timer_t0_cmd_reset_get(), adv_timer_t0_cmd_rfu_get(), adv_timer_t0_cmd_start_get(), adv_timer_t0_cmd_stop_get(), adv_timer_t0_cmd_update_get(), adv_timer_t0_config_clksel_get(), adv_timer_t0_config_insel_get(), adv_timer_t0_config_mode_get(), adv_timer_t0_config_presc_get(), adv_timer_t0_config_updownsel_get(), adv_timer_t0_counter_counter_get(), adv_timer_t0_th_channel0_mode_get(), adv_timer_t0_th_channel0_th_get(), adv_timer_t0_th_channel1_mode_get(), adv_timer_t0_th_channel1_th_get(), adv_timer_t0_th_channel2_mode_get(), adv_timer_t0_th_channel2_th_get(), adv_timer_t0_th_channel3_mode_get(), adv_timer_t0_th_channel3_th_get(), adv_timer_t0_threshold_th_hi_get(), adv_timer_t0_threshold_th_lo_get(), adv_timer_t1_cmd_arm_get(), adv_timer_t1_cmd_reset_get(), adv_timer_t1_cmd_start_get(), adv_timer_t1_cmd_stop_get(), adv_timer_t1_cmd_update_get(), adv_timer_t1_config_clksel_get(), adv_timer_t1_config_insel_get(), adv_timer_t1_config_mode_get(), adv_timer_t1_config_presc_get(), adv_timer_t1_config_updownsel_get(), adv_timer_t1_counter_counter_get(), adv_timer_t1_th_channel0_mode_get(), adv_timer_t1_th_channel0_th_get(), adv_timer_t1_th_channel1_mode_get(), adv_timer_t1_th_channel1_th_get(), adv_timer_t1_th_channel2_mode_get(), adv_timer_t1_th_channel2_th_get(), adv_timer_t1_th_channel3_mode_get(), adv_timer_t1_th_channel3_th_get(), adv_timer_t1_threshold_th_hi_get(), adv_timer_t1_threshold_th_lo_get(), adv_timer_t2_cmd_arm_get(), adv_timer_t2_cmd_reset_get(), adv_timer_t2_cmd_start_get(), adv_timer_t2_cmd_stop_get(), adv_timer_t2_cmd_update_get(), adv_timer_t2_config_clksel_get(), adv_timer_t2_config_insel_get(), adv_timer_t2_config_mode_get(), adv_timer_t2_config_presc_get(), adv_timer_t2_config_updownsel_get(), adv_timer_t2_counter_counter_get(), adv_timer_t2_th_channel0_mode_get(), adv_timer_t2_th_channel0_th_get(), adv_timer_t2_th_channel1_mode_get(), adv_timer_t2_th_channel1_th_get(), adv_timer_t2_th_channel2_mode_get(), adv_timer_t2_th_channel2_th_get(), adv_timer_t2_th_channel3_mode_get(), adv_timer_t2_th_channel3_th_get(), adv_timer_t2_threshold_th_hi_get(), adv_timer_t2_threshold_th_lo_get(), adv_timer_t3_cmd_arm_get(), adv_timer_t3_cmd_reset_get(), adv_timer_t3_cmd_start_get(), adv_timer_t3_cmd_stop_get(), adv_timer_t3_cmd_update_get(), adv_timer_t3_config_clksel_get(), adv_timer_t3_config_insel_get(), adv_timer_t3_config_mode_get(), adv_timer_t3_config_presc_get(), adv_timer_t3_config_updownsel_get(), adv_timer_t3_counter_counter_get(), adv_timer_t3_th_channel0_mode_get(), adv_timer_t3_th_channel0_th_get(), adv_timer_t3_th_channel1_mode_get(), adv_timer_t3_th_channel1_th_get(), adv_timer_t3_th_channel2_mode_get(), adv_timer_t3_th_channel2_th_get(), adv_timer_t3_th_channel3_mode_get(), adv_timer_t3_th_channel3_th_get(), adv_timer_t3_threshold_th_hi_get(), adv_timer_t3_threshold_th_lo_get(), decompressor_clock_enable_reg_clock_enable_get(), decompressor_conf_reg_decompr_direction_get(), decompressor_conf_reg_decompr_mode_get(), decompressor_conf_reg_extension_type_get(), decompressor_conf_reg_item_bit_width_get(), decompressor_conf_reg_item_to_decompress_get(), decompressor_conf_reg_sign_extension_get(), decompressor_conf_reg_start_bit_get(), decompressor_conf_reg_start_byte_get(), decompressor_l2_count_reg_l2_linear_count_get(), decompressor_l2_stride_reg_l2_stride_count_get(), decompressor_lut_write_reg_lut_addr_get(), decompressor_lut_write_reg_lut_data_get(), decompressor_mode_reg_transf_mode_get(), decompressor_push_cmd_reg_trigger_get(), decompressor_soft_reset_reg_soft_reset_get(), decompressor_status_reg_status_get(), decompressor_tcdm_count_reg_tcdm_linear_count_get(), decompressor_tcdm_stride_reg_tcdm_stride_count_get(), fll_ccr1_clk0_div_get(), fll_ccr1_clk1_div_get(), fll_ccr1_clk2_div_get(), fll_ccr1_clk3_div_get(), fll_ccr2_ckg0_get(), fll_ccr2_ckg1_get(), fll_ccr2_ckg2_get(), fll_ccr2_ckg3_get(), fll_ccr2_clk0_sel_get(), fll_ccr2_clk1_sel_get(), fll_ccr2_clk2_sel_get(), fll_ccr2_clk3_sel_get(), fll_drr_dco_max_get(), fll_drr_dco_min_get(), fll_f0cr1_dco_en_get(), fll_f0cr1_itg_per_get(), fll_f0cr1_lock_tol_get(), fll_f0cr1_loop_gain_get(), fll_f0cr1_op_mode_get(), fll_f0cr1_stbl_get(), fll_f0cr1_ttm_en_get(), fll_f0cr2_dco_code_get(), fll_f0cr2_mfi_get(), fll_f1cr1_dco_en_get(), fll_f1cr1_itg_per_get(), fll_f1cr1_lock_tol_get(), fll_f1cr1_loop_gain_get(), fll_f1cr1_op_mode_get(), fll_f1cr1_stbl_get(), fll_f1cr1_ttm_en_get(), fll_f1cr2_dco_code_get(), fll_f1cr2_mfi_get(), fll_f2cr1_dco_en_get(), fll_f2cr1_itg_per_get(), fll_f2cr1_lock_tol_get(), fll_f2cr1_loop_gain_get(), fll_f2cr1_op_mode_get(), fll_f2cr1_stbl_get(), fll_f2cr1_ttm_en_get(), fll_f2cr2_dco_code_get(), fll_f2cr2_mfi_get(), fll_f3cr1_dco_en_get(), fll_f3cr1_itg_per_get(), fll_f3cr1_lock_tol_get(), fll_f3cr1_loop_gain_get(), fll_f3cr1_op_mode_get(), fll_f3cr1_stbl_get(), fll_f3cr1_ttm_en_get(), fll_f3cr2_dco_code_get(), fll_f3cr2_mfi_get(), fll_fsr_clmp_hi_err0_get(), fll_fsr_clmp_hi_err1_get(), fll_fsr_clmp_hi_err2_get(), fll_fsr_clmp_hi_err3_get(), fll_fsr_clmp_lo_err0_get(), fll_fsr_clmp_lo_err1_get(), fll_fsr_clmp_lo_err2_get(), fll_fsr_clmp_lo_err3_get(), fll_fsr_fdc_sat_err0_get(), fll_fsr_fdc_sat_err1_get(), fll_fsr_fdc_sat_err2_get(), fll_fsr_fdc_sat_err3_get(), fll_fsr_lock0_get(), fll_fsr_lock1_get(), fll_fsr_lock2_get(), fll_fsr_lock3_get(), fll_ttr_refresh_get(), gpio_padcfg_00_03_padcfg_get(), gpio_padcfg_04_07_padcfg_get(), gpio_padcfg_08_11_padcfg_get(), gpio_padcfg_12_15_padcfg_get(), gpio_padcfg_16_19_padcfg_get(), gpio_padcfg_20_23_padcfg_get(), gpio_padcfg_24_27_padcfg_get(), gpio_padcfg_28_31_padcfg_get(), gpio_padcfg_32_35_padcfg_get(), gpio_padcfg_36_39_padcfg_get(), gpio_padcfg_40_43_padcfg_get(), gpio_padcfg_44_47_padcfg_get(), gpio_padcfg_48_51_padcfg_get(), gpio_padcfg_52_55_padcfg_get(), gpio_padcfg_56_59_padcfg_get(), gpio_padcfg_60_63_padcfg_get(), gpio_padcfg_64_67_padcfg_get(), gpio_padcfg_68_71_padcfg_get(), gpio_padcfg_72_75_padcfg_get(), gpio_padcfg_76_79_padcfg_get(), gpio_padcfg_80_83_padcfg_get(), gpio_padcfg_84_87_padcfg_get(), gpio_padcfg_88_91_padcfg_get(), gpio_padcfg_92_95_padcfg_get(), udma_aes_cfg_mode_get(), udma_aes_dest_rx_dest_get(), udma_aes_dest_tx_dest_get(), udma_aes_setup_block_rst_get(), udma_aes_setup_ecb_cbc_get(), udma_aes_setup_enc_dec_get(), udma_aes_setup_fifo_clr_get(), udma_aes_setup_key_init_get(), udma_aes_setup_key_type_get(), udma_aes_setup_reserved_get(), udma_asrc_ctrl_cfg_0_clk_en_get(), udma_asrc_ctrl_cfg_0_fs_in_get(), udma_asrc_ctrl_cfg_0_fs_out_get(), udma_asrc_ctrl_cfg_0_lock_wnd_get(), udma_asrc_ctrl_cfg_0_rstn_get(), udma_asrc_ctrl_cfg_1_clk_en_get(), udma_asrc_ctrl_cfg_1_fs_in_get(), udma_asrc_ctrl_cfg_1_fs_out_get(), udma_asrc_ctrl_cfg_1_lock_wnd_get(), udma_asrc_ctrl_cfg_1_rstn_get(), udma_asrc_lane_cfg_0_ch_en_get(), udma_asrc_lane_cfg_0_clk_en_get(), udma_asrc_lane_cfg_0_ctrl_mux_get(), udma_asrc_lane_cfg_0_drop_on_wait_get(), udma_asrc_lane_cfg_0_rstn_get(), udma_asrc_lane_cfg_0_use_stream_in_get(), udma_asrc_lane_cfg_0_use_stream_out_get(), udma_asrc_lane_cfg_0_wait_lock_in_get(), udma_asrc_lane_cfg_0_wait_lock_out_get(), udma_asrc_lane_cfg_1_ch_en_get(), udma_asrc_lane_cfg_1_clk_en_get(), udma_asrc_lane_cfg_1_ctrl_mux_get(), udma_asrc_lane_cfg_1_drop_on_wait_get(), udma_asrc_lane_cfg_1_rstn_get(), udma_asrc_lane_cfg_1_use_stream_in_get(), udma_asrc_lane_cfg_1_use_stream_out_get(), udma_asrc_lane_cfg_1_wait_lock_in_get(), udma_asrc_lane_cfg_1_wait_lock_out_get(), udma_asrc_lane_cfg_2_ch_en_get(), udma_asrc_lane_cfg_2_clk_en_get(), udma_asrc_lane_cfg_2_ctrl_mux_get(), udma_asrc_lane_cfg_2_drop_on_wait_get(), udma_asrc_lane_cfg_2_rstn_get(), udma_asrc_lane_cfg_2_use_stream_in_get(), udma_asrc_lane_cfg_2_use_stream_out_get(), udma_asrc_lane_cfg_2_wait_lock_in_get(), udma_asrc_lane_cfg_2_wait_lock_out_get(), udma_asrc_lane_cfg_3_ch_en_get(), udma_asrc_lane_cfg_3_clk_en_get(), udma_asrc_lane_cfg_3_ctrl_mux_get(), udma_asrc_lane_cfg_3_drop_on_wait_get(), udma_asrc_lane_cfg_3_rstn_get(), udma_asrc_lane_cfg_3_use_stream_in_get(), udma_asrc_lane_cfg_3_use_stream_out_get(), udma_asrc_lane_cfg_3_wait_lock_in_get(), udma_asrc_lane_cfg_3_wait_lock_out_get(), udma_asrc_lane_idin_0_id_ch0_get(), udma_asrc_lane_idin_0_id_ch1_get(), udma_asrc_lane_idin_0_id_ch2_get(), udma_asrc_lane_idin_0_id_ch3_get(), udma_asrc_lane_idin_1_id_ch0_get(), udma_asrc_lane_idin_1_id_ch1_get(), udma_asrc_lane_idin_1_id_ch2_get(), udma_asrc_lane_idin_1_id_ch3_get(), udma_asrc_lane_idin_2_id_ch0_get(), udma_asrc_lane_idin_2_id_ch1_get(), udma_asrc_lane_idin_2_id_ch2_get(), udma_asrc_lane_idin_2_id_ch3_get(), udma_asrc_lane_idin_3_id_ch0_get(), udma_asrc_lane_idin_3_id_ch1_get(), udma_asrc_lane_idin_3_id_ch2_get(), udma_asrc_lane_idin_3_id_ch3_get(), udma_asrc_lane_idout_0_id_ch0_get(), udma_asrc_lane_idout_0_id_ch1_get(), udma_asrc_lane_idout_0_id_ch2_get(), udma_asrc_lane_idout_0_id_ch3_get(), udma_asrc_lane_idout_1_id_ch0_get(), udma_asrc_lane_idout_1_id_ch1_get(), udma_asrc_lane_idout_1_id_ch2_get(), udma_asrc_lane_idout_1_id_ch3_get(), udma_asrc_lane_idout_2_id_ch0_get(), udma_asrc_lane_idout_2_id_ch1_get(), udma_asrc_lane_idout_2_id_ch2_get(), udma_asrc_lane_idout_2_id_ch3_get(), udma_asrc_lane_idout_3_id_ch0_get(), udma_asrc_lane_idout_3_id_ch1_get(), udma_asrc_lane_idout_3_id_ch2_get(), udma_asrc_lane_idout_3_id_ch3_get(), udma_asrc_mem2mem_cfg_ch_en_get(), udma_asrc_mem2mem_cfg_clk_en_get(), udma_asrc_mem2mem_cfg_ctx_id_get(), udma_asrc_mem2mem_cfg_fs_in_get(), udma_asrc_mem2mem_cfg_fs_out_get(), udma_asrc_mem2mem_cfg_restore_get(), udma_asrc_mem2mem_cfg_rstn_get(), udma_asrc_mem2mem_cfg_store_get(), udma_asrc_mem2mem_id_m2m_in_ch0_get(), udma_asrc_mem2mem_id_m2m_in_ch1_get(), udma_asrc_mem2mem_id_m2m_out_ch0_get(), udma_asrc_mem2mem_id_m2m_out_ch1_get(), udma_asrc_mem2mem_ratio_m2m_ratio_en_get(), udma_asrc_mem2mem_ratio_m2m_ratio_get(), udma_asrc_status_lock_get(), udma_core_2d_addrgen_cfg_ctrl_cont_get(), udma_core_2d_addrgen_cfg_ctrl_en_get(), udma_core_2d_addrgen_cfg_ctrl_stop_get(), udma_core_fifo_cfg_ctrl_en_get(), udma_core_fifo_cfg_ctrl_stop_get(), udma_core_fifo_cfg_ctrl_timeout_mon_get(), udma_core_fifo_cfg_evt_en_get(), udma_core_fifo_cfg_evt_num_bytes_get(), udma_cpi_cam_cfg_glob_en_get(), udma_cpi_cam_cfg_glob_format_get(), udma_cpi_cam_cfg_glob_framedrop_en_get(), udma_cpi_cam_cfg_glob_framedrop_val_get(), udma_cpi_cam_cfg_glob_frameslice_en_get(), udma_cpi_cam_cfg_ll_frameslice_llx_get(), udma_cpi_cam_cfg_ll_frameslice_lly_get(), udma_cpi_cam_cfg_rgb_sequence_get(), udma_cpi_cam_cfg_size_rowlen_get(), udma_cpi_cam_cfg_ur_frameslice_urx_get(), udma_cpi_cam_cfg_ur_frameslice_ury_get(), udma_cpi_cam_hsync_polarity_hsync_polarity_get(), udma_cpi_cam_rx_datasize_rx_datasize_get(), udma_cpi_cam_rx_dest_rx_dest_get(), udma_cpi_cam_vsync_polarity_vsync_polarity_get(), udma_ctrl_cfg_event_cmp_evt0_get(), udma_ctrl_cfg_event_cmp_evt1_get(), udma_ctrl_cfg_event_cmp_evt2_get(), udma_ctrl_cfg_event_cmp_evt3_get(), udma_ctrl_datamove0_size_en_get(), udma_ctrl_datamove0_size_size_get(), udma_ctrl_datamove0_size_stop_get(), udma_ctrl_datamove1_size_en_get(), udma_ctrl_datamove1_size_size_get(), udma_ctrl_datamove1_size_stop_get(), udma_ctrl_datamove_cfg_dest_id_0_get(), udma_ctrl_datamove_cfg_dest_id_1_get(), udma_ctrl_datamove_cfg_source_id_0_get(), udma_ctrl_datamove_cfg_source_id_1_get(), udma_ctrl_fifo_cfg_pop_id_get(), udma_ctrl_fifo_cfg_push_id_get(), udma_ctrl_timeout_ch0_cnt_get(), udma_ctrl_timeout_ch0_en_get(), udma_ctrl_timeout_ch0_mode_get(), udma_ctrl_timeout_ch0_source_id_get(), udma_ctrl_timeout_ch1_cnt_get(), udma_ctrl_timeout_ch1_en_get(), udma_ctrl_timeout_ch1_mode_get(), udma_ctrl_timeout_ch1_source_id_get(), udma_ctrl_timeout_ch2_cnt_get(), udma_ctrl_timeout_ch2_en_get(), udma_ctrl_timeout_ch2_mode_get(), udma_ctrl_timeout_ch2_source_id_get(), udma_ctrl_timeout_ch3_cnt_get(), udma_ctrl_timeout_ch3_en_get(), udma_ctrl_timeout_ch3_mode_get(), udma_ctrl_timeout_ch3_source_id_get(), udma_ctrl_timeout_ch4_cnt_get(), udma_ctrl_timeout_ch4_en_get(), udma_ctrl_timeout_ch4_mode_get(), udma_ctrl_timeout_ch4_source_id_get(), udma_ctrl_timeout_ch5_cnt_get(), udma_ctrl_timeout_ch5_en_get(), udma_ctrl_timeout_ch5_mode_get(), udma_ctrl_timeout_ch5_source_id_get(), udma_ctrl_timeout_ch6_cnt_get(), udma_ctrl_timeout_ch6_en_get(), udma_ctrl_timeout_ch6_mode_get(), udma_ctrl_timeout_ch6_source_id_get(), udma_ctrl_timeout_ch7_cnt_get(), udma_ctrl_timeout_ch7_en_get(), udma_ctrl_timeout_ch7_mode_get(), udma_ctrl_timeout_ch7_source_id_get(), udma_ctrl_timeout_pre0_clr_get(), udma_ctrl_timeout_pre0_cnt_get(), udma_ctrl_timeout_pre0_en_get(), udma_ctrl_timeout_pre1_clr_get(), udma_ctrl_timeout_pre1_cnt_get(), udma_ctrl_timeout_pre1_en_get(), udma_ctrl_timeout_pre2_clr_get(), udma_ctrl_timeout_pre2_cnt_get(), udma_ctrl_timeout_pre2_en_get(), udma_ctrl_timeout_pre3_clr_get(), udma_ctrl_timeout_pre3_cnt_get(), udma_ctrl_timeout_pre3_en_get(), udma_ctrl_timeout_pre4_clr_get(), udma_ctrl_timeout_pre4_cnt_get(), udma_ctrl_timeout_pre4_en_get(), udma_ctrl_timeout_pre5_clr_get(), udma_ctrl_timeout_pre5_cnt_get(), udma_ctrl_timeout_pre5_en_get(), udma_ctrl_timeout_pre6_clr_get(), udma_ctrl_timeout_pre6_cnt_get(), udma_ctrl_timeout_pre6_en_get(), udma_ctrl_timeout_pre7_clr_get(), udma_ctrl_timeout_pre7_cnt_get(), udma_ctrl_timeout_pre7_en_get(), udma_hyper_burst_enable_2d_enable_get(), udma_hyper_burst_enable_2d_mode_get(), udma_hyper_burst_enable_cs0_auto_burst_enable_get(), udma_hyper_burst_enable_cs0_maximum_check_enable_get(), udma_hyper_burst_enable_cs1_auto_burst_enable_get(), udma_hyper_burst_enable_cs1_maximum_check_enable_get(), udma_hyper_clk_div_data_get(), udma_hyper_clk_div_valid_get(), udma_hyper_device_dt0_get(), udma_hyper_device_dt1_get(), udma_hyper_device_sdio_get(), udma_hyper_device_type_get(), udma_hyper_ext_addr_reg_access_get(), udma_hyper_ext_addr_saddr_get(), udma_hyper_irq_en_en_get(), udma_hyper_irq_en_xip_en_get(), udma_hyper_mba0_mba0_get(), udma_hyper_mba0_reserved_get(), udma_hyper_mba1_mba1_get(), udma_hyper_mba1_reserved_get(), udma_hyper_ospi_alter_mode0_get(), udma_hyper_ospi_alter_mode1_get(), udma_hyper_ospi_alter_xip_mode0_get(), udma_hyper_ospi_alter_xip_mode1_get(), udma_hyper_ospi_cfg_addr_dtr_str_get(), udma_hyper_ospi_cfg_addr_size_get(), udma_hyper_ospi_cfg_cmd_dtr_str_get(), udma_hyper_ospi_cfg_cmd_size_get(), udma_hyper_ospi_cfg_data_dtr_msb_get(), udma_hyper_ospi_cfg_data_dtr_str_get(), udma_hyper_ospi_cfg_line_get(), udma_hyper_ospi_cfg_xip_addr_dtr_str_get(), udma_hyper_ospi_cfg_xip_addr_size_get(), udma_hyper_ospi_cfg_xip_cmd_dtr_str_get(), udma_hyper_ospi_cfg_xip_cmd_size_get(), udma_hyper_ospi_cfg_xip_data_dtr_msb_get(), udma_hyper_ospi_cfg_xip_data_dtr_str_get(), udma_hyper_ospi_cfg_xip_line_get(), udma_hyper_ospi_cmd_cmd_get(), udma_hyper_ospi_cmd_sdio_cmd_op_get(), udma_hyper_ospi_cmd_sdio_cmd_rsp_type_get(), udma_hyper_ospi_cmd_xip_cmd_get(), udma_hyper_ospi_cmd_xip_sdio_cmd_op_get(), udma_hyper_ospi_cmd_xip_sdio_cmd_rsp_type_get(), udma_hyper_ospi_csn_auto_en_get(), udma_hyper_ospi_csn_direct_ctrl_get(), udma_hyper_ospi_csn_index_get(), udma_hyper_ospi_csn_reserved_get(), udma_hyper_ospi_csn_sdio_auto_stop_get(), udma_hyper_ospi_csn_sdio_block_num_get(), udma_hyper_ospi_csn_sdio_block_size_get(), udma_hyper_ospi_csn_sdio_data_quad_ddr_get(), udma_hyper_ospi_csn_sdio_data_quad_get(), udma_hyper_ospi_csn_value_get(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_en_get(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_value_get(), udma_hyper_ospi_ram_opt_opt_read_en_cs_get(), udma_hyper_ospi_ram_opt_psram_addr_even_get(), udma_hyper_ospi_ram_opt_psram_cmd_en_get(), udma_hyper_ospi_ram_opt_psram_cross_boundary_en_get(), udma_hyper_ospi_ram_opt_psram_read_bit_get(), udma_hyper_ospi_ram_opt_real_addr_en_get(), udma_hyper_ospi_reg_xip_xip_latency0_get(), udma_hyper_ospi_reg_xip_xip_latency1_get(), udma_hyper_rx_dest_dest_get(), udma_hyper_rx_dest_dest_stream_get(), udma_hyper_status_reserved_get(), udma_hyper_status_rx_error_get(), udma_hyper_status_rx_tx_end_get(), udma_hyper_status_sdio_error_status_get(), udma_hyper_status_sdio_rx_tx_end_get(), udma_hyper_status_sdio_rx_tx_error_get(), udma_hyper_status_tx_error_get(), udma_hyper_timing_cfg_additional_latency_autocheck_en_get(), udma_hyper_timing_cfg_cs_max_get(), udma_hyper_timing_cfg_latency0_get(), udma_hyper_timing_cfg_latency1_get(), udma_hyper_timing_cfg_rw_recovery_get(), udma_hyper_timing_cfg_rwds_delay_get(), udma_hyper_trans_cfg_rxtx_get(), udma_hyper_trans_cfg_valid_get(), udma_hyper_trans_mode_auto_ena_get(), udma_hyper_trans_mode_stream_en_get(), udma_hyper_trans_mode_stream_xip_en_get(), udma_hyper_trans_mode_xip_en_get(), udma_hyper_trans_mode_xip_halted_get(), udma_hyper_tx_dest_dest_get(), udma_hyper_tx_dest_dest_stream_get(), udma_i2c_status_reg_idx_status_foll_eof_rcv_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_eof_snd_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_error_arlo_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_error_framing_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_purge_event_o_idx_get(), udma_i2c_status_reg_idx_status_foll_sof_rcv_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_sof_snd_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_unlock_event_o_idx_get(), udma_i2c_status_reg_idx_status_i2c_prescaler_set_div10_event_o_idx_get(), udma_i2c_status_reg_idx_status_i2c_soft_reset_event_o_idx_get(), udma_i2c_status_reg_idx_status_lead_command_event_i_idx_get(), udma_i2c_status_reg_idx_status_lead_error_arlo_event_i_idx_get(), udma_i2c_status_reg_idx_status_lead_error_framing_event_i_idx_get(), udma_i2c_status_reg_idx_status_lead_error_nack_event_i_idx_get(), udma_i2c_status_reg_idx_status_lead_purge_event_o_idx_get(), udma_i2c_status_reg_idx_status_lead_unlock_event_o_idx_get(), udma_mram_clk_div_data_get(), udma_mram_clk_div_enable_get(), udma_mram_clk_div_valid_get(), udma_mram_enable_2d_enable_get(), udma_mram_erase_addr_addr_lsb_get(), udma_mram_erase_addr_addr_msb_get(), udma_mram_erase_size_size_get(), udma_mram_ier_erase_en_get(), udma_mram_ier_program_en_get(), udma_mram_ier_rx_done_en_get(), udma_mram_ier_rx_xip_done_en_get(), udma_mram_ier_trim_config_en_get(), udma_mram_ier_xip_erase_en_get(), udma_mram_ier_xip_program_en_get(), udma_mram_ier_xip_trim_config_en_get(), udma_mram_isr_erase_done_get(), udma_mram_isr_program_done_get(), udma_mram_isr_rx_done_get(), udma_mram_isr_trim_config_done_get(), udma_mram_mode_dpd_get(), udma_mram_mode_eccbyps_get(), udma_mram_mode_nvr_get(), udma_mram_mode_operation_get(), udma_mram_mode_porb_get(), udma_mram_mode_retb_get(), udma_mram_mode_rstb_get(), udma_mram_mode_tmen_get(), udma_mram_rx_dest_dest_get(), udma_mram_status_ec_err_get(), udma_mram_status_erase_busy_get(), udma_mram_status_rx_busy_get(), udma_mram_status_tx_busy_get(), udma_mram_status_ue_err_get(), udma_mram_timing_cfg_ads_time_cnt_get(), udma_mram_timing_cfg_go_sup_time_cnt_get(), udma_mram_timing_cfg_men_time_cnt_get(), udma_mram_timing_cfg_pgs_time_cnt_get(), udma_mram_timing_cfg_prog_time_cnt_get(), udma_mram_timing_cfg_rw_time_cnt_get(), udma_mram_timing_cfg_strobe_time_cnt_get(), udma_mram_trans_cfg_rxtx_get(), udma_mram_trans_cfg_valid_get(), udma_mram_trans_mode_auto_ena_get(), udma_mram_trans_mode_reserved_get(), udma_mram_trans_mode_xip_en_get(), udma_mram_trans_mode_xip_halted_get(), udma_mram_trans_size_size_get(), udma_mram_tx_dest_dest_get(), udma_timestamp_reg_clk_cfg_clk_mux_en_get(), udma_timestamp_reg_clk_cfg_clk_mux_get(), udma_timestamp_reg_clk_cfg_gpio_sel_get(), udma_timestamp_reg_clk_cfg_prescaler_get(), udma_timestamp_reg_clk_cfg_pwm_sel_get(), udma_timestamp_reg_cmd_cnt_clr_get(), udma_timestamp_reg_cmd_cnt_stop_get(), udma_timestamp_reg_dest_rx_dest_get(), udma_timestamp_reg_setup_ch0_1_input_en_ch0_get(), udma_timestamp_reg_setup_ch0_1_input_en_ch1_get(), udma_timestamp_reg_setup_ch0_1_input_sel_ch0_get(), udma_timestamp_reg_setup_ch0_1_input_sel_ch1_get(), udma_timestamp_reg_setup_ch0_1_input_type_ch0_get(), udma_timestamp_reg_setup_ch0_1_input_type_ch1_get(), udma_timestamp_reg_setup_ch2_3_input_en_ch2_get(), udma_timestamp_reg_setup_ch2_3_input_en_ch3_get(), udma_timestamp_reg_setup_ch2_3_input_sel_ch2_get(), udma_timestamp_reg_setup_ch2_3_input_sel_ch3_get(), udma_timestamp_reg_setup_ch2_3_input_type_ch2_get(), udma_timestamp_reg_setup_ch2_3_input_type_ch3_get(), udma_timestamp_reg_setup_ch4_5_input_en_ch4_get(), udma_timestamp_reg_setup_ch4_5_input_en_ch5_get(), udma_timestamp_reg_setup_ch4_5_input_sel_ch4_get(), udma_timestamp_reg_setup_ch4_5_input_sel_ch5_get(), udma_timestamp_reg_setup_ch4_5_input_type_ch4_get(), udma_timestamp_reg_setup_ch4_5_input_type_ch5_get(), udma_timestamp_reg_setup_ch6_7_input_en_ch6_get(), udma_timestamp_reg_setup_ch6_7_input_en_ch7_get(), udma_timestamp_reg_setup_ch6_7_input_sel_ch6_get(), udma_timestamp_reg_setup_ch6_7_input_sel_ch7_get(), udma_timestamp_reg_setup_ch6_7_input_type_ch6_get(), udma_timestamp_reg_setup_ch6_7_input_type_ch7_get(), udma_timestamp_reg_setup_cnt_cnt_ext_en_get(), udma_timestamp_reg_setup_cnt_cnt_ext_sel_get(), and udma_timestamp_reg_setup_cnt_cnt_ext_type_get().
| #define GAP_BINSERT | ( | dst, | |
| src, | |||
| size, | |||
| off | |||
| ) |
Referenced by adv_timer_cg_ena_set(), adv_timer_ch_mux_ch_sel_0_set(), adv_timer_ch_mux_ch_sel_1_set(), adv_timer_ch_mux_ch_sel_2_set(), adv_timer_ch_mux_ch_sel_3_set(), adv_timer_ch_mux_ch_sel_4_set(), adv_timer_ch_mux_ch_sel_5_set(), adv_timer_ch_mux_ch_sel_6_set(), adv_timer_ch_mux_ch_sel_7_set(), adv_timer_event_cfg_ena_set(), adv_timer_event_cfg_sel0_set(), adv_timer_event_cfg_sel1_set(), adv_timer_event_cfg_sel2_set(), adv_timer_event_cfg_sel3_set(), adv_timer_t0_cmd_arm_set(), adv_timer_t0_cmd_reset_set(), adv_timer_t0_cmd_rfu_set(), adv_timer_t0_cmd_start_set(), adv_timer_t0_cmd_stop_set(), adv_timer_t0_cmd_update_set(), adv_timer_t0_config_clksel_set(), adv_timer_t0_config_insel_set(), adv_timer_t0_config_mode_set(), adv_timer_t0_config_presc_set(), adv_timer_t0_config_updownsel_set(), adv_timer_t0_counter_counter_set(), adv_timer_t0_th_channel0_mode_set(), adv_timer_t0_th_channel0_th_set(), adv_timer_t0_th_channel1_mode_set(), adv_timer_t0_th_channel1_th_set(), adv_timer_t0_th_channel2_mode_set(), adv_timer_t0_th_channel2_th_set(), adv_timer_t0_th_channel3_mode_set(), adv_timer_t0_th_channel3_th_set(), adv_timer_t0_threshold_th_hi_set(), adv_timer_t0_threshold_th_lo_set(), adv_timer_t1_cmd_arm_set(), adv_timer_t1_cmd_reset_set(), adv_timer_t1_cmd_start_set(), adv_timer_t1_cmd_stop_set(), adv_timer_t1_cmd_update_set(), adv_timer_t1_config_clksel_set(), adv_timer_t1_config_insel_set(), adv_timer_t1_config_mode_set(), adv_timer_t1_config_presc_set(), adv_timer_t1_config_updownsel_set(), adv_timer_t1_counter_counter_set(), adv_timer_t1_th_channel0_mode_set(), adv_timer_t1_th_channel0_th_set(), adv_timer_t1_th_channel1_mode_set(), adv_timer_t1_th_channel1_th_set(), adv_timer_t1_th_channel2_mode_set(), adv_timer_t1_th_channel2_th_set(), adv_timer_t1_th_channel3_mode_set(), adv_timer_t1_th_channel3_th_set(), adv_timer_t1_threshold_th_hi_set(), adv_timer_t1_threshold_th_lo_set(), adv_timer_t2_cmd_arm_set(), adv_timer_t2_cmd_reset_set(), adv_timer_t2_cmd_start_set(), adv_timer_t2_cmd_stop_set(), adv_timer_t2_cmd_update_set(), adv_timer_t2_config_clksel_set(), adv_timer_t2_config_insel_set(), adv_timer_t2_config_mode_set(), adv_timer_t2_config_presc_set(), adv_timer_t2_config_updownsel_set(), adv_timer_t2_counter_counter_set(), adv_timer_t2_th_channel0_mode_set(), adv_timer_t2_th_channel0_th_set(), adv_timer_t2_th_channel1_mode_set(), adv_timer_t2_th_channel1_th_set(), adv_timer_t2_th_channel2_mode_set(), adv_timer_t2_th_channel2_th_set(), adv_timer_t2_th_channel3_mode_set(), adv_timer_t2_th_channel3_th_set(), adv_timer_t2_threshold_th_hi_set(), adv_timer_t2_threshold_th_lo_set(), adv_timer_t3_cmd_arm_set(), adv_timer_t3_cmd_reset_set(), adv_timer_t3_cmd_start_set(), adv_timer_t3_cmd_stop_set(), adv_timer_t3_cmd_update_set(), adv_timer_t3_config_clksel_set(), adv_timer_t3_config_insel_set(), adv_timer_t3_config_mode_set(), adv_timer_t3_config_presc_set(), adv_timer_t3_config_updownsel_set(), adv_timer_t3_counter_counter_set(), adv_timer_t3_th_channel0_mode_set(), adv_timer_t3_th_channel0_th_set(), adv_timer_t3_th_channel1_mode_set(), adv_timer_t3_th_channel1_th_set(), adv_timer_t3_th_channel2_mode_set(), adv_timer_t3_th_channel2_th_set(), adv_timer_t3_th_channel3_mode_set(), adv_timer_t3_th_channel3_th_set(), adv_timer_t3_threshold_th_hi_set(), adv_timer_t3_threshold_th_lo_set(), decompressor_clock_enable_reg_clock_enable_set(), decompressor_conf_reg_decompr_direction_set(), decompressor_conf_reg_decompr_mode_set(), decompressor_conf_reg_extension_type_set(), decompressor_conf_reg_item_bit_width_set(), decompressor_conf_reg_item_to_decompress_set(), decompressor_conf_reg_sign_extension_set(), decompressor_conf_reg_start_bit_set(), decompressor_conf_reg_start_byte_set(), decompressor_l2_count_reg_l2_linear_count_set(), decompressor_l2_stride_reg_l2_stride_count_set(), decompressor_lut_write_reg_lut_addr_set(), decompressor_lut_write_reg_lut_data_set(), decompressor_mode_reg_transf_mode_set(), decompressor_push_cmd_reg_trigger_set(), decompressor_soft_reset_reg_soft_reset_set(), decompressor_status_reg_status_set(), decompressor_tcdm_count_reg_tcdm_linear_count_set(), decompressor_tcdm_stride_reg_tcdm_stride_count_set(), fll_ccr1_clk0_div_set(), fll_ccr1_clk1_div_set(), fll_ccr1_clk2_div_set(), fll_ccr1_clk3_div_set(), fll_ccr2_ckg0_set(), fll_ccr2_ckg1_set(), fll_ccr2_ckg2_set(), fll_ccr2_ckg3_set(), fll_ccr2_clk0_sel_set(), fll_ccr2_clk1_sel_set(), fll_ccr2_clk2_sel_set(), fll_ccr2_clk3_sel_set(), fll_drr_dco_max_set(), fll_drr_dco_min_set(), fll_f0cr1_dco_en_set(), fll_f0cr1_itg_per_set(), fll_f0cr1_lock_tol_set(), fll_f0cr1_loop_gain_set(), fll_f0cr1_op_mode_set(), fll_f0cr1_stbl_set(), fll_f0cr1_ttm_en_set(), fll_f0cr2_dco_code_set(), fll_f0cr2_mfi_set(), fll_f1cr1_dco_en_set(), fll_f1cr1_itg_per_set(), fll_f1cr1_lock_tol_set(), fll_f1cr1_loop_gain_set(), fll_f1cr1_op_mode_set(), fll_f1cr1_stbl_set(), fll_f1cr1_ttm_en_set(), fll_f1cr2_dco_code_set(), fll_f1cr2_mfi_set(), fll_f2cr1_dco_en_set(), fll_f2cr1_itg_per_set(), fll_f2cr1_lock_tol_set(), fll_f2cr1_loop_gain_set(), fll_f2cr1_op_mode_set(), fll_f2cr1_stbl_set(), fll_f2cr1_ttm_en_set(), fll_f2cr2_dco_code_set(), fll_f2cr2_mfi_set(), fll_f3cr1_dco_en_set(), fll_f3cr1_itg_per_set(), fll_f3cr1_lock_tol_set(), fll_f3cr1_loop_gain_set(), fll_f3cr1_op_mode_set(), fll_f3cr1_stbl_set(), fll_f3cr1_ttm_en_set(), fll_f3cr2_dco_code_set(), fll_f3cr2_mfi_set(), fll_fsr_clmp_hi_err0_set(), fll_fsr_clmp_hi_err1_set(), fll_fsr_clmp_hi_err2_set(), fll_fsr_clmp_hi_err3_set(), fll_fsr_clmp_lo_err0_set(), fll_fsr_clmp_lo_err1_set(), fll_fsr_clmp_lo_err2_set(), fll_fsr_clmp_lo_err3_set(), fll_fsr_fdc_sat_err0_set(), fll_fsr_fdc_sat_err1_set(), fll_fsr_fdc_sat_err2_set(), fll_fsr_fdc_sat_err3_set(), fll_fsr_lock0_set(), fll_fsr_lock1_set(), fll_fsr_lock2_set(), fll_fsr_lock3_set(), fll_ttr_refresh_set(), gpio_padcfg_00_03_padcfg_set(), gpio_padcfg_04_07_padcfg_set(), gpio_padcfg_08_11_padcfg_set(), gpio_padcfg_12_15_padcfg_set(), gpio_padcfg_16_19_padcfg_set(), gpio_padcfg_20_23_padcfg_set(), gpio_padcfg_24_27_padcfg_set(), gpio_padcfg_28_31_padcfg_set(), gpio_padcfg_32_35_padcfg_set(), gpio_padcfg_36_39_padcfg_set(), gpio_padcfg_40_43_padcfg_set(), gpio_padcfg_44_47_padcfg_set(), gpio_padcfg_48_51_padcfg_set(), gpio_padcfg_52_55_padcfg_set(), gpio_padcfg_56_59_padcfg_set(), gpio_padcfg_60_63_padcfg_set(), gpio_padcfg_64_67_padcfg_set(), gpio_padcfg_68_71_padcfg_set(), gpio_padcfg_72_75_padcfg_set(), gpio_padcfg_76_79_padcfg_set(), gpio_padcfg_80_83_padcfg_set(), gpio_padcfg_84_87_padcfg_set(), gpio_padcfg_88_91_padcfg_set(), gpio_padcfg_92_95_padcfg_set(), hal_cl_dma_cmd_make(), udma_aes_cfg_mode_set(), udma_aes_dest_rx_dest_set(), udma_aes_dest_tx_dest_set(), udma_aes_setup_block_rst_set(), udma_aes_setup_ecb_cbc_set(), udma_aes_setup_enc_dec_set(), udma_aes_setup_fifo_clr_set(), udma_aes_setup_key_init_set(), udma_aes_setup_key_type_set(), udma_aes_setup_reserved_set(), udma_asrc_ctrl_cfg_0_clk_en_set(), udma_asrc_ctrl_cfg_0_fs_in_set(), udma_asrc_ctrl_cfg_0_fs_out_set(), udma_asrc_ctrl_cfg_0_lock_wnd_set(), udma_asrc_ctrl_cfg_0_rstn_set(), udma_asrc_ctrl_cfg_1_clk_en_set(), udma_asrc_ctrl_cfg_1_fs_in_set(), udma_asrc_ctrl_cfg_1_fs_out_set(), udma_asrc_ctrl_cfg_1_lock_wnd_set(), udma_asrc_ctrl_cfg_1_rstn_set(), udma_asrc_lane_cfg_0_ch_en_set(), udma_asrc_lane_cfg_0_clk_en_set(), udma_asrc_lane_cfg_0_ctrl_mux_set(), udma_asrc_lane_cfg_0_drop_on_wait_set(), udma_asrc_lane_cfg_0_rstn_set(), udma_asrc_lane_cfg_0_use_stream_in_set(), udma_asrc_lane_cfg_0_use_stream_out_set(), udma_asrc_lane_cfg_0_wait_lock_in_set(), udma_asrc_lane_cfg_0_wait_lock_out_set(), udma_asrc_lane_cfg_1_ch_en_set(), udma_asrc_lane_cfg_1_clk_en_set(), udma_asrc_lane_cfg_1_ctrl_mux_set(), udma_asrc_lane_cfg_1_drop_on_wait_set(), udma_asrc_lane_cfg_1_rstn_set(), udma_asrc_lane_cfg_1_use_stream_in_set(), udma_asrc_lane_cfg_1_use_stream_out_set(), udma_asrc_lane_cfg_1_wait_lock_in_set(), udma_asrc_lane_cfg_1_wait_lock_out_set(), udma_asrc_lane_cfg_2_ch_en_set(), udma_asrc_lane_cfg_2_clk_en_set(), udma_asrc_lane_cfg_2_ctrl_mux_set(), udma_asrc_lane_cfg_2_drop_on_wait_set(), udma_asrc_lane_cfg_2_rstn_set(), udma_asrc_lane_cfg_2_use_stream_in_set(), udma_asrc_lane_cfg_2_use_stream_out_set(), udma_asrc_lane_cfg_2_wait_lock_in_set(), udma_asrc_lane_cfg_2_wait_lock_out_set(), udma_asrc_lane_cfg_3_ch_en_set(), udma_asrc_lane_cfg_3_clk_en_set(), udma_asrc_lane_cfg_3_ctrl_mux_set(), udma_asrc_lane_cfg_3_drop_on_wait_set(), udma_asrc_lane_cfg_3_rstn_set(), udma_asrc_lane_cfg_3_use_stream_in_set(), udma_asrc_lane_cfg_3_use_stream_out_set(), udma_asrc_lane_cfg_3_wait_lock_in_set(), udma_asrc_lane_cfg_3_wait_lock_out_set(), udma_asrc_lane_idin_0_id_ch0_set(), udma_asrc_lane_idin_0_id_ch1_set(), udma_asrc_lane_idin_0_id_ch2_set(), udma_asrc_lane_idin_0_id_ch3_set(), udma_asrc_lane_idin_1_id_ch0_set(), udma_asrc_lane_idin_1_id_ch1_set(), udma_asrc_lane_idin_1_id_ch2_set(), udma_asrc_lane_idin_1_id_ch3_set(), udma_asrc_lane_idin_2_id_ch0_set(), udma_asrc_lane_idin_2_id_ch1_set(), udma_asrc_lane_idin_2_id_ch2_set(), udma_asrc_lane_idin_2_id_ch3_set(), udma_asrc_lane_idin_3_id_ch0_set(), udma_asrc_lane_idin_3_id_ch1_set(), udma_asrc_lane_idin_3_id_ch2_set(), udma_asrc_lane_idin_3_id_ch3_set(), udma_asrc_lane_idout_0_id_ch0_set(), udma_asrc_lane_idout_0_id_ch1_set(), udma_asrc_lane_idout_0_id_ch2_set(), udma_asrc_lane_idout_0_id_ch3_set(), udma_asrc_lane_idout_1_id_ch0_set(), udma_asrc_lane_idout_1_id_ch1_set(), udma_asrc_lane_idout_1_id_ch2_set(), udma_asrc_lane_idout_1_id_ch3_set(), udma_asrc_lane_idout_2_id_ch0_set(), udma_asrc_lane_idout_2_id_ch1_set(), udma_asrc_lane_idout_2_id_ch2_set(), udma_asrc_lane_idout_2_id_ch3_set(), udma_asrc_lane_idout_3_id_ch0_set(), udma_asrc_lane_idout_3_id_ch1_set(), udma_asrc_lane_idout_3_id_ch2_set(), udma_asrc_lane_idout_3_id_ch3_set(), udma_asrc_mem2mem_cfg_ch_en_set(), udma_asrc_mem2mem_cfg_clk_en_set(), udma_asrc_mem2mem_cfg_ctx_id_set(), udma_asrc_mem2mem_cfg_fs_in_set(), udma_asrc_mem2mem_cfg_fs_out_set(), udma_asrc_mem2mem_cfg_restore_set(), udma_asrc_mem2mem_cfg_rstn_set(), udma_asrc_mem2mem_cfg_store_set(), udma_asrc_mem2mem_id_m2m_in_ch0_set(), udma_asrc_mem2mem_id_m2m_in_ch1_set(), udma_asrc_mem2mem_id_m2m_out_ch0_set(), udma_asrc_mem2mem_id_m2m_out_ch1_set(), udma_asrc_mem2mem_ratio_m2m_ratio_en_set(), udma_asrc_mem2mem_ratio_m2m_ratio_set(), udma_asrc_status_lock_set(), udma_core_2d_addrgen_cfg_ctrl_cont_set(), udma_core_2d_addrgen_cfg_ctrl_en_set(), udma_core_2d_addrgen_cfg_ctrl_stop_set(), udma_core_fifo_cfg_ctrl_en_set(), udma_core_fifo_cfg_ctrl_stop_set(), udma_core_fifo_cfg_ctrl_timeout_mon_set(), udma_core_fifo_cfg_evt_en_set(), udma_core_fifo_cfg_evt_num_bytes_set(), udma_cpi_cam_cfg_glob_en_set(), udma_cpi_cam_cfg_glob_format_set(), udma_cpi_cam_cfg_glob_framedrop_en_set(), udma_cpi_cam_cfg_glob_framedrop_val_set(), udma_cpi_cam_cfg_glob_frameslice_en_set(), udma_cpi_cam_cfg_ll_frameslice_llx_set(), udma_cpi_cam_cfg_ll_frameslice_lly_set(), udma_cpi_cam_cfg_rgb_sequence_set(), udma_cpi_cam_cfg_size_rowlen_set(), udma_cpi_cam_cfg_ur_frameslice_urx_set(), udma_cpi_cam_cfg_ur_frameslice_ury_set(), udma_cpi_cam_hsync_polarity_hsync_polarity_set(), udma_cpi_cam_rx_datasize_rx_datasize_set(), udma_cpi_cam_rx_dest_rx_dest_set(), udma_cpi_cam_vsync_polarity_vsync_polarity_set(), udma_ctrl_cfg_event_cmp_evt0_set(), udma_ctrl_cfg_event_cmp_evt1_set(), udma_ctrl_cfg_event_cmp_evt2_set(), udma_ctrl_cfg_event_cmp_evt3_set(), udma_ctrl_datamove0_size_en_set(), udma_ctrl_datamove0_size_size_set(), udma_ctrl_datamove0_size_stop_set(), udma_ctrl_datamove1_size_en_set(), udma_ctrl_datamove1_size_size_set(), udma_ctrl_datamove1_size_stop_set(), udma_ctrl_datamove_cfg_dest_id_0_set(), udma_ctrl_datamove_cfg_dest_id_1_set(), udma_ctrl_datamove_cfg_source_id_0_set(), udma_ctrl_datamove_cfg_source_id_1_set(), udma_ctrl_fifo_cfg_pop_id_set(), udma_ctrl_fifo_cfg_push_id_set(), udma_ctrl_timeout_ch0_cnt_set(), udma_ctrl_timeout_ch0_en_set(), udma_ctrl_timeout_ch0_mode_set(), udma_ctrl_timeout_ch0_source_id_set(), udma_ctrl_timeout_ch1_cnt_set(), udma_ctrl_timeout_ch1_en_set(), udma_ctrl_timeout_ch1_mode_set(), udma_ctrl_timeout_ch1_source_id_set(), udma_ctrl_timeout_ch2_cnt_set(), udma_ctrl_timeout_ch2_en_set(), udma_ctrl_timeout_ch2_mode_set(), udma_ctrl_timeout_ch2_source_id_set(), udma_ctrl_timeout_ch3_cnt_set(), udma_ctrl_timeout_ch3_en_set(), udma_ctrl_timeout_ch3_mode_set(), udma_ctrl_timeout_ch3_source_id_set(), udma_ctrl_timeout_ch4_cnt_set(), udma_ctrl_timeout_ch4_en_set(), udma_ctrl_timeout_ch4_mode_set(), udma_ctrl_timeout_ch4_source_id_set(), udma_ctrl_timeout_ch5_cnt_set(), udma_ctrl_timeout_ch5_en_set(), udma_ctrl_timeout_ch5_mode_set(), udma_ctrl_timeout_ch5_source_id_set(), udma_ctrl_timeout_ch6_cnt_set(), udma_ctrl_timeout_ch6_en_set(), udma_ctrl_timeout_ch6_mode_set(), udma_ctrl_timeout_ch6_source_id_set(), udma_ctrl_timeout_ch7_cnt_set(), udma_ctrl_timeout_ch7_en_set(), udma_ctrl_timeout_ch7_mode_set(), udma_ctrl_timeout_ch7_source_id_set(), udma_ctrl_timeout_pre0_clr_set(), udma_ctrl_timeout_pre0_cnt_set(), udma_ctrl_timeout_pre0_en_set(), udma_ctrl_timeout_pre1_clr_set(), udma_ctrl_timeout_pre1_cnt_set(), udma_ctrl_timeout_pre1_en_set(), udma_ctrl_timeout_pre2_clr_set(), udma_ctrl_timeout_pre2_cnt_set(), udma_ctrl_timeout_pre2_en_set(), udma_ctrl_timeout_pre3_clr_set(), udma_ctrl_timeout_pre3_cnt_set(), udma_ctrl_timeout_pre3_en_set(), udma_ctrl_timeout_pre4_clr_set(), udma_ctrl_timeout_pre4_cnt_set(), udma_ctrl_timeout_pre4_en_set(), udma_ctrl_timeout_pre5_clr_set(), udma_ctrl_timeout_pre5_cnt_set(), udma_ctrl_timeout_pre5_en_set(), udma_ctrl_timeout_pre6_clr_set(), udma_ctrl_timeout_pre6_cnt_set(), udma_ctrl_timeout_pre6_en_set(), udma_ctrl_timeout_pre7_clr_set(), udma_ctrl_timeout_pre7_cnt_set(), udma_ctrl_timeout_pre7_en_set(), udma_hyper_burst_enable_2d_enable_set(), udma_hyper_burst_enable_2d_mode_set(), udma_hyper_burst_enable_cs0_auto_burst_enable_set(), udma_hyper_burst_enable_cs0_maximum_check_enable_set(), udma_hyper_burst_enable_cs1_auto_burst_enable_set(), udma_hyper_burst_enable_cs1_maximum_check_enable_set(), udma_hyper_clk_div_data_set(), udma_hyper_clk_div_valid_set(), udma_hyper_device_dt0_set(), udma_hyper_device_dt1_set(), udma_hyper_device_sdio_set(), udma_hyper_device_type_set(), udma_hyper_ext_addr_reg_access_set(), udma_hyper_ext_addr_saddr_set(), udma_hyper_irq_en_en_set(), udma_hyper_irq_en_xip_en_set(), udma_hyper_mba0_mba0_set(), udma_hyper_mba0_reserved_set(), udma_hyper_mba1_mba1_set(), udma_hyper_mba1_reserved_set(), udma_hyper_ospi_alter_mode0_set(), udma_hyper_ospi_alter_mode1_set(), udma_hyper_ospi_alter_xip_mode0_set(), udma_hyper_ospi_alter_xip_mode1_set(), udma_hyper_ospi_cfg_addr_dtr_str_set(), udma_hyper_ospi_cfg_addr_size_set(), udma_hyper_ospi_cfg_cmd_dtr_str_set(), udma_hyper_ospi_cfg_cmd_size_set(), udma_hyper_ospi_cfg_data_dtr_msb_set(), udma_hyper_ospi_cfg_data_dtr_str_set(), udma_hyper_ospi_cfg_line_set(), udma_hyper_ospi_cfg_xip_addr_dtr_str_set(), udma_hyper_ospi_cfg_xip_addr_size_set(), udma_hyper_ospi_cfg_xip_cmd_dtr_str_set(), udma_hyper_ospi_cfg_xip_cmd_size_set(), udma_hyper_ospi_cfg_xip_data_dtr_msb_set(), udma_hyper_ospi_cfg_xip_data_dtr_str_set(), udma_hyper_ospi_cfg_xip_line_set(), udma_hyper_ospi_cmd_cmd_set(), udma_hyper_ospi_cmd_sdio_cmd_op_set(), udma_hyper_ospi_cmd_sdio_cmd_rsp_type_set(), udma_hyper_ospi_cmd_xip_cmd_set(), udma_hyper_ospi_cmd_xip_sdio_cmd_op_set(), udma_hyper_ospi_cmd_xip_sdio_cmd_rsp_type_set(), udma_hyper_ospi_csn_auto_en_set(), udma_hyper_ospi_csn_direct_ctrl_set(), udma_hyper_ospi_csn_index_set(), udma_hyper_ospi_csn_reserved_set(), udma_hyper_ospi_csn_sdio_auto_stop_set(), udma_hyper_ospi_csn_sdio_block_num_set(), udma_hyper_ospi_csn_sdio_block_size_set(), udma_hyper_ospi_csn_sdio_data_quad_ddr_set(), udma_hyper_ospi_csn_sdio_data_quad_set(), udma_hyper_ospi_csn_value_set(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_en_set(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_value_set(), udma_hyper_ospi_ram_opt_opt_read_en_cs_set(), udma_hyper_ospi_ram_opt_psram_addr_even_set(), udma_hyper_ospi_ram_opt_psram_cmd_en_set(), udma_hyper_ospi_ram_opt_psram_cross_boundary_en_set(), udma_hyper_ospi_ram_opt_psram_read_bit_set(), udma_hyper_ospi_ram_opt_real_addr_en_set(), udma_hyper_ospi_reg_xip_xip_latency0_set(), udma_hyper_ospi_reg_xip_xip_latency1_set(), udma_hyper_rx_dest_dest_set(), udma_hyper_rx_dest_dest_stream_set(), udma_hyper_status_reserved_set(), udma_hyper_status_rx_error_set(), udma_hyper_status_rx_tx_end_set(), udma_hyper_status_sdio_error_status_set(), udma_hyper_status_sdio_rx_tx_end_set(), udma_hyper_status_sdio_rx_tx_error_set(), udma_hyper_status_tx_error_set(), udma_hyper_timing_cfg_additional_latency_autocheck_en_set(), udma_hyper_timing_cfg_cs_max_set(), udma_hyper_timing_cfg_latency0_set(), udma_hyper_timing_cfg_latency1_set(), udma_hyper_timing_cfg_rw_recovery_set(), udma_hyper_timing_cfg_rwds_delay_set(), udma_hyper_trans_cfg_rxtx_set(), udma_hyper_trans_cfg_valid_set(), udma_hyper_trans_mode_auto_ena_set(), udma_hyper_trans_mode_stream_en_set(), udma_hyper_trans_mode_stream_xip_en_set(), udma_hyper_trans_mode_xip_en_set(), udma_hyper_trans_mode_xip_halted_set(), udma_hyper_tx_dest_dest_set(), udma_hyper_tx_dest_dest_stream_set(), udma_i2c_status_reg_idx_status_foll_eof_rcv_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_eof_snd_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_error_arlo_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_error_framing_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_purge_event_o_idx_set(), udma_i2c_status_reg_idx_status_foll_sof_rcv_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_sof_snd_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_unlock_event_o_idx_set(), udma_i2c_status_reg_idx_status_i2c_prescaler_set_div10_event_o_idx_set(), udma_i2c_status_reg_idx_status_i2c_soft_reset_event_o_idx_set(), udma_i2c_status_reg_idx_status_lead_command_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_error_arlo_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_error_framing_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_error_nack_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_purge_event_o_idx_set(), udma_i2c_status_reg_idx_status_lead_unlock_event_o_idx_set(), udma_mram_clk_div_data_set(), udma_mram_clk_div_enable_set(), udma_mram_clk_div_valid_set(), udma_mram_enable_2d_enable_set(), udma_mram_erase_addr_addr_lsb_set(), udma_mram_erase_addr_addr_msb_set(), udma_mram_erase_size_size_set(), udma_mram_ier_erase_en_set(), udma_mram_ier_program_en_set(), udma_mram_ier_rx_done_en_set(), udma_mram_ier_rx_xip_done_en_set(), udma_mram_ier_trim_config_en_set(), udma_mram_ier_xip_erase_en_set(), udma_mram_ier_xip_program_en_set(), udma_mram_ier_xip_trim_config_en_set(), udma_mram_isr_erase_done_set(), udma_mram_isr_program_done_set(), udma_mram_isr_rx_done_set(), udma_mram_isr_trim_config_done_set(), udma_mram_mode_dpd_set(), udma_mram_mode_eccbyps_set(), udma_mram_mode_nvr_set(), udma_mram_mode_operation_set(), udma_mram_mode_porb_set(), udma_mram_mode_retb_set(), udma_mram_mode_rstb_set(), udma_mram_mode_tmen_set(), udma_mram_rx_dest_dest_set(), udma_mram_status_ec_err_set(), udma_mram_status_erase_busy_set(), udma_mram_status_rx_busy_set(), udma_mram_status_tx_busy_set(), udma_mram_status_ue_err_set(), udma_mram_timing_cfg_ads_time_cnt_set(), udma_mram_timing_cfg_go_sup_time_cnt_set(), udma_mram_timing_cfg_men_time_cnt_set(), udma_mram_timing_cfg_pgs_time_cnt_set(), udma_mram_timing_cfg_prog_time_cnt_set(), udma_mram_timing_cfg_rw_time_cnt_set(), udma_mram_timing_cfg_strobe_time_cnt_set(), udma_mram_trans_cfg_rxtx_set(), udma_mram_trans_cfg_valid_set(), udma_mram_trans_mode_auto_ena_set(), udma_mram_trans_mode_reserved_set(), udma_mram_trans_mode_xip_en_set(), udma_mram_trans_mode_xip_halted_set(), udma_mram_trans_size_size_set(), udma_mram_tx_dest_dest_set(), udma_timestamp_reg_clk_cfg_clk_mux_en_set(), udma_timestamp_reg_clk_cfg_clk_mux_set(), udma_timestamp_reg_clk_cfg_gpio_sel_set(), udma_timestamp_reg_clk_cfg_prescaler_set(), udma_timestamp_reg_clk_cfg_pwm_sel_set(), udma_timestamp_reg_cmd_cnt_clr_set(), udma_timestamp_reg_cmd_cnt_stop_set(), udma_timestamp_reg_dest_rx_dest_set(), udma_timestamp_reg_setup_ch0_1_input_en_ch0_set(), udma_timestamp_reg_setup_ch0_1_input_en_ch1_set(), udma_timestamp_reg_setup_ch0_1_input_sel_ch0_set(), udma_timestamp_reg_setup_ch0_1_input_sel_ch1_set(), udma_timestamp_reg_setup_ch0_1_input_type_ch0_set(), udma_timestamp_reg_setup_ch0_1_input_type_ch1_set(), udma_timestamp_reg_setup_ch2_3_input_en_ch2_set(), udma_timestamp_reg_setup_ch2_3_input_en_ch3_set(), udma_timestamp_reg_setup_ch2_3_input_sel_ch2_set(), udma_timestamp_reg_setup_ch2_3_input_sel_ch3_set(), udma_timestamp_reg_setup_ch2_3_input_type_ch2_set(), udma_timestamp_reg_setup_ch2_3_input_type_ch3_set(), udma_timestamp_reg_setup_ch4_5_input_en_ch4_set(), udma_timestamp_reg_setup_ch4_5_input_en_ch5_set(), udma_timestamp_reg_setup_ch4_5_input_sel_ch4_set(), udma_timestamp_reg_setup_ch4_5_input_sel_ch5_set(), udma_timestamp_reg_setup_ch4_5_input_type_ch4_set(), udma_timestamp_reg_setup_ch4_5_input_type_ch5_set(), udma_timestamp_reg_setup_ch6_7_input_en_ch6_set(), udma_timestamp_reg_setup_ch6_7_input_en_ch7_set(), udma_timestamp_reg_setup_ch6_7_input_sel_ch6_set(), udma_timestamp_reg_setup_ch6_7_input_sel_ch7_set(), udma_timestamp_reg_setup_ch6_7_input_type_ch6_set(), udma_timestamp_reg_setup_ch6_7_input_type_ch7_set(), udma_timestamp_reg_setup_cnt_cnt_ext_en_set(), udma_timestamp_reg_setup_cnt_cnt_ext_sel_set(), and udma_timestamp_reg_setup_cnt_cnt_ext_type_set().
| #define GAP_BINSERT_R | ( | dst, | |
| src, | |||
| size, | |||
| off | |||
| ) |
| #define GAP_READ | ( | base, | |
| offset | |||
| ) |
Referenced by adv_timer_cg_ena_get(), adv_timer_cg_ena_gets(), adv_timer_cg_ena_set(), adv_timer_cg_get(), adv_timer_ch_mux_ch_sel_0_get(), adv_timer_ch_mux_ch_sel_0_gets(), adv_timer_ch_mux_ch_sel_0_set(), adv_timer_ch_mux_ch_sel_1_get(), adv_timer_ch_mux_ch_sel_1_gets(), adv_timer_ch_mux_ch_sel_1_set(), adv_timer_ch_mux_ch_sel_2_get(), adv_timer_ch_mux_ch_sel_2_gets(), adv_timer_ch_mux_ch_sel_2_set(), adv_timer_ch_mux_ch_sel_3_get(), adv_timer_ch_mux_ch_sel_3_gets(), adv_timer_ch_mux_ch_sel_3_set(), adv_timer_ch_mux_ch_sel_4_get(), adv_timer_ch_mux_ch_sel_4_gets(), adv_timer_ch_mux_ch_sel_4_set(), adv_timer_ch_mux_ch_sel_5_get(), adv_timer_ch_mux_ch_sel_5_gets(), adv_timer_ch_mux_ch_sel_5_set(), adv_timer_ch_mux_ch_sel_6_get(), adv_timer_ch_mux_ch_sel_6_gets(), adv_timer_ch_mux_ch_sel_6_set(), adv_timer_ch_mux_ch_sel_7_get(), adv_timer_ch_mux_ch_sel_7_gets(), adv_timer_ch_mux_ch_sel_7_set(), adv_timer_ch_mux_get(), adv_timer_event_cfg_ena_get(), adv_timer_event_cfg_ena_gets(), adv_timer_event_cfg_ena_set(), adv_timer_event_cfg_get(), adv_timer_event_cfg_sel0_get(), adv_timer_event_cfg_sel0_gets(), adv_timer_event_cfg_sel0_set(), adv_timer_event_cfg_sel1_get(), adv_timer_event_cfg_sel1_gets(), adv_timer_event_cfg_sel1_set(), adv_timer_event_cfg_sel2_get(), adv_timer_event_cfg_sel2_gets(), adv_timer_event_cfg_sel2_set(), adv_timer_event_cfg_sel3_get(), adv_timer_event_cfg_sel3_gets(), adv_timer_event_cfg_sel3_set(), adv_timer_t0_cmd_arm_get(), adv_timer_t0_cmd_arm_gets(), adv_timer_t0_cmd_arm_set(), adv_timer_t0_cmd_get(), adv_timer_t0_cmd_reset_get(), adv_timer_t0_cmd_reset_gets(), adv_timer_t0_cmd_reset_set(), adv_timer_t0_cmd_rfu_get(), adv_timer_t0_cmd_rfu_gets(), adv_timer_t0_cmd_rfu_set(), adv_timer_t0_cmd_start_get(), adv_timer_t0_cmd_start_gets(), adv_timer_t0_cmd_start_set(), adv_timer_t0_cmd_stop_get(), adv_timer_t0_cmd_stop_gets(), adv_timer_t0_cmd_stop_set(), adv_timer_t0_cmd_update_get(), adv_timer_t0_cmd_update_gets(), adv_timer_t0_cmd_update_set(), adv_timer_t0_config_clksel_get(), adv_timer_t0_config_clksel_gets(), adv_timer_t0_config_clksel_set(), adv_timer_t0_config_get(), adv_timer_t0_config_insel_get(), adv_timer_t0_config_insel_gets(), adv_timer_t0_config_insel_set(), adv_timer_t0_config_mode_get(), adv_timer_t0_config_mode_gets(), adv_timer_t0_config_mode_set(), adv_timer_t0_config_presc_get(), adv_timer_t0_config_presc_gets(), adv_timer_t0_config_presc_set(), adv_timer_t0_config_updownsel_get(), adv_timer_t0_config_updownsel_gets(), adv_timer_t0_config_updownsel_set(), adv_timer_t0_counter_counter_get(), adv_timer_t0_counter_counter_gets(), adv_timer_t0_counter_counter_set(), adv_timer_t0_counter_get(), adv_timer_t0_th_channel0_get(), adv_timer_t0_th_channel0_lut_get(), adv_timer_t0_th_channel0_mode_get(), adv_timer_t0_th_channel0_mode_gets(), adv_timer_t0_th_channel0_mode_set(), adv_timer_t0_th_channel0_th_get(), adv_timer_t0_th_channel0_th_gets(), adv_timer_t0_th_channel0_th_set(), adv_timer_t0_th_channel1_get(), adv_timer_t0_th_channel1_lut_get(), adv_timer_t0_th_channel1_mode_get(), adv_timer_t0_th_channel1_mode_gets(), adv_timer_t0_th_channel1_mode_set(), adv_timer_t0_th_channel1_th_get(), adv_timer_t0_th_channel1_th_gets(), adv_timer_t0_th_channel1_th_set(), adv_timer_t0_th_channel2_get(), adv_timer_t0_th_channel2_lut_get(), adv_timer_t0_th_channel2_mode_get(), adv_timer_t0_th_channel2_mode_gets(), adv_timer_t0_th_channel2_mode_set(), adv_timer_t0_th_channel2_th_get(), adv_timer_t0_th_channel2_th_gets(), adv_timer_t0_th_channel2_th_set(), adv_timer_t0_th_channel3_get(), adv_timer_t0_th_channel3_lut_get(), adv_timer_t0_th_channel3_mode_get(), adv_timer_t0_th_channel3_mode_gets(), adv_timer_t0_th_channel3_mode_set(), adv_timer_t0_th_channel3_th_get(), adv_timer_t0_th_channel3_th_gets(), adv_timer_t0_th_channel3_th_set(), adv_timer_t0_threshold_get(), adv_timer_t0_threshold_th_hi_get(), adv_timer_t0_threshold_th_hi_gets(), adv_timer_t0_threshold_th_hi_set(), adv_timer_t0_threshold_th_lo_get(), adv_timer_t0_threshold_th_lo_gets(), adv_timer_t0_threshold_th_lo_set(), adv_timer_t1_cmd_arm_get(), adv_timer_t1_cmd_arm_gets(), adv_timer_t1_cmd_arm_set(), adv_timer_t1_cmd_get(), adv_timer_t1_cmd_reset_get(), adv_timer_t1_cmd_reset_gets(), adv_timer_t1_cmd_reset_set(), adv_timer_t1_cmd_start_get(), adv_timer_t1_cmd_start_gets(), adv_timer_t1_cmd_start_set(), adv_timer_t1_cmd_stop_get(), adv_timer_t1_cmd_stop_gets(), adv_timer_t1_cmd_stop_set(), adv_timer_t1_cmd_update_get(), adv_timer_t1_cmd_update_gets(), adv_timer_t1_cmd_update_set(), adv_timer_t1_config_clksel_get(), adv_timer_t1_config_clksel_gets(), adv_timer_t1_config_clksel_set(), adv_timer_t1_config_get(), adv_timer_t1_config_insel_get(), adv_timer_t1_config_insel_gets(), adv_timer_t1_config_insel_set(), adv_timer_t1_config_mode_get(), adv_timer_t1_config_mode_gets(), adv_timer_t1_config_mode_set(), adv_timer_t1_config_presc_get(), adv_timer_t1_config_presc_gets(), adv_timer_t1_config_presc_set(), adv_timer_t1_config_updownsel_get(), adv_timer_t1_config_updownsel_gets(), adv_timer_t1_config_updownsel_set(), adv_timer_t1_counter_counter_get(), adv_timer_t1_counter_counter_gets(), adv_timer_t1_counter_counter_set(), adv_timer_t1_counter_get(), adv_timer_t1_th_channel0_get(), adv_timer_t1_th_channel0_lut_get(), adv_timer_t1_th_channel0_mode_get(), adv_timer_t1_th_channel0_mode_gets(), adv_timer_t1_th_channel0_mode_set(), adv_timer_t1_th_channel0_th_get(), adv_timer_t1_th_channel0_th_gets(), adv_timer_t1_th_channel0_th_set(), adv_timer_t1_th_channel1_get(), adv_timer_t1_th_channel1_lut_get(), adv_timer_t1_th_channel1_mode_get(), adv_timer_t1_th_channel1_mode_gets(), adv_timer_t1_th_channel1_mode_set(), adv_timer_t1_th_channel1_th_get(), adv_timer_t1_th_channel1_th_gets(), adv_timer_t1_th_channel1_th_set(), adv_timer_t1_th_channel2_get(), adv_timer_t1_th_channel2_lut_get(), adv_timer_t1_th_channel2_mode_get(), adv_timer_t1_th_channel2_mode_gets(), adv_timer_t1_th_channel2_mode_set(), adv_timer_t1_th_channel2_th_get(), adv_timer_t1_th_channel2_th_gets(), adv_timer_t1_th_channel2_th_set(), adv_timer_t1_th_channel3_get(), adv_timer_t1_th_channel3_lut_get(), adv_timer_t1_th_channel3_mode_get(), adv_timer_t1_th_channel3_mode_gets(), adv_timer_t1_th_channel3_mode_set(), adv_timer_t1_th_channel3_th_get(), adv_timer_t1_th_channel3_th_gets(), adv_timer_t1_th_channel3_th_set(), adv_timer_t1_threshold_get(), adv_timer_t1_threshold_th_hi_get(), adv_timer_t1_threshold_th_hi_gets(), adv_timer_t1_threshold_th_hi_set(), adv_timer_t1_threshold_th_lo_get(), adv_timer_t1_threshold_th_lo_gets(), adv_timer_t1_threshold_th_lo_set(), adv_timer_t2_cmd_arm_get(), adv_timer_t2_cmd_arm_gets(), adv_timer_t2_cmd_arm_set(), adv_timer_t2_cmd_get(), adv_timer_t2_cmd_reset_get(), adv_timer_t2_cmd_reset_gets(), adv_timer_t2_cmd_reset_set(), adv_timer_t2_cmd_start_get(), adv_timer_t2_cmd_start_gets(), adv_timer_t2_cmd_start_set(), adv_timer_t2_cmd_stop_get(), adv_timer_t2_cmd_stop_gets(), adv_timer_t2_cmd_stop_set(), adv_timer_t2_cmd_update_get(), adv_timer_t2_cmd_update_gets(), adv_timer_t2_cmd_update_set(), adv_timer_t2_config_clksel_get(), adv_timer_t2_config_clksel_gets(), adv_timer_t2_config_clksel_set(), adv_timer_t2_config_get(), adv_timer_t2_config_insel_get(), adv_timer_t2_config_insel_gets(), adv_timer_t2_config_insel_set(), adv_timer_t2_config_mode_get(), adv_timer_t2_config_mode_gets(), adv_timer_t2_config_mode_set(), adv_timer_t2_config_presc_get(), adv_timer_t2_config_presc_gets(), adv_timer_t2_config_presc_set(), adv_timer_t2_config_updownsel_get(), adv_timer_t2_config_updownsel_gets(), adv_timer_t2_config_updownsel_set(), adv_timer_t2_counter_counter_get(), adv_timer_t2_counter_counter_gets(), adv_timer_t2_counter_counter_set(), adv_timer_t2_counter_get(), adv_timer_t2_th_channel0_get(), adv_timer_t2_th_channel0_lut_get(), adv_timer_t2_th_channel0_mode_get(), adv_timer_t2_th_channel0_mode_gets(), adv_timer_t2_th_channel0_mode_set(), adv_timer_t2_th_channel0_th_get(), adv_timer_t2_th_channel0_th_gets(), adv_timer_t2_th_channel0_th_set(), adv_timer_t2_th_channel1_get(), adv_timer_t2_th_channel1_lut_get(), adv_timer_t2_th_channel1_mode_get(), adv_timer_t2_th_channel1_mode_gets(), adv_timer_t2_th_channel1_mode_set(), adv_timer_t2_th_channel1_th_get(), adv_timer_t2_th_channel1_th_gets(), adv_timer_t2_th_channel1_th_set(), adv_timer_t2_th_channel2_get(), adv_timer_t2_th_channel2_lut_get(), adv_timer_t2_th_channel2_mode_get(), adv_timer_t2_th_channel2_mode_gets(), adv_timer_t2_th_channel2_mode_set(), adv_timer_t2_th_channel2_th_get(), adv_timer_t2_th_channel2_th_gets(), adv_timer_t2_th_channel2_th_set(), adv_timer_t2_th_channel3_get(), adv_timer_t2_th_channel3_lut_get(), adv_timer_t2_th_channel3_mode_get(), adv_timer_t2_th_channel3_mode_gets(), adv_timer_t2_th_channel3_mode_set(), adv_timer_t2_th_channel3_th_get(), adv_timer_t2_th_channel3_th_gets(), adv_timer_t2_th_channel3_th_set(), adv_timer_t2_threshold_get(), adv_timer_t2_threshold_th_hi_get(), adv_timer_t2_threshold_th_hi_gets(), adv_timer_t2_threshold_th_hi_set(), adv_timer_t2_threshold_th_lo_get(), adv_timer_t2_threshold_th_lo_gets(), adv_timer_t2_threshold_th_lo_set(), adv_timer_t3_cmd_arm_get(), adv_timer_t3_cmd_arm_gets(), adv_timer_t3_cmd_arm_set(), adv_timer_t3_cmd_get(), adv_timer_t3_cmd_reset_get(), adv_timer_t3_cmd_reset_gets(), adv_timer_t3_cmd_reset_set(), adv_timer_t3_cmd_start_get(), adv_timer_t3_cmd_start_gets(), adv_timer_t3_cmd_start_set(), adv_timer_t3_cmd_stop_get(), adv_timer_t3_cmd_stop_gets(), adv_timer_t3_cmd_stop_set(), adv_timer_t3_cmd_update_get(), adv_timer_t3_cmd_update_gets(), adv_timer_t3_cmd_update_set(), adv_timer_t3_config_clksel_get(), adv_timer_t3_config_clksel_gets(), adv_timer_t3_config_clksel_set(), adv_timer_t3_config_get(), adv_timer_t3_config_insel_get(), adv_timer_t3_config_insel_gets(), adv_timer_t3_config_insel_set(), adv_timer_t3_config_mode_get(), adv_timer_t3_config_mode_gets(), adv_timer_t3_config_mode_set(), adv_timer_t3_config_presc_get(), adv_timer_t3_config_presc_gets(), adv_timer_t3_config_presc_set(), adv_timer_t3_config_updownsel_get(), adv_timer_t3_config_updownsel_gets(), adv_timer_t3_config_updownsel_set(), adv_timer_t3_counter_counter_get(), adv_timer_t3_counter_counter_gets(), adv_timer_t3_counter_counter_set(), adv_timer_t3_counter_get(), adv_timer_t3_th_channel0_get(), adv_timer_t3_th_channel0_lut_get(), adv_timer_t3_th_channel0_mode_get(), adv_timer_t3_th_channel0_mode_gets(), adv_timer_t3_th_channel0_mode_set(), adv_timer_t3_th_channel0_th_get(), adv_timer_t3_th_channel0_th_gets(), adv_timer_t3_th_channel0_th_set(), adv_timer_t3_th_channel1_get(), adv_timer_t3_th_channel1_lut_get(), adv_timer_t3_th_channel1_mode_get(), adv_timer_t3_th_channel1_mode_gets(), adv_timer_t3_th_channel1_mode_set(), adv_timer_t3_th_channel1_th_get(), adv_timer_t3_th_channel1_th_gets(), adv_timer_t3_th_channel1_th_set(), adv_timer_t3_th_channel2_get(), adv_timer_t3_th_channel2_lut_get(), adv_timer_t3_th_channel2_mode_get(), adv_timer_t3_th_channel2_mode_gets(), adv_timer_t3_th_channel2_mode_set(), adv_timer_t3_th_channel2_th_get(), adv_timer_t3_th_channel2_th_gets(), adv_timer_t3_th_channel2_th_set(), adv_timer_t3_th_channel3_get(), adv_timer_t3_th_channel3_lut_get(), adv_timer_t3_th_channel3_mode_get(), adv_timer_t3_th_channel3_mode_gets(), adv_timer_t3_th_channel3_mode_set(), adv_timer_t3_th_channel3_th_get(), adv_timer_t3_th_channel3_th_gets(), adv_timer_t3_th_channel3_th_set(), adv_timer_t3_threshold_get(), adv_timer_t3_threshold_th_hi_get(), adv_timer_t3_threshold_th_hi_gets(), adv_timer_t3_threshold_th_hi_set(), adv_timer_t3_threshold_th_lo_get(), adv_timer_t3_threshold_th_lo_gets(), adv_timer_t3_threshold_th_lo_set(), apb_soc_ctrl_bootsel_get(), apb_soc_ctrl_cl_busy_get(), apb_soc_ctrl_cl_isolate_get(), apb_soc_ctrl_clk_div_clu_get(), apb_soc_ctrl_clk_div_i3c_get(), apb_soc_ctrl_clk_div_per_get(), apb_soc_ctrl_clk_div_soc_get(), apb_soc_ctrl_clk_en_quiddikey_get(), apb_soc_ctrl_clk_sel_get(), apb_soc_ctrl_corestatus_get(), apb_soc_ctrl_fc_boot_get(), apb_soc_ctrl_fc_fetch_get(), apb_soc_ctrl_info_get(), apb_soc_ctrl_jtagreg_get(), apb_soc_ctrl_padcfg0_get(), apb_soc_ctrl_padcfg10_get(), apb_soc_ctrl_padcfg11_get(), apb_soc_ctrl_padcfg12_get(), apb_soc_ctrl_padcfg13_get(), apb_soc_ctrl_padcfg14_get(), apb_soc_ctrl_padcfg15_get(), apb_soc_ctrl_padcfg16_get(), apb_soc_ctrl_padcfg17_get(), apb_soc_ctrl_padcfg18_get(), apb_soc_ctrl_padcfg19_get(), apb_soc_ctrl_padcfg1_get(), apb_soc_ctrl_padcfg20_get(), apb_soc_ctrl_padcfg21_get(), apb_soc_ctrl_padcfg22_get(), apb_soc_ctrl_padcfg23_get(), apb_soc_ctrl_padcfg2_get(), apb_soc_ctrl_padcfg3_get(), apb_soc_ctrl_padcfg4_get(), apb_soc_ctrl_padcfg5_get(), apb_soc_ctrl_padcfg6_get(), apb_soc_ctrl_padcfg7_get(), apb_soc_ctrl_padcfg8_get(), apb_soc_ctrl_padcfg9_get(), apb_soc_ctrl_padfun0_get(), apb_soc_ctrl_padfun1_get(), apb_soc_ctrl_padfun2_get(), apb_soc_ctrl_padfun3_get(), apb_soc_ctrl_padfun4_get(), apb_soc_ctrl_padfun5_get(), apb_soc_ctrl_reserved0_get(), apb_soc_ctrl_reserved10_get(), apb_soc_ctrl_reserved11_get(), apb_soc_ctrl_reserved12_get(), apb_soc_ctrl_reserved1_get(), apb_soc_ctrl_reserved2_get(), apb_soc_ctrl_reserved3_get(), apb_soc_ctrl_reserved4_get(), apb_soc_ctrl_reserved5_get(), apb_soc_ctrl_reserved6_get(), apb_soc_ctrl_reserved7_get(), apb_soc_ctrl_reserved8_get(), apb_soc_ctrl_reserved9_get(), apb_soc_ctrl_rwm_l2_intl_get(), apb_soc_ctrl_rwm_l2_pri_get(), apb_soc_ctrl_sleep_ctrl_get(), apb_soc_ctrl_sleep_ctrl_old_get(), apb_soc_ctrl_supervisor_dbg_get(), apb_soc_ctrl_wakeup_ctrl_get(), apb_soc_ctrl_wd_rst_get(), cl_dma_cmd_get(), cl_dma_status_get(), cluster_ctrl_unit_boot_addr0_get(), cluster_ctrl_unit_boot_addr1_get(), cluster_ctrl_unit_boot_addr2_get(), cluster_ctrl_unit_boot_addr3_get(), cluster_ctrl_unit_boot_addr4_get(), cluster_ctrl_unit_boot_addr5_get(), cluster_ctrl_unit_boot_addr6_get(), cluster_ctrl_unit_boot_addr7_get(), cluster_ctrl_unit_clock_gate_get(), cluster_ctrl_unit_dbg_halt_mask_get(), cluster_ctrl_unit_dbg_halt_status_get(), cluster_ctrl_unit_dbg_resume_get(), cluster_ctrl_unit_eoc_get(), cluster_ctrl_unit_fetch_en_get(), cluster_ctrl_unit_tcdm_arb_policy_ch0_get(), cluster_ctrl_unit_tcdm_arb_policy_ch0_rep_get(), cluster_ctrl_unit_tcdm_arb_policy_ch1_get(), cluster_ctrl_unit_tcdm_arb_policy_ch1_rep_get(), cluster_icache_ctrl_enable_get(), cluster_icache_ctrl_enable_l1_l15_prefetch_get(), cluster_icache_ctrl_enable_special_core_cache_get(), cluster_icache_ctrl_flush_get(), cluster_icache_ctrl_l0_flush_get(), cluster_icache_ctrl_sel_flush_get(), decompressor_bit_read_reg_bit_read_get(), decompressor_bit_read_reg_bit_read_gets(), decompressor_bit_read_reg_get(), decompressor_clock_enable_reg_clock_enable_get(), decompressor_clock_enable_reg_clock_enable_gets(), decompressor_clock_enable_reg_clock_enable_set(), decompressor_clock_enable_reg_get(), decompressor_conf_reg_decompr_direction_get(), decompressor_conf_reg_decompr_direction_gets(), decompressor_conf_reg_decompr_direction_set(), decompressor_conf_reg_decompr_mode_get(), decompressor_conf_reg_decompr_mode_gets(), decompressor_conf_reg_decompr_mode_set(), decompressor_conf_reg_extension_type_get(), decompressor_conf_reg_extension_type_gets(), decompressor_conf_reg_extension_type_set(), decompressor_conf_reg_get(), decompressor_conf_reg_item_bit_width_get(), decompressor_conf_reg_item_bit_width_gets(), decompressor_conf_reg_item_bit_width_set(), decompressor_conf_reg_item_to_decompress_get(), decompressor_conf_reg_item_to_decompress_gets(), decompressor_conf_reg_item_to_decompress_set(), decompressor_conf_reg_sign_extension_get(), decompressor_conf_reg_sign_extension_gets(), decompressor_conf_reg_sign_extension_set(), decompressor_conf_reg_start_bit_get(), decompressor_conf_reg_start_bit_gets(), decompressor_conf_reg_start_bit_set(), decompressor_conf_reg_start_byte_get(), decompressor_conf_reg_start_byte_gets(), decompressor_conf_reg_start_byte_set(), decompressor_l2_addr_reg_get(), decompressor_l2_addr_reg_l2_start_addr_get(), decompressor_l2_addr_reg_l2_start_addr_gets(), decompressor_l2_count_reg_get(), decompressor_l2_count_reg_l2_linear_count_get(), decompressor_l2_count_reg_l2_linear_count_gets(), decompressor_l2_count_reg_l2_linear_count_set(), decompressor_l2_stride_reg_get(), decompressor_l2_stride_reg_l2_stride_count_get(), decompressor_l2_stride_reg_l2_stride_count_gets(), decompressor_l2_stride_reg_l2_stride_count_set(), decompressor_lut_write_reg_get(), decompressor_lut_write_reg_lut_addr_get(), decompressor_lut_write_reg_lut_addr_gets(), decompressor_lut_write_reg_lut_addr_set(), decompressor_lut_write_reg_lut_data_get(), decompressor_lut_write_reg_lut_data_gets(), decompressor_lut_write_reg_lut_data_set(), decompressor_mode_reg_get(), decompressor_mode_reg_transf_mode_get(), decompressor_mode_reg_transf_mode_gets(), decompressor_mode_reg_transf_mode_set(), decompressor_push_cmd_reg_get(), decompressor_push_cmd_reg_trigger_get(), decompressor_push_cmd_reg_trigger_gets(), decompressor_push_cmd_reg_trigger_set(), decompressor_soft_reset_reg_get(), decompressor_soft_reset_reg_soft_reset_get(), decompressor_soft_reset_reg_soft_reset_gets(), decompressor_soft_reset_reg_soft_reset_set(), decompressor_special_symbol_reg_get(), decompressor_special_symbol_reg_special_symbol_get(), decompressor_special_symbol_reg_special_symbol_gets(), decompressor_status_reg_get(), decompressor_status_reg_status_get(), decompressor_status_reg_status_gets(), decompressor_status_reg_status_set(), decompressor_tcdm_addr_reg_get(), decompressor_tcdm_addr_reg_tcdm_start_addr_get(), decompressor_tcdm_addr_reg_tcdm_start_addr_gets(), decompressor_tcdm_count_reg_get(), decompressor_tcdm_count_reg_tcdm_linear_count_get(), decompressor_tcdm_count_reg_tcdm_linear_count_gets(), decompressor_tcdm_count_reg_tcdm_linear_count_set(), decompressor_tcdm_stride_reg_get(), decompressor_tcdm_stride_reg_tcdm_stride_count_get(), decompressor_tcdm_stride_reg_tcdm_stride_count_gets(), decompressor_tcdm_stride_reg_tcdm_stride_count_set(), efuse_cfg_get(), efuse_cmd_get(), fc_icache_ctrl_enable_get(), fc_icache_ctrl_flush_get(), fc_icache_ctrl_sel_flush_get(), fc_icache_ctrl_status_get(), fc_itc_ack_clear_get(), fc_itc_ack_get(), fc_itc_ack_set_get(), fc_itc_fifo_get(), fc_itc_mask_clear_get(), fc_itc_mask_get(), fc_itc_mask_set_get(), fc_itc_status_clear_get(), fc_itc_status_get(), fc_itc_status_set_get(), fc_mpu_apb_rule0_get(), fc_mpu_apb_rule1_get(), fc_mpu_apb_rule2_get(), fc_mpu_apb_rule3_get(), fc_mpu_apb_rule4_get(), fc_mpu_apb_rule5_get(), fc_mpu_apb_rule6_get(), fc_mpu_apb_rule7_get(), fc_mpu_fc_tcdm_rule0_get(), fc_mpu_fc_tcdm_rule1_get(), fc_mpu_fc_tcdm_rule2_get(), fc_mpu_fc_tcdm_rule3_get(), fc_mpu_fc_tcdm_rule4_get(), fc_mpu_fc_tcdm_rule5_get(), fc_mpu_fc_tcdm_rule6_get(), fc_mpu_fc_tcdm_rule7_get(), fc_mpu_l2_rule0_get(), fc_mpu_l2_rule1_get(), fc_mpu_l2_rule2_get(), fc_mpu_l2_rule3_get(), fc_mpu_l2_rule4_get(), fc_mpu_l2_rule5_get(), fc_mpu_l2_rule6_get(), fc_mpu_l2_rule7_get(), fc_mpu_mpu_enable_get(), fll_ccr1_clk0_div_get(), fll_ccr1_clk0_div_gets(), fll_ccr1_clk0_div_set(), fll_ccr1_clk1_div_get(), fll_ccr1_clk1_div_gets(), fll_ccr1_clk1_div_set(), fll_ccr1_clk2_div_get(), fll_ccr1_clk2_div_gets(), fll_ccr1_clk2_div_set(), fll_ccr1_clk3_div_get(), fll_ccr1_clk3_div_gets(), fll_ccr1_clk3_div_set(), fll_ccr1_get(), fll_ccr2_ckg0_get(), fll_ccr2_ckg0_gets(), fll_ccr2_ckg0_set(), fll_ccr2_ckg1_get(), fll_ccr2_ckg1_gets(), fll_ccr2_ckg1_set(), fll_ccr2_ckg2_get(), fll_ccr2_ckg2_gets(), fll_ccr2_ckg2_set(), fll_ccr2_ckg3_get(), fll_ccr2_ckg3_gets(), fll_ccr2_ckg3_set(), fll_ccr2_clk0_sel_get(), fll_ccr2_clk0_sel_gets(), fll_ccr2_clk0_sel_set(), fll_ccr2_clk1_sel_get(), fll_ccr2_clk1_sel_gets(), fll_ccr2_clk1_sel_set(), fll_ccr2_clk2_sel_get(), fll_ccr2_clk2_sel_gets(), fll_ccr2_clk2_sel_set(), fll_ccr2_clk3_sel_get(), fll_ccr2_clk3_sel_gets(), fll_ccr2_clk3_sel_set(), fll_ccr2_get(), fll_drr_dco_max_get(), fll_drr_dco_max_gets(), fll_drr_dco_max_set(), fll_drr_dco_min_get(), fll_drr_dco_min_gets(), fll_drr_dco_min_set(), fll_drr_get(), fll_f0cr1_dco_en_get(), fll_f0cr1_dco_en_gets(), fll_f0cr1_dco_en_set(), fll_f0cr1_get(), fll_f0cr1_itg_per_get(), fll_f0cr1_itg_per_gets(), fll_f0cr1_itg_per_set(), fll_f0cr1_lock_tol_get(), fll_f0cr1_lock_tol_gets(), fll_f0cr1_lock_tol_set(), fll_f0cr1_loop_gain_get(), fll_f0cr1_loop_gain_gets(), fll_f0cr1_loop_gain_set(), fll_f0cr1_op_mode_get(), fll_f0cr1_op_mode_gets(), fll_f0cr1_op_mode_set(), fll_f0cr1_stbl_get(), fll_f0cr1_stbl_gets(), fll_f0cr1_stbl_set(), fll_f0cr1_ttm_en_get(), fll_f0cr1_ttm_en_gets(), fll_f0cr1_ttm_en_set(), fll_f0cr2_dco_code_get(), fll_f0cr2_dco_code_gets(), fll_f0cr2_dco_code_set(), fll_f0cr2_get(), fll_f0cr2_mfi_get(), fll_f0cr2_mfi_gets(), fll_f0cr2_mfi_set(), fll_f1cr1_dco_en_get(), fll_f1cr1_dco_en_gets(), fll_f1cr1_dco_en_set(), fll_f1cr1_get(), fll_f1cr1_itg_per_get(), fll_f1cr1_itg_per_gets(), fll_f1cr1_itg_per_set(), fll_f1cr1_lock_tol_get(), fll_f1cr1_lock_tol_gets(), fll_f1cr1_lock_tol_set(), fll_f1cr1_loop_gain_get(), fll_f1cr1_loop_gain_gets(), fll_f1cr1_loop_gain_set(), fll_f1cr1_op_mode_get(), fll_f1cr1_op_mode_gets(), fll_f1cr1_op_mode_set(), fll_f1cr1_stbl_get(), fll_f1cr1_stbl_gets(), fll_f1cr1_stbl_set(), fll_f1cr1_ttm_en_get(), fll_f1cr1_ttm_en_gets(), fll_f1cr1_ttm_en_set(), fll_f1cr2_dco_code_get(), fll_f1cr2_dco_code_gets(), fll_f1cr2_dco_code_set(), fll_f1cr2_get(), fll_f1cr2_mfi_get(), fll_f1cr2_mfi_gets(), fll_f1cr2_mfi_set(), fll_f2cr1_dco_en_get(), fll_f2cr1_dco_en_gets(), fll_f2cr1_dco_en_set(), fll_f2cr1_get(), fll_f2cr1_itg_per_get(), fll_f2cr1_itg_per_gets(), fll_f2cr1_itg_per_set(), fll_f2cr1_lock_tol_get(), fll_f2cr1_lock_tol_gets(), fll_f2cr1_lock_tol_set(), fll_f2cr1_loop_gain_get(), fll_f2cr1_loop_gain_gets(), fll_f2cr1_loop_gain_set(), fll_f2cr1_op_mode_get(), fll_f2cr1_op_mode_gets(), fll_f2cr1_op_mode_set(), fll_f2cr1_stbl_get(), fll_f2cr1_stbl_gets(), fll_f2cr1_stbl_set(), fll_f2cr1_ttm_en_get(), fll_f2cr1_ttm_en_gets(), fll_f2cr1_ttm_en_set(), fll_f2cr2_dco_code_get(), fll_f2cr2_dco_code_gets(), fll_f2cr2_dco_code_set(), fll_f2cr2_get(), fll_f2cr2_mfi_get(), fll_f2cr2_mfi_gets(), fll_f2cr2_mfi_set(), fll_f3cr1_dco_en_get(), fll_f3cr1_dco_en_gets(), fll_f3cr1_dco_en_set(), fll_f3cr1_get(), fll_f3cr1_itg_per_get(), fll_f3cr1_itg_per_gets(), fll_f3cr1_itg_per_set(), fll_f3cr1_lock_tol_get(), fll_f3cr1_lock_tol_gets(), fll_f3cr1_lock_tol_set(), fll_f3cr1_loop_gain_get(), fll_f3cr1_loop_gain_gets(), fll_f3cr1_loop_gain_set(), fll_f3cr1_op_mode_get(), fll_f3cr1_op_mode_gets(), fll_f3cr1_op_mode_set(), fll_f3cr1_stbl_get(), fll_f3cr1_stbl_gets(), fll_f3cr1_stbl_set(), fll_f3cr1_ttm_en_get(), fll_f3cr1_ttm_en_gets(), fll_f3cr1_ttm_en_set(), fll_f3cr2_dco_code_get(), fll_f3cr2_dco_code_gets(), fll_f3cr2_dco_code_set(), fll_f3cr2_get(), fll_f3cr2_mfi_get(), fll_f3cr2_mfi_gets(), fll_f3cr2_mfi_set(), fll_fcr1_get(), fll_fcr2_get(), fll_fsr_clmp_hi_err0_get(), fll_fsr_clmp_hi_err0_gets(), fll_fsr_clmp_hi_err0_set(), fll_fsr_clmp_hi_err1_get(), fll_fsr_clmp_hi_err1_gets(), fll_fsr_clmp_hi_err1_set(), fll_fsr_clmp_hi_err2_get(), fll_fsr_clmp_hi_err2_gets(), fll_fsr_clmp_hi_err2_set(), fll_fsr_clmp_hi_err3_get(), fll_fsr_clmp_hi_err3_gets(), fll_fsr_clmp_hi_err3_set(), fll_fsr_clmp_lo_err0_get(), fll_fsr_clmp_lo_err0_gets(), fll_fsr_clmp_lo_err0_set(), fll_fsr_clmp_lo_err1_get(), fll_fsr_clmp_lo_err1_gets(), fll_fsr_clmp_lo_err1_set(), fll_fsr_clmp_lo_err2_get(), fll_fsr_clmp_lo_err2_gets(), fll_fsr_clmp_lo_err2_set(), fll_fsr_clmp_lo_err3_get(), fll_fsr_clmp_lo_err3_gets(), fll_fsr_clmp_lo_err3_set(), fll_fsr_fdc_sat_err0_get(), fll_fsr_fdc_sat_err0_gets(), fll_fsr_fdc_sat_err0_set(), fll_fsr_fdc_sat_err1_get(), fll_fsr_fdc_sat_err1_gets(), fll_fsr_fdc_sat_err1_set(), fll_fsr_fdc_sat_err2_get(), fll_fsr_fdc_sat_err2_gets(), fll_fsr_fdc_sat_err2_set(), fll_fsr_fdc_sat_err3_get(), fll_fsr_fdc_sat_err3_gets(), fll_fsr_fdc_sat_err3_set(), fll_fsr_get(), fll_fsr_lock0_get(), fll_fsr_lock0_gets(), fll_fsr_lock0_set(), fll_fsr_lock1_get(), fll_fsr_lock1_gets(), fll_fsr_lock1_set(), fll_fsr_lock2_get(), fll_fsr_lock2_gets(), fll_fsr_lock2_set(), fll_fsr_lock3_get(), fll_fsr_lock3_gets(), fll_fsr_lock3_set(), fll_ttr_get(), fll_ttr_refresh_get(), fll_ttr_refresh_gets(), fll_ttr_refresh_set(), gpio_gpioen_00_31_get(), gpio_gpioen_00_31_gpioen_get(), gpio_gpioen_00_31_gpioen_gets(), gpio_gpioen_32_63_get(), gpio_gpioen_32_63_gpioen_get(), gpio_gpioen_32_63_gpioen_gets(), gpio_gpioen_64_95_get(), gpio_gpioen_64_95_gpioen_get(), gpio_gpioen_64_95_gpioen_gets(), gpio_gpioen_get(), gpio_inten_00_31_get(), gpio_inten_00_31_inten_get(), gpio_inten_00_31_inten_gets(), gpio_inten_32_63_get(), gpio_inten_32_63_inten_get(), gpio_inten_32_63_inten_gets(), gpio_inten_64_95_get(), gpio_inten_64_95_inten_get(), gpio_inten_64_95_inten_gets(), gpio_inten_get(), gpio_intstatus_00_31_get(), gpio_intstatus_00_31_intstatus_get(), gpio_intstatus_00_31_intstatus_gets(), gpio_intstatus_32_63_get(), gpio_intstatus_32_63_intstatus_get(), gpio_intstatus_32_63_intstatus_gets(), gpio_intstatus_64_95_get(), gpio_intstatus_64_95_intstatus_get(), gpio_intstatus_64_95_intstatus_gets(), gpio_intstatus_get(), gpio_inttype_00_15_get(), gpio_inttype_00_15_inttype_get(), gpio_inttype_00_15_inttype_gets(), gpio_inttype_16_31_get(), gpio_inttype_16_31_inttype_get(), gpio_inttype_16_31_inttype_gets(), gpio_inttype_32_47_get(), gpio_inttype_32_47_inttype_get(), gpio_inttype_32_47_inttype_gets(), gpio_inttype_48_63_get(), gpio_inttype_48_63_inttype_get(), gpio_inttype_48_63_inttype_gets(), gpio_inttype_64_79_get(), gpio_inttype_64_79_inttype_get(), gpio_inttype_64_79_inttype_gets(), gpio_inttype_80_95_get(), gpio_inttype_80_95_inttype_get(), gpio_inttype_80_95_inttype_gets(), gpio_inttype_get(), gpio_padcfg_00_03_get(), gpio_padcfg_00_03_padcfg_get(), gpio_padcfg_00_03_padcfg_gets(), gpio_padcfg_00_03_padcfg_set(), gpio_padcfg_04_07_get(), gpio_padcfg_04_07_padcfg_get(), gpio_padcfg_04_07_padcfg_gets(), gpio_padcfg_04_07_padcfg_set(), gpio_padcfg_08_11_get(), gpio_padcfg_08_11_padcfg_get(), gpio_padcfg_08_11_padcfg_gets(), gpio_padcfg_08_11_padcfg_set(), gpio_padcfg_12_15_get(), gpio_padcfg_12_15_padcfg_get(), gpio_padcfg_12_15_padcfg_gets(), gpio_padcfg_12_15_padcfg_set(), gpio_padcfg_16_19_get(), gpio_padcfg_16_19_padcfg_get(), gpio_padcfg_16_19_padcfg_gets(), gpio_padcfg_16_19_padcfg_set(), gpio_padcfg_20_23_get(), gpio_padcfg_20_23_padcfg_get(), gpio_padcfg_20_23_padcfg_gets(), gpio_padcfg_20_23_padcfg_set(), gpio_padcfg_24_27_get(), gpio_padcfg_24_27_padcfg_get(), gpio_padcfg_24_27_padcfg_gets(), gpio_padcfg_24_27_padcfg_set(), gpio_padcfg_28_31_get(), gpio_padcfg_28_31_padcfg_get(), gpio_padcfg_28_31_padcfg_gets(), gpio_padcfg_28_31_padcfg_set(), gpio_padcfg_32_35_get(), gpio_padcfg_32_35_padcfg_get(), gpio_padcfg_32_35_padcfg_gets(), gpio_padcfg_32_35_padcfg_set(), gpio_padcfg_36_39_get(), gpio_padcfg_36_39_padcfg_get(), gpio_padcfg_36_39_padcfg_gets(), gpio_padcfg_36_39_padcfg_set(), gpio_padcfg_40_43_get(), gpio_padcfg_40_43_padcfg_get(), gpio_padcfg_40_43_padcfg_gets(), gpio_padcfg_40_43_padcfg_set(), gpio_padcfg_44_47_get(), gpio_padcfg_44_47_padcfg_get(), gpio_padcfg_44_47_padcfg_gets(), gpio_padcfg_44_47_padcfg_set(), gpio_padcfg_48_51_get(), gpio_padcfg_48_51_padcfg_get(), gpio_padcfg_48_51_padcfg_gets(), gpio_padcfg_48_51_padcfg_set(), gpio_padcfg_52_55_get(), gpio_padcfg_52_55_padcfg_get(), gpio_padcfg_52_55_padcfg_gets(), gpio_padcfg_52_55_padcfg_set(), gpio_padcfg_56_59_get(), gpio_padcfg_56_59_padcfg_get(), gpio_padcfg_56_59_padcfg_gets(), gpio_padcfg_56_59_padcfg_set(), gpio_padcfg_60_63_get(), gpio_padcfg_60_63_padcfg_get(), gpio_padcfg_60_63_padcfg_gets(), gpio_padcfg_60_63_padcfg_set(), gpio_padcfg_64_67_get(), gpio_padcfg_64_67_padcfg_get(), gpio_padcfg_64_67_padcfg_gets(), gpio_padcfg_64_67_padcfg_set(), gpio_padcfg_68_71_get(), gpio_padcfg_68_71_padcfg_get(), gpio_padcfg_68_71_padcfg_gets(), gpio_padcfg_68_71_padcfg_set(), gpio_padcfg_72_75_get(), gpio_padcfg_72_75_padcfg_get(), gpio_padcfg_72_75_padcfg_gets(), gpio_padcfg_72_75_padcfg_set(), gpio_padcfg_76_79_get(), gpio_padcfg_76_79_padcfg_get(), gpio_padcfg_76_79_padcfg_gets(), gpio_padcfg_76_79_padcfg_set(), gpio_padcfg_80_83_get(), gpio_padcfg_80_83_padcfg_get(), gpio_padcfg_80_83_padcfg_gets(), gpio_padcfg_80_83_padcfg_set(), gpio_padcfg_84_87_get(), gpio_padcfg_84_87_padcfg_get(), gpio_padcfg_84_87_padcfg_gets(), gpio_padcfg_84_87_padcfg_set(), gpio_padcfg_88_91_get(), gpio_padcfg_88_91_padcfg_get(), gpio_padcfg_88_91_padcfg_gets(), gpio_padcfg_88_91_padcfg_set(), gpio_padcfg_92_95_get(), gpio_padcfg_92_95_padcfg_get(), gpio_padcfg_92_95_padcfg_gets(), gpio_padcfg_92_95_padcfg_set(), gpio_padcfg_get(), gpio_paddir_00_31_get(), gpio_paddir_00_31_paddir_get(), gpio_paddir_00_31_paddir_gets(), gpio_paddir_32_63_get(), gpio_paddir_32_63_paddir_get(), gpio_paddir_32_63_paddir_gets(), gpio_paddir_64_95_get(), gpio_paddir_64_95_paddir_get(), gpio_paddir_64_95_paddir_gets(), gpio_paddir_get(), gpio_padin_00_31_get(), gpio_padin_00_31_padin_get(), gpio_padin_00_31_padin_gets(), gpio_padin_32_63_get(), gpio_padin_32_63_padin_get(), gpio_padin_32_63_padin_gets(), gpio_padin_64_95_get(), gpio_padin_64_95_padin_get(), gpio_padin_64_95_padin_gets(), gpio_padin_get(), gpio_padout_00_31_get(), gpio_padout_00_31_padout_get(), gpio_padout_00_31_padout_gets(), gpio_padout_32_63_get(), gpio_padout_32_63_padout_get(), gpio_padout_32_63_padout_gets(), gpio_padout_64_95_get(), gpio_padout_64_95_padout_get(), gpio_padout_64_95_padout_gets(), gpio_padout_get(), gpio_padoutclr_00_31_get(), gpio_padoutclr_00_31_padoutclr_get(), gpio_padoutclr_00_31_padoutclr_gets(), gpio_padoutclr_32_63_get(), gpio_padoutclr_32_63_padoutclr_get(), gpio_padoutclr_32_63_padoutclr_gets(), gpio_padoutclr_64_95_get(), gpio_padoutclr_64_95_padoutclr_get(), gpio_padoutclr_64_95_padoutclr_gets(), gpio_padoutset_00_31_get(), gpio_padoutset_00_31_padoutset_get(), gpio_padoutset_00_31_padoutset_gets(), gpio_padoutset_32_63_get(), gpio_padoutset_32_63_padoutset_get(), gpio_padoutset_32_63_padoutset_gets(), gpio_padoutset_64_95_get(), gpio_padoutset_64_95_padoutset_get(), gpio_padoutset_64_95_padoutset_gets(), hal_cl_eu_barrier_team_get(), hal_cl_eu_dispatch_fifo_pop(), hal_udma_ctrl_timeout_mode_set(), hal_udma_ctrl_timeout_prescaler_enabled(), hal_udma_ctrl_timeout_timeout_start(), hal_udma_ctrl_timeout_timeout_stop(), hwce_acquire_get(), hwce_finished_jobs_get(), hwce_gen_config0_get(), hwce_gen_config1_get(), hwce_gen_config2_get(), hwce_gen_config3_get(), hwce_job_config0_aliased_get(), hwce_job_config0_ctx0_get(), hwce_job_config0_ctx1_get(), hwce_job_config1_aliased_get(), hwce_job_config1_ctx0_get(), hwce_job_config1_ctx1_get(), hwce_job_config2_aliased_get(), hwce_job_config2_ctx0_get(), hwce_job_config2_ctx1_get(), hwce_offloader_id_get(), hwce_running_job_get(), hwce_soft_clear_get(), hwce_status_get(), hwce_sw_evt_get(), hwce_trigger_get(), hwce_w_base_addr_aliased_get(), hwce_w_base_addr_ctx0_get(), hwce_w_base_addr_ctx1_get(), hwce_x_feat_stride_length_aliased_get(), hwce_x_feat_stride_length_ctx0_get(), hwce_x_feat_stride_length_ctx1_get(), hwce_x_in_base_addr_aliased_get(), hwce_x_in_base_addr_ctx0_get(), hwce_x_in_base_addr_ctx1_get(), hwce_x_line_stride_length_aliased_get(), hwce_x_line_stride_length_ctx0_get(), hwce_x_line_stride_length_ctx1_get(), hwce_x_trans_size_aliased_get(), hwce_x_trans_size_ctx0_get(), hwce_x_trans_size_ctx1_get(), hwce_y_feat_stride_length_aliased_get(), hwce_y_feat_stride_length_ctx0_get(), hwce_y_feat_stride_length_ctx1_get(), hwce_y_in_0_base_addr_aliased_get(), hwce_y_in_0_base_addr_ctx0_get(), hwce_y_in_0_base_addr_ctx1_get(), hwce_y_in_1_base_addr_aliased_get(), hwce_y_in_1_base_addr_ctx0_get(), hwce_y_in_1_base_addr_ctx1_get(), hwce_y_in_2_base_addr_aliased_get(), hwce_y_in_2_base_addr_ctx0_get(), hwce_y_in_2_base_addr_ctx1_get(), hwce_y_line_stride_length_aliased_get(), hwce_y_line_stride_length_ctx0_get(), hwce_y_line_stride_length_ctx1_get(), hwce_y_out_0_base_addr_aliased_get(), hwce_y_out_0_base_addr_ctx0_get(), hwce_y_out_0_base_addr_ctx1_get(), hwce_y_out_1_base_addr_aliased_get(), hwce_y_out_1_base_addr_ctx0_get(), hwce_y_out_1_base_addr_ctx1_get(), hwce_y_out_2_base_addr_aliased_get(), hwce_y_out_2_base_addr_ctx0_get(), hwce_y_out_2_base_addr_ctx1_get(), hwce_y_trans_size_aliased_get(), hwce_y_trans_size_ctx0_get(), hwce_y_trans_size_ctx1_get(), i3c_bus_avail_timer_reg_get(), i3c_bus_free_timer_reg_get(), i3c_cmd_tr_req_reg_1_get(), i3c_cmd_tr_req_reg_2_get(), i3c_data_rx_fifo_reg_get(), i3c_data_tx_fifo_reg_get(), i3c_device_addr_table_reg0_get(), i3c_device_addr_table_reg10_get(), i3c_device_addr_table_reg11_get(), i3c_device_addr_table_reg1_get(), i3c_device_addr_table_reg2_get(), i3c_device_addr_table_reg3_get(), i3c_device_addr_table_reg4_get(), i3c_device_addr_table_reg5_get(), i3c_device_addr_table_reg6_get(), i3c_device_addr_table_reg7_get(), i3c_device_addr_table_reg8_get(), i3c_device_addr_table_reg9_get(), i3c_device_char_table_reg0_0_get(), i3c_device_char_table_reg0_10_get(), i3c_device_char_table_reg0_11_get(), i3c_device_char_table_reg0_1_get(), i3c_device_char_table_reg0_2_get(), i3c_device_char_table_reg0_3_get(), i3c_device_char_table_reg0_4_get(), i3c_device_char_table_reg0_5_get(), i3c_device_char_table_reg0_6_get(), i3c_device_char_table_reg0_7_get(), i3c_device_char_table_reg0_8_get(), i3c_device_char_table_reg0_9_get(), i3c_device_char_table_reg1_0_get(), i3c_device_char_table_reg1_10_get(), i3c_device_char_table_reg1_11_get(), i3c_device_char_table_reg1_1_get(), i3c_device_char_table_reg1_2_get(), i3c_device_char_table_reg1_3_get(), i3c_device_char_table_reg1_4_get(), i3c_device_char_table_reg1_5_get(), i3c_device_char_table_reg1_6_get(), i3c_device_char_table_reg1_7_get(), i3c_device_char_table_reg1_8_get(), i3c_device_char_table_reg1_9_get(), i3c_device_char_table_reg2_0_get(), i3c_device_char_table_reg2_10_get(), i3c_device_char_table_reg2_11_get(), i3c_device_char_table_reg2_1_get(), i3c_device_char_table_reg2_2_get(), i3c_device_char_table_reg2_3_get(), i3c_device_char_table_reg2_4_get(), i3c_device_char_table_reg2_5_get(), i3c_device_char_table_reg2_6_get(), i3c_device_char_table_reg2_7_get(), i3c_device_char_table_reg2_8_get(), i3c_device_char_table_reg2_9_get(), i3c_device_char_table_reg3_0_get(), i3c_device_char_table_reg3_10_get(), i3c_device_char_table_reg3_11_get(), i3c_device_char_table_reg3_1_get(), i3c_device_char_table_reg3_2_get(), i3c_device_char_table_reg3_3_get(), i3c_device_char_table_reg3_4_get(), i3c_device_char_table_reg3_5_get(), i3c_device_char_table_reg3_6_get(), i3c_device_char_table_reg3_7_get(), i3c_device_char_table_reg3_8_get(), i3c_device_char_table_reg3_9_get(), i3c_ibi_data_reg_get(), i3c_ibi_resp_reg_get(), i3c_irq_status_reg_get(), i3c_mst_cntl_en_reg_get(), i3c_resp_reg_get(), i3c_tcas_timer_reg_get(), i3c_tcbp_timer_reg_get(), i3c_tcbsr_timer_reg_get(), i3c_tds_timer_reg_get(), i3c_thd_ddr_timer_reg_get(), i3c_thd_pp_timer_reg_get(), i3c_thd_sta_timer_reg_get(), i3c_thigh_od_timer_reg_get(), i3c_thigh_pp_timer_reg_get(), i3c_thigh_timer_reg_get(), i3c_tidle_timer_reg_get(), i3c_tlow_od_timer_reg_get(), i3c_tlow_pp_timer_reg_get(), i3c_tlow_timer_reg_get(), i3c_tsco_timer_reg_get(), i3c_tsu_sta_timer_reg_get(), i3c_tsu_stop_timer_reg_get(), i3c_tvd_data_timer_reg_get(), non_secured_riscv_debug_cause_get(), non_secured_riscv_debug_csr_hwlp0c_get(), non_secured_riscv_debug_csr_hwlp0e_get(), non_secured_riscv_debug_csr_hwlp0s_get(), non_secured_riscv_debug_csr_hwlp1c_get(), non_secured_riscv_debug_csr_hwlp1e_get(), non_secured_riscv_debug_csr_hwlp1s_get(), non_secured_riscv_debug_csr_mcause_get(), non_secured_riscv_debug_csr_mepc_get(), non_secured_riscv_debug_csr_mhartid_get(), non_secured_riscv_debug_csr_mstatus_get(), non_secured_riscv_debug_csr_mtvec_get(), non_secured_riscv_debug_csr_pccr_get(), non_secured_riscv_debug_csr_pcer_get(), non_secured_riscv_debug_csr_pcmr_get(), non_secured_riscv_debug_csr_privlv_get(), non_secured_riscv_debug_csr_uhartid_get(), non_secured_riscv_debug_ctrl_get(), non_secured_riscv_debug_gpr0_get(), non_secured_riscv_debug_gpr10_get(), non_secured_riscv_debug_gpr11_get(), non_secured_riscv_debug_gpr12_get(), non_secured_riscv_debug_gpr13_get(), non_secured_riscv_debug_gpr14_get(), non_secured_riscv_debug_gpr15_get(), non_secured_riscv_debug_gpr16_get(), non_secured_riscv_debug_gpr17_get(), non_secured_riscv_debug_gpr18_get(), non_secured_riscv_debug_gpr19_get(), non_secured_riscv_debug_gpr1_get(), non_secured_riscv_debug_gpr20_get(), non_secured_riscv_debug_gpr21_get(), non_secured_riscv_debug_gpr22_get(), non_secured_riscv_debug_gpr23_get(), non_secured_riscv_debug_gpr24_get(), non_secured_riscv_debug_gpr25_get(), non_secured_riscv_debug_gpr26_get(), non_secured_riscv_debug_gpr27_get(), non_secured_riscv_debug_gpr28_get(), non_secured_riscv_debug_gpr29_get(), non_secured_riscv_debug_gpr2_get(), non_secured_riscv_debug_gpr30_get(), non_secured_riscv_debug_gpr31_get(), non_secured_riscv_debug_gpr3_get(), non_secured_riscv_debug_gpr4_get(), non_secured_riscv_debug_gpr5_get(), non_secured_riscv_debug_gpr6_get(), non_secured_riscv_debug_gpr7_get(), non_secured_riscv_debug_gpr8_get(), non_secured_riscv_debug_gpr9_get(), non_secured_riscv_debug_hit_get(), non_secured_riscv_debug_ie_get(), non_secured_riscv_debug_npc_get(), non_secured_riscv_debug_ppc_get(), power_manager_dlcpd_idl_ifr_get(), power_manager_dlcpd_idn_ifr_get(), power_manager_dlcpd_ifr_get(), power_manager_dlcpd_imr_get(), power_manager_dlcpd_iok_ifr_get(), power_manager_dlcpd_iup_ifr_get(), power_manager_dlcpd_mpacr_get(), power_manager_dlcpd_mpadr_get(), power_manager_dlcpd_msr_get(), quiddikey_ar_get(), quiddikey_cr_get(), quiddikey_dir_get(), quiddikey_dor_get(), quiddikey_hw_id_get(), quiddikey_hw_info_get(), quiddikey_hw_ruc0_get(), quiddikey_hw_ruc1_get(), quiddikey_hw_setting_get(), quiddikey_hw_ver_get(), quiddikey_ier_get(), quiddikey_if_sr_get(), quiddikey_imr_get(), quiddikey_isr_get(), quiddikey_key_dest_get(), quiddikey_misc_get(), quiddikey_sr_get(), quiddikey_test_get(), rtc_apb_cr_get(), rtc_apb_dr_get(), rtc_apb_icr_get(), rtc_apb_ifr_get(), rtc_apb_imr_get(), rtc_apb_sr_get(), rtc_reserved_get(), secured_riscv_debug_cause_get(), secured_riscv_debug_csr_hwlp0c_get(), secured_riscv_debug_csr_hwlp0e_get(), secured_riscv_debug_csr_hwlp0s_get(), secured_riscv_debug_csr_hwlp1c_get(), secured_riscv_debug_csr_hwlp1e_get(), secured_riscv_debug_csr_hwlp1s_get(), secured_riscv_debug_csr_mcause_get(), secured_riscv_debug_csr_mepc_get(), secured_riscv_debug_csr_mhartid_get(), secured_riscv_debug_csr_mstatus_get(), secured_riscv_debug_csr_mtvec_get(), secured_riscv_debug_csr_pccr_get(), secured_riscv_debug_csr_pcer_get(), secured_riscv_debug_csr_pcmr_get(), secured_riscv_debug_csr_privlv_get(), secured_riscv_debug_csr_ucause_get(), secured_riscv_debug_csr_uepc_get(), secured_riscv_debug_csr_uhartid_get(), secured_riscv_debug_csr_ustatus_get(), secured_riscv_debug_csr_utvec_get(), secured_riscv_debug_ctrl_get(), secured_riscv_debug_gpr0_get(), secured_riscv_debug_gpr10_get(), secured_riscv_debug_gpr11_get(), secured_riscv_debug_gpr12_get(), secured_riscv_debug_gpr13_get(), secured_riscv_debug_gpr14_get(), secured_riscv_debug_gpr15_get(), secured_riscv_debug_gpr16_get(), secured_riscv_debug_gpr17_get(), secured_riscv_debug_gpr18_get(), secured_riscv_debug_gpr19_get(), secured_riscv_debug_gpr1_get(), secured_riscv_debug_gpr20_get(), secured_riscv_debug_gpr21_get(), secured_riscv_debug_gpr22_get(), secured_riscv_debug_gpr23_get(), secured_riscv_debug_gpr24_get(), secured_riscv_debug_gpr25_get(), secured_riscv_debug_gpr26_get(), secured_riscv_debug_gpr27_get(), secured_riscv_debug_gpr28_get(), secured_riscv_debug_gpr29_get(), secured_riscv_debug_gpr2_get(), secured_riscv_debug_gpr30_get(), secured_riscv_debug_gpr31_get(), secured_riscv_debug_gpr3_get(), secured_riscv_debug_gpr4_get(), secured_riscv_debug_gpr5_get(), secured_riscv_debug_gpr6_get(), secured_riscv_debug_gpr7_get(), secured_riscv_debug_gpr8_get(), secured_riscv_debug_gpr9_get(), secured_riscv_debug_hit_get(), secured_riscv_debug_ie_get(), secured_riscv_debug_npc_get(), secured_riscv_debug_ppc_get(), soc_ctrl_padcfg_get(), soc_ctrl_padfun_get(), soc_eu_cl_mask_lsb_get(), soc_eu_cl_mask_msb_get(), soc_eu_err_lsb_get(), soc_eu_err_msb_get(), soc_eu_fc_mask_lsb_get(), soc_eu_fc_mask_msb_get(), soc_eu_pr_mask_lsb_get(), soc_eu_pr_mask_msb_get(), soc_eu_sw_event_get(), soc_eu_timer1_sel_hi_get(), soc_eu_timer1_sel_lo_get(), soc_eu_timer2_sel_hi_get(), soc_eu_timer2_sel_lo_get(), timer_unit_cfg_hi_get(), timer_unit_cfg_lo_get(), timer_unit_cmp_hi_get(), timer_unit_cmp_lo_get(), timer_unit_cnt_hi_get(), timer_unit_cnt_lo_get(), timer_unit_reset_hi_get(), timer_unit_reset_lo_get(), timer_unit_start_hi_get(), timer_unit_start_lo_get(), udma_aes_cfg_get(), udma_aes_cfg_mode_get(), udma_aes_cfg_mode_gets(), udma_aes_cfg_mode_set(), udma_aes_dest_get(), udma_aes_dest_rx_dest_get(), udma_aes_dest_rx_dest_gets(), udma_aes_dest_rx_dest_set(), udma_aes_dest_tx_dest_get(), udma_aes_dest_tx_dest_gets(), udma_aes_dest_tx_dest_set(), udma_aes_iv0_0_get(), udma_aes_iv0_1_get(), udma_aes_iv0_2_get(), udma_aes_iv0_3_get(), udma_aes_key0_0_get(), udma_aes_key0_1_get(), udma_aes_key0_2_get(), udma_aes_key0_3_get(), udma_aes_key0_4_get(), udma_aes_key0_5_get(), udma_aes_key0_6_get(), udma_aes_key0_7_get(), udma_aes_setup_block_rst_get(), udma_aes_setup_block_rst_gets(), udma_aes_setup_block_rst_set(), udma_aes_setup_ecb_cbc_get(), udma_aes_setup_ecb_cbc_gets(), udma_aes_setup_ecb_cbc_set(), udma_aes_setup_enc_dec_get(), udma_aes_setup_enc_dec_gets(), udma_aes_setup_enc_dec_set(), udma_aes_setup_fifo_clr_get(), udma_aes_setup_fifo_clr_gets(), udma_aes_setup_fifo_clr_set(), udma_aes_setup_get(), udma_aes_setup_key_init_get(), udma_aes_setup_key_init_gets(), udma_aes_setup_key_init_set(), udma_aes_setup_key_type_get(), udma_aes_setup_key_type_gets(), udma_aes_setup_key_type_set(), udma_aes_setup_reserved_get(), udma_aes_setup_reserved_gets(), udma_aes_setup_reserved_set(), udma_asrc_ctrl_cfg_0_clk_en_get(), udma_asrc_ctrl_cfg_0_clk_en_gets(), udma_asrc_ctrl_cfg_0_clk_en_set(), udma_asrc_ctrl_cfg_0_fs_in_get(), udma_asrc_ctrl_cfg_0_fs_in_gets(), udma_asrc_ctrl_cfg_0_fs_in_set(), udma_asrc_ctrl_cfg_0_fs_out_get(), udma_asrc_ctrl_cfg_0_fs_out_gets(), udma_asrc_ctrl_cfg_0_fs_out_set(), udma_asrc_ctrl_cfg_0_get(), udma_asrc_ctrl_cfg_0_lock_wnd_get(), udma_asrc_ctrl_cfg_0_lock_wnd_gets(), udma_asrc_ctrl_cfg_0_lock_wnd_set(), udma_asrc_ctrl_cfg_0_rstn_get(), udma_asrc_ctrl_cfg_0_rstn_gets(), udma_asrc_ctrl_cfg_0_rstn_set(), udma_asrc_ctrl_cfg_1_clk_en_get(), udma_asrc_ctrl_cfg_1_clk_en_gets(), udma_asrc_ctrl_cfg_1_clk_en_set(), udma_asrc_ctrl_cfg_1_fs_in_get(), udma_asrc_ctrl_cfg_1_fs_in_gets(), udma_asrc_ctrl_cfg_1_fs_in_set(), udma_asrc_ctrl_cfg_1_fs_out_get(), udma_asrc_ctrl_cfg_1_fs_out_gets(), udma_asrc_ctrl_cfg_1_fs_out_set(), udma_asrc_ctrl_cfg_1_get(), udma_asrc_ctrl_cfg_1_lock_wnd_get(), udma_asrc_ctrl_cfg_1_lock_wnd_gets(), udma_asrc_ctrl_cfg_1_lock_wnd_set(), udma_asrc_ctrl_cfg_1_rstn_get(), udma_asrc_ctrl_cfg_1_rstn_gets(), udma_asrc_ctrl_cfg_1_rstn_set(), udma_asrc_ctrl_cfg_get(), udma_asrc_lane_cfg_0_ch_en_get(), udma_asrc_lane_cfg_0_ch_en_gets(), udma_asrc_lane_cfg_0_ch_en_set(), udma_asrc_lane_cfg_0_clk_en_get(), udma_asrc_lane_cfg_0_clk_en_gets(), udma_asrc_lane_cfg_0_clk_en_set(), udma_asrc_lane_cfg_0_ctrl_mux_get(), udma_asrc_lane_cfg_0_ctrl_mux_gets(), udma_asrc_lane_cfg_0_ctrl_mux_set(), udma_asrc_lane_cfg_0_drop_on_wait_get(), udma_asrc_lane_cfg_0_drop_on_wait_gets(), udma_asrc_lane_cfg_0_drop_on_wait_set(), udma_asrc_lane_cfg_0_get(), udma_asrc_lane_cfg_0_rstn_get(), udma_asrc_lane_cfg_0_rstn_gets(), udma_asrc_lane_cfg_0_rstn_set(), udma_asrc_lane_cfg_0_use_stream_in_get(), udma_asrc_lane_cfg_0_use_stream_in_gets(), udma_asrc_lane_cfg_0_use_stream_in_set(), udma_asrc_lane_cfg_0_use_stream_out_get(), udma_asrc_lane_cfg_0_use_stream_out_gets(), udma_asrc_lane_cfg_0_use_stream_out_set(), udma_asrc_lane_cfg_0_wait_lock_in_get(), udma_asrc_lane_cfg_0_wait_lock_in_gets(), udma_asrc_lane_cfg_0_wait_lock_in_set(), udma_asrc_lane_cfg_0_wait_lock_out_get(), udma_asrc_lane_cfg_0_wait_lock_out_gets(), udma_asrc_lane_cfg_0_wait_lock_out_set(), udma_asrc_lane_cfg_1_ch_en_get(), udma_asrc_lane_cfg_1_ch_en_gets(), udma_asrc_lane_cfg_1_ch_en_set(), udma_asrc_lane_cfg_1_clk_en_get(), udma_asrc_lane_cfg_1_clk_en_gets(), udma_asrc_lane_cfg_1_clk_en_set(), udma_asrc_lane_cfg_1_ctrl_mux_get(), udma_asrc_lane_cfg_1_ctrl_mux_gets(), udma_asrc_lane_cfg_1_ctrl_mux_set(), udma_asrc_lane_cfg_1_drop_on_wait_get(), udma_asrc_lane_cfg_1_drop_on_wait_gets(), udma_asrc_lane_cfg_1_drop_on_wait_set(), udma_asrc_lane_cfg_1_get(), udma_asrc_lane_cfg_1_rstn_get(), udma_asrc_lane_cfg_1_rstn_gets(), udma_asrc_lane_cfg_1_rstn_set(), udma_asrc_lane_cfg_1_use_stream_in_get(), udma_asrc_lane_cfg_1_use_stream_in_gets(), udma_asrc_lane_cfg_1_use_stream_in_set(), udma_asrc_lane_cfg_1_use_stream_out_get(), udma_asrc_lane_cfg_1_use_stream_out_gets(), udma_asrc_lane_cfg_1_use_stream_out_set(), udma_asrc_lane_cfg_1_wait_lock_in_get(), udma_asrc_lane_cfg_1_wait_lock_in_gets(), udma_asrc_lane_cfg_1_wait_lock_in_set(), udma_asrc_lane_cfg_1_wait_lock_out_get(), udma_asrc_lane_cfg_1_wait_lock_out_gets(), udma_asrc_lane_cfg_1_wait_lock_out_set(), udma_asrc_lane_cfg_2_ch_en_get(), udma_asrc_lane_cfg_2_ch_en_gets(), udma_asrc_lane_cfg_2_ch_en_set(), udma_asrc_lane_cfg_2_clk_en_get(), udma_asrc_lane_cfg_2_clk_en_gets(), udma_asrc_lane_cfg_2_clk_en_set(), udma_asrc_lane_cfg_2_ctrl_mux_get(), udma_asrc_lane_cfg_2_ctrl_mux_gets(), udma_asrc_lane_cfg_2_ctrl_mux_set(), udma_asrc_lane_cfg_2_drop_on_wait_get(), udma_asrc_lane_cfg_2_drop_on_wait_gets(), udma_asrc_lane_cfg_2_drop_on_wait_set(), udma_asrc_lane_cfg_2_get(), udma_asrc_lane_cfg_2_rstn_get(), udma_asrc_lane_cfg_2_rstn_gets(), udma_asrc_lane_cfg_2_rstn_set(), udma_asrc_lane_cfg_2_use_stream_in_get(), udma_asrc_lane_cfg_2_use_stream_in_gets(), udma_asrc_lane_cfg_2_use_stream_in_set(), udma_asrc_lane_cfg_2_use_stream_out_get(), udma_asrc_lane_cfg_2_use_stream_out_gets(), udma_asrc_lane_cfg_2_use_stream_out_set(), udma_asrc_lane_cfg_2_wait_lock_in_get(), udma_asrc_lane_cfg_2_wait_lock_in_gets(), udma_asrc_lane_cfg_2_wait_lock_in_set(), udma_asrc_lane_cfg_2_wait_lock_out_get(), udma_asrc_lane_cfg_2_wait_lock_out_gets(), udma_asrc_lane_cfg_2_wait_lock_out_set(), udma_asrc_lane_cfg_3_ch_en_get(), udma_asrc_lane_cfg_3_ch_en_gets(), udma_asrc_lane_cfg_3_ch_en_set(), udma_asrc_lane_cfg_3_clk_en_get(), udma_asrc_lane_cfg_3_clk_en_gets(), udma_asrc_lane_cfg_3_clk_en_set(), udma_asrc_lane_cfg_3_ctrl_mux_get(), udma_asrc_lane_cfg_3_ctrl_mux_gets(), udma_asrc_lane_cfg_3_ctrl_mux_set(), udma_asrc_lane_cfg_3_drop_on_wait_get(), udma_asrc_lane_cfg_3_drop_on_wait_gets(), udma_asrc_lane_cfg_3_drop_on_wait_set(), udma_asrc_lane_cfg_3_get(), udma_asrc_lane_cfg_3_rstn_get(), udma_asrc_lane_cfg_3_rstn_gets(), udma_asrc_lane_cfg_3_rstn_set(), udma_asrc_lane_cfg_3_use_stream_in_get(), udma_asrc_lane_cfg_3_use_stream_in_gets(), udma_asrc_lane_cfg_3_use_stream_in_set(), udma_asrc_lane_cfg_3_use_stream_out_get(), udma_asrc_lane_cfg_3_use_stream_out_gets(), udma_asrc_lane_cfg_3_use_stream_out_set(), udma_asrc_lane_cfg_3_wait_lock_in_get(), udma_asrc_lane_cfg_3_wait_lock_in_gets(), udma_asrc_lane_cfg_3_wait_lock_in_set(), udma_asrc_lane_cfg_3_wait_lock_out_get(), udma_asrc_lane_cfg_3_wait_lock_out_gets(), udma_asrc_lane_cfg_3_wait_lock_out_set(), udma_asrc_lane_cfg_get(), udma_asrc_lane_idin_0_get(), udma_asrc_lane_idin_0_id_ch0_get(), udma_asrc_lane_idin_0_id_ch0_gets(), udma_asrc_lane_idin_0_id_ch0_set(), udma_asrc_lane_idin_0_id_ch1_get(), udma_asrc_lane_idin_0_id_ch1_gets(), udma_asrc_lane_idin_0_id_ch1_set(), udma_asrc_lane_idin_0_id_ch2_get(), udma_asrc_lane_idin_0_id_ch2_gets(), udma_asrc_lane_idin_0_id_ch2_set(), udma_asrc_lane_idin_0_id_ch3_get(), udma_asrc_lane_idin_0_id_ch3_gets(), udma_asrc_lane_idin_0_id_ch3_set(), udma_asrc_lane_idin_1_get(), udma_asrc_lane_idin_1_id_ch0_get(), udma_asrc_lane_idin_1_id_ch0_gets(), udma_asrc_lane_idin_1_id_ch0_set(), udma_asrc_lane_idin_1_id_ch1_get(), udma_asrc_lane_idin_1_id_ch1_gets(), udma_asrc_lane_idin_1_id_ch1_set(), udma_asrc_lane_idin_1_id_ch2_get(), udma_asrc_lane_idin_1_id_ch2_gets(), udma_asrc_lane_idin_1_id_ch2_set(), udma_asrc_lane_idin_1_id_ch3_get(), udma_asrc_lane_idin_1_id_ch3_gets(), udma_asrc_lane_idin_1_id_ch3_set(), udma_asrc_lane_idin_2_get(), udma_asrc_lane_idin_2_id_ch0_get(), udma_asrc_lane_idin_2_id_ch0_gets(), udma_asrc_lane_idin_2_id_ch0_set(), udma_asrc_lane_idin_2_id_ch1_get(), udma_asrc_lane_idin_2_id_ch1_gets(), udma_asrc_lane_idin_2_id_ch1_set(), udma_asrc_lane_idin_2_id_ch2_get(), udma_asrc_lane_idin_2_id_ch2_gets(), udma_asrc_lane_idin_2_id_ch2_set(), udma_asrc_lane_idin_2_id_ch3_get(), udma_asrc_lane_idin_2_id_ch3_gets(), udma_asrc_lane_idin_2_id_ch3_set(), udma_asrc_lane_idin_3_get(), udma_asrc_lane_idin_3_id_ch0_get(), udma_asrc_lane_idin_3_id_ch0_gets(), udma_asrc_lane_idin_3_id_ch0_set(), udma_asrc_lane_idin_3_id_ch1_get(), udma_asrc_lane_idin_3_id_ch1_gets(), udma_asrc_lane_idin_3_id_ch1_set(), udma_asrc_lane_idin_3_id_ch2_get(), udma_asrc_lane_idin_3_id_ch2_gets(), udma_asrc_lane_idin_3_id_ch2_set(), udma_asrc_lane_idin_3_id_ch3_get(), udma_asrc_lane_idin_3_id_ch3_gets(), udma_asrc_lane_idin_3_id_ch3_set(), udma_asrc_lane_idout_0_get(), udma_asrc_lane_idout_0_id_ch0_get(), udma_asrc_lane_idout_0_id_ch0_gets(), udma_asrc_lane_idout_0_id_ch0_set(), udma_asrc_lane_idout_0_id_ch1_get(), udma_asrc_lane_idout_0_id_ch1_gets(), udma_asrc_lane_idout_0_id_ch1_set(), udma_asrc_lane_idout_0_id_ch2_get(), udma_asrc_lane_idout_0_id_ch2_gets(), udma_asrc_lane_idout_0_id_ch2_set(), udma_asrc_lane_idout_0_id_ch3_get(), udma_asrc_lane_idout_0_id_ch3_gets(), udma_asrc_lane_idout_0_id_ch3_set(), udma_asrc_lane_idout_1_get(), udma_asrc_lane_idout_1_id_ch0_get(), udma_asrc_lane_idout_1_id_ch0_gets(), udma_asrc_lane_idout_1_id_ch0_set(), udma_asrc_lane_idout_1_id_ch1_get(), udma_asrc_lane_idout_1_id_ch1_gets(), udma_asrc_lane_idout_1_id_ch1_set(), udma_asrc_lane_idout_1_id_ch2_get(), udma_asrc_lane_idout_1_id_ch2_gets(), udma_asrc_lane_idout_1_id_ch2_set(), udma_asrc_lane_idout_1_id_ch3_get(), udma_asrc_lane_idout_1_id_ch3_gets(), udma_asrc_lane_idout_1_id_ch3_set(), udma_asrc_lane_idout_2_get(), udma_asrc_lane_idout_2_id_ch0_get(), udma_asrc_lane_idout_2_id_ch0_gets(), udma_asrc_lane_idout_2_id_ch0_set(), udma_asrc_lane_idout_2_id_ch1_get(), udma_asrc_lane_idout_2_id_ch1_gets(), udma_asrc_lane_idout_2_id_ch1_set(), udma_asrc_lane_idout_2_id_ch2_get(), udma_asrc_lane_idout_2_id_ch2_gets(), udma_asrc_lane_idout_2_id_ch2_set(), udma_asrc_lane_idout_2_id_ch3_get(), udma_asrc_lane_idout_2_id_ch3_gets(), udma_asrc_lane_idout_2_id_ch3_set(), udma_asrc_lane_idout_3_get(), udma_asrc_lane_idout_3_id_ch0_get(), udma_asrc_lane_idout_3_id_ch0_gets(), udma_asrc_lane_idout_3_id_ch0_set(), udma_asrc_lane_idout_3_id_ch1_get(), udma_asrc_lane_idout_3_id_ch1_gets(), udma_asrc_lane_idout_3_id_ch1_set(), udma_asrc_lane_idout_3_id_ch2_get(), udma_asrc_lane_idout_3_id_ch2_gets(), udma_asrc_lane_idout_3_id_ch2_set(), udma_asrc_lane_idout_3_id_ch3_get(), udma_asrc_lane_idout_3_id_ch3_gets(), udma_asrc_lane_idout_3_id_ch3_set(), udma_asrc_mem2mem_cfg_ch_en_get(), udma_asrc_mem2mem_cfg_ch_en_gets(), udma_asrc_mem2mem_cfg_ch_en_set(), udma_asrc_mem2mem_cfg_clk_en_get(), udma_asrc_mem2mem_cfg_clk_en_gets(), udma_asrc_mem2mem_cfg_clk_en_set(), udma_asrc_mem2mem_cfg_ctx_id_get(), udma_asrc_mem2mem_cfg_ctx_id_gets(), udma_asrc_mem2mem_cfg_ctx_id_set(), udma_asrc_mem2mem_cfg_fs_in_get(), udma_asrc_mem2mem_cfg_fs_in_gets(), udma_asrc_mem2mem_cfg_fs_in_set(), udma_asrc_mem2mem_cfg_fs_out_get(), udma_asrc_mem2mem_cfg_fs_out_gets(), udma_asrc_mem2mem_cfg_fs_out_set(), udma_asrc_mem2mem_cfg_get(), udma_asrc_mem2mem_cfg_restore_get(), udma_asrc_mem2mem_cfg_restore_gets(), udma_asrc_mem2mem_cfg_restore_set(), udma_asrc_mem2mem_cfg_rstn_get(), udma_asrc_mem2mem_cfg_rstn_gets(), udma_asrc_mem2mem_cfg_rstn_set(), udma_asrc_mem2mem_cfg_store_get(), udma_asrc_mem2mem_cfg_store_gets(), udma_asrc_mem2mem_cfg_store_set(), udma_asrc_mem2mem_id_get(), udma_asrc_mem2mem_id_m2m_in_ch0_get(), udma_asrc_mem2mem_id_m2m_in_ch0_gets(), udma_asrc_mem2mem_id_m2m_in_ch0_set(), udma_asrc_mem2mem_id_m2m_in_ch1_get(), udma_asrc_mem2mem_id_m2m_in_ch1_gets(), udma_asrc_mem2mem_id_m2m_in_ch1_set(), udma_asrc_mem2mem_id_m2m_out_ch0_get(), udma_asrc_mem2mem_id_m2m_out_ch0_gets(), udma_asrc_mem2mem_id_m2m_out_ch0_set(), udma_asrc_mem2mem_id_m2m_out_ch1_get(), udma_asrc_mem2mem_id_m2m_out_ch1_gets(), udma_asrc_mem2mem_id_m2m_out_ch1_set(), udma_asrc_mem2mem_ratio_get(), udma_asrc_mem2mem_ratio_m2m_ratio_en_get(), udma_asrc_mem2mem_ratio_m2m_ratio_en_gets(), udma_asrc_mem2mem_ratio_m2m_ratio_en_set(), udma_asrc_mem2mem_ratio_m2m_ratio_get(), udma_asrc_mem2mem_ratio_m2m_ratio_gets(), udma_asrc_mem2mem_ratio_m2m_ratio_set(), udma_asrc_status_get(), udma_asrc_status_lock_get(), udma_asrc_status_lock_gets(), udma_asrc_status_lock_set(), udma_core_2d_addrgen_cfg_bytes_left_bytes_left_get(), udma_core_2d_addrgen_cfg_bytes_left_bytes_left_gets(), udma_core_2d_addrgen_cfg_bytes_left_get(), udma_core_2d_addrgen_cfg_ctrl_cont_get(), udma_core_2d_addrgen_cfg_ctrl_cont_gets(), udma_core_2d_addrgen_cfg_ctrl_cont_set(), udma_core_2d_addrgen_cfg_ctrl_en_get(), udma_core_2d_addrgen_cfg_ctrl_en_gets(), udma_core_2d_addrgen_cfg_ctrl_en_set(), udma_core_2d_addrgen_cfg_ctrl_get(), udma_core_2d_addrgen_cfg_ctrl_stop_get(), udma_core_2d_addrgen_cfg_ctrl_stop_gets(), udma_core_2d_addrgen_cfg_ctrl_stop_set(), udma_core_2d_addrgen_cfg_curr_addr_curr_addr_get(), udma_core_2d_addrgen_cfg_curr_addr_curr_addr_gets(), udma_core_2d_addrgen_cfg_curr_addr_get(), udma_core_2d_addrgen_cfg_row_len_get(), udma_core_2d_addrgen_cfg_row_len_row_len_get(), udma_core_2d_addrgen_cfg_row_len_row_len_gets(), udma_core_2d_addrgen_cfg_sa_buf0_get(), udma_core_2d_addrgen_cfg_sa_buf0_sa_addr0_get(), udma_core_2d_addrgen_cfg_sa_buf0_sa_addr0_gets(), udma_core_2d_addrgen_cfg_sa_buf1_get(), udma_core_2d_addrgen_cfg_sa_buf1_sa_addr1_get(), udma_core_2d_addrgen_cfg_sa_buf1_sa_addr1_gets(), udma_core_2d_addrgen_cfg_size_get(), udma_core_2d_addrgen_cfg_size_size_get(), udma_core_2d_addrgen_cfg_size_size_gets(), udma_core_2d_addrgen_cfg_stride_get(), udma_core_2d_addrgen_cfg_stride_stride_get(), udma_core_2d_addrgen_cfg_stride_stride_gets(), udma_core_fifo_cfg_ctrl_en_get(), udma_core_fifo_cfg_ctrl_en_gets(), udma_core_fifo_cfg_ctrl_en_set(), udma_core_fifo_cfg_ctrl_get(), udma_core_fifo_cfg_ctrl_stop_get(), udma_core_fifo_cfg_ctrl_stop_gets(), udma_core_fifo_cfg_ctrl_stop_set(), udma_core_fifo_cfg_ctrl_timeout_mon_get(), udma_core_fifo_cfg_ctrl_timeout_mon_gets(), udma_core_fifo_cfg_ctrl_timeout_mon_set(), udma_core_fifo_cfg_evt_en_get(), udma_core_fifo_cfg_evt_en_gets(), udma_core_fifo_cfg_evt_en_set(), udma_core_fifo_cfg_evt_get(), udma_core_fifo_cfg_evt_num_bytes_get(), udma_core_fifo_cfg_evt_num_bytes_gets(), udma_core_fifo_cfg_evt_num_bytes_set(), udma_core_fifo_cfg_fifo_fill_get(), udma_core_fifo_cfg_sa_buffer_get(), udma_core_fifo_cfg_size_get(), udma_core_lin_addrgen_cfg_bytes_left_get(), udma_core_lin_addrgen_cfg_ctrl_get(), udma_core_lin_addrgen_cfg_curr_addr_get(), udma_core_lin_addrgen_cfg_sa_buf0_get(), udma_core_lin_addrgen_cfg_sa_buf1_get(), udma_core_lin_addrgen_cfg_size_get(), udma_cpi_cam_cfg_glob_en_get(), udma_cpi_cam_cfg_glob_en_gets(), udma_cpi_cam_cfg_glob_en_set(), udma_cpi_cam_cfg_glob_format_get(), udma_cpi_cam_cfg_glob_format_gets(), udma_cpi_cam_cfg_glob_format_set(), udma_cpi_cam_cfg_glob_framedrop_en_get(), udma_cpi_cam_cfg_glob_framedrop_en_gets(), udma_cpi_cam_cfg_glob_framedrop_en_set(), udma_cpi_cam_cfg_glob_framedrop_val_get(), udma_cpi_cam_cfg_glob_framedrop_val_gets(), udma_cpi_cam_cfg_glob_framedrop_val_set(), udma_cpi_cam_cfg_glob_frameslice_en_get(), udma_cpi_cam_cfg_glob_frameslice_en_gets(), udma_cpi_cam_cfg_glob_frameslice_en_set(), udma_cpi_cam_cfg_glob_get(), udma_cpi_cam_cfg_ll_frameslice_llx_get(), udma_cpi_cam_cfg_ll_frameslice_llx_gets(), udma_cpi_cam_cfg_ll_frameslice_llx_set(), udma_cpi_cam_cfg_ll_frameslice_lly_get(), udma_cpi_cam_cfg_ll_frameslice_lly_gets(), udma_cpi_cam_cfg_ll_frameslice_lly_set(), udma_cpi_cam_cfg_ll_get(), udma_cpi_cam_cfg_rgb_get(), udma_cpi_cam_cfg_rgb_sequence_get(), udma_cpi_cam_cfg_rgb_sequence_gets(), udma_cpi_cam_cfg_rgb_sequence_set(), udma_cpi_cam_cfg_size_get(), udma_cpi_cam_cfg_size_rowlen_get(), udma_cpi_cam_cfg_size_rowlen_gets(), udma_cpi_cam_cfg_size_rowlen_set(), udma_cpi_cam_cfg_ur_frameslice_urx_get(), udma_cpi_cam_cfg_ur_frameslice_urx_gets(), udma_cpi_cam_cfg_ur_frameslice_urx_set(), udma_cpi_cam_cfg_ur_frameslice_ury_get(), udma_cpi_cam_cfg_ur_frameslice_ury_gets(), udma_cpi_cam_cfg_ur_frameslice_ury_set(), udma_cpi_cam_cfg_ur_get(), udma_cpi_cam_hsync_polarity_hsync_polarity_get(), udma_cpi_cam_hsync_polarity_hsync_polarity_gets(), udma_cpi_cam_hsync_polarity_hsync_polarity_set(), udma_cpi_cam_rx_datasize_get(), udma_cpi_cam_rx_datasize_rx_datasize_get(), udma_cpi_cam_rx_datasize_rx_datasize_gets(), udma_cpi_cam_rx_datasize_rx_datasize_set(), udma_cpi_cam_rx_dest_get(), udma_cpi_cam_rx_dest_rx_dest_get(), udma_cpi_cam_rx_dest_rx_dest_gets(), udma_cpi_cam_rx_dest_rx_dest_set(), udma_cpi_cam_sync_polarity_get(), udma_cpi_cam_vsync_polarity_vsync_polarity_get(), udma_cpi_cam_vsync_polarity_vsync_polarity_gets(), udma_cpi_cam_vsync_polarity_vsync_polarity_set(), udma_ctrl_cfg_cg_clr_get(), udma_ctrl_cfg_cg_get(), udma_ctrl_cfg_cg_set_get(), udma_ctrl_cfg_event_cmp_evt0_get(), udma_ctrl_cfg_event_cmp_evt0_gets(), udma_ctrl_cfg_event_cmp_evt0_set(), udma_ctrl_cfg_event_cmp_evt1_get(), udma_ctrl_cfg_event_cmp_evt1_gets(), udma_ctrl_cfg_event_cmp_evt1_set(), udma_ctrl_cfg_event_cmp_evt2_get(), udma_ctrl_cfg_event_cmp_evt2_gets(), udma_ctrl_cfg_event_cmp_evt2_set(), udma_ctrl_cfg_event_cmp_evt3_get(), udma_ctrl_cfg_event_cmp_evt3_gets(), udma_ctrl_cfg_event_cmp_evt3_set(), udma_ctrl_cfg_event_get(), udma_ctrl_cfg_rstn_clr_get(), udma_ctrl_cfg_rstn_get(), udma_ctrl_cfg_rstn_set_get(), udma_ctrl_datamove0_size_en_get(), udma_ctrl_datamove0_size_en_gets(), udma_ctrl_datamove0_size_en_set(), udma_ctrl_datamove0_size_get(), udma_ctrl_datamove0_size_size_get(), udma_ctrl_datamove0_size_size_gets(), udma_ctrl_datamove0_size_size_set(), udma_ctrl_datamove0_size_stop_get(), udma_ctrl_datamove0_size_stop_gets(), udma_ctrl_datamove0_size_stop_set(), udma_ctrl_datamove1_size_en_get(), udma_ctrl_datamove1_size_en_gets(), udma_ctrl_datamove1_size_en_set(), udma_ctrl_datamove1_size_get(), udma_ctrl_datamove1_size_size_get(), udma_ctrl_datamove1_size_size_gets(), udma_ctrl_datamove1_size_size_set(), udma_ctrl_datamove1_size_stop_get(), udma_ctrl_datamove1_size_stop_gets(), udma_ctrl_datamove1_size_stop_set(), udma_ctrl_datamove_cfg_dest_id_0_get(), udma_ctrl_datamove_cfg_dest_id_0_gets(), udma_ctrl_datamove_cfg_dest_id_0_set(), udma_ctrl_datamove_cfg_dest_id_1_get(), udma_ctrl_datamove_cfg_dest_id_1_gets(), udma_ctrl_datamove_cfg_dest_id_1_set(), udma_ctrl_datamove_cfg_get(), udma_ctrl_datamove_cfg_source_id_0_get(), udma_ctrl_datamove_cfg_source_id_0_gets(), udma_ctrl_datamove_cfg_source_id_0_set(), udma_ctrl_datamove_cfg_source_id_1_get(), udma_ctrl_datamove_cfg_source_id_1_gets(), udma_ctrl_datamove_cfg_source_id_1_set(), udma_ctrl_fifo_cfg_get(), udma_ctrl_fifo_cfg_pop_id_get(), udma_ctrl_fifo_cfg_pop_id_gets(), udma_ctrl_fifo_cfg_pop_id_set(), udma_ctrl_fifo_cfg_push_id_get(), udma_ctrl_fifo_cfg_push_id_gets(), udma_ctrl_fifo_cfg_push_id_set(), udma_ctrl_fifo_pushpop_16_get(), udma_ctrl_fifo_pushpop_24_get(), udma_ctrl_fifo_pushpop_32_get(), udma_ctrl_fifo_pushpop_8_get(), udma_ctrl_stream_cfg_get(), udma_ctrl_timeout_ch0_cnt_get(), udma_ctrl_timeout_ch0_cnt_gets(), udma_ctrl_timeout_ch0_cnt_set(), udma_ctrl_timeout_ch0_en_get(), udma_ctrl_timeout_ch0_en_gets(), udma_ctrl_timeout_ch0_en_set(), udma_ctrl_timeout_ch0_get(), udma_ctrl_timeout_ch0_mode_get(), udma_ctrl_timeout_ch0_mode_gets(), udma_ctrl_timeout_ch0_mode_set(), udma_ctrl_timeout_ch0_source_id_get(), udma_ctrl_timeout_ch0_source_id_gets(), udma_ctrl_timeout_ch0_source_id_set(), udma_ctrl_timeout_ch1_cnt_get(), udma_ctrl_timeout_ch1_cnt_gets(), udma_ctrl_timeout_ch1_cnt_set(), udma_ctrl_timeout_ch1_en_get(), udma_ctrl_timeout_ch1_en_gets(), udma_ctrl_timeout_ch1_en_set(), udma_ctrl_timeout_ch1_get(), udma_ctrl_timeout_ch1_mode_get(), udma_ctrl_timeout_ch1_mode_gets(), udma_ctrl_timeout_ch1_mode_set(), udma_ctrl_timeout_ch1_source_id_get(), udma_ctrl_timeout_ch1_source_id_gets(), udma_ctrl_timeout_ch1_source_id_set(), udma_ctrl_timeout_ch2_cnt_get(), udma_ctrl_timeout_ch2_cnt_gets(), udma_ctrl_timeout_ch2_cnt_set(), udma_ctrl_timeout_ch2_en_get(), udma_ctrl_timeout_ch2_en_gets(), udma_ctrl_timeout_ch2_en_set(), udma_ctrl_timeout_ch2_get(), udma_ctrl_timeout_ch2_mode_get(), udma_ctrl_timeout_ch2_mode_gets(), udma_ctrl_timeout_ch2_mode_set(), udma_ctrl_timeout_ch2_source_id_get(), udma_ctrl_timeout_ch2_source_id_gets(), udma_ctrl_timeout_ch2_source_id_set(), udma_ctrl_timeout_ch3_cnt_get(), udma_ctrl_timeout_ch3_cnt_gets(), udma_ctrl_timeout_ch3_cnt_set(), udma_ctrl_timeout_ch3_en_get(), udma_ctrl_timeout_ch3_en_gets(), udma_ctrl_timeout_ch3_en_set(), udma_ctrl_timeout_ch3_get(), udma_ctrl_timeout_ch3_mode_get(), udma_ctrl_timeout_ch3_mode_gets(), udma_ctrl_timeout_ch3_mode_set(), udma_ctrl_timeout_ch3_source_id_get(), udma_ctrl_timeout_ch3_source_id_gets(), udma_ctrl_timeout_ch3_source_id_set(), udma_ctrl_timeout_ch4_cnt_get(), udma_ctrl_timeout_ch4_cnt_gets(), udma_ctrl_timeout_ch4_cnt_set(), udma_ctrl_timeout_ch4_en_get(), udma_ctrl_timeout_ch4_en_gets(), udma_ctrl_timeout_ch4_en_set(), udma_ctrl_timeout_ch4_get(), udma_ctrl_timeout_ch4_mode_get(), udma_ctrl_timeout_ch4_mode_gets(), udma_ctrl_timeout_ch4_mode_set(), udma_ctrl_timeout_ch4_source_id_get(), udma_ctrl_timeout_ch4_source_id_gets(), udma_ctrl_timeout_ch4_source_id_set(), udma_ctrl_timeout_ch5_cnt_get(), udma_ctrl_timeout_ch5_cnt_gets(), udma_ctrl_timeout_ch5_cnt_set(), udma_ctrl_timeout_ch5_en_get(), udma_ctrl_timeout_ch5_en_gets(), udma_ctrl_timeout_ch5_en_set(), udma_ctrl_timeout_ch5_get(), udma_ctrl_timeout_ch5_mode_get(), udma_ctrl_timeout_ch5_mode_gets(), udma_ctrl_timeout_ch5_mode_set(), udma_ctrl_timeout_ch5_source_id_get(), udma_ctrl_timeout_ch5_source_id_gets(), udma_ctrl_timeout_ch5_source_id_set(), udma_ctrl_timeout_ch6_cnt_get(), udma_ctrl_timeout_ch6_cnt_gets(), udma_ctrl_timeout_ch6_cnt_set(), udma_ctrl_timeout_ch6_en_get(), udma_ctrl_timeout_ch6_en_gets(), udma_ctrl_timeout_ch6_en_set(), udma_ctrl_timeout_ch6_get(), udma_ctrl_timeout_ch6_mode_get(), udma_ctrl_timeout_ch6_mode_gets(), udma_ctrl_timeout_ch6_mode_set(), udma_ctrl_timeout_ch6_source_id_get(), udma_ctrl_timeout_ch6_source_id_gets(), udma_ctrl_timeout_ch6_source_id_set(), udma_ctrl_timeout_ch7_cnt_get(), udma_ctrl_timeout_ch7_cnt_gets(), udma_ctrl_timeout_ch7_cnt_set(), udma_ctrl_timeout_ch7_en_get(), udma_ctrl_timeout_ch7_en_gets(), udma_ctrl_timeout_ch7_en_set(), udma_ctrl_timeout_ch7_get(), udma_ctrl_timeout_ch7_mode_get(), udma_ctrl_timeout_ch7_mode_gets(), udma_ctrl_timeout_ch7_mode_set(), udma_ctrl_timeout_ch7_source_id_get(), udma_ctrl_timeout_ch7_source_id_gets(), udma_ctrl_timeout_ch7_source_id_set(), udma_ctrl_timeout_pre0_clr_get(), udma_ctrl_timeout_pre0_clr_gets(), udma_ctrl_timeout_pre0_clr_set(), udma_ctrl_timeout_pre0_cnt_get(), udma_ctrl_timeout_pre0_cnt_gets(), udma_ctrl_timeout_pre0_cnt_set(), udma_ctrl_timeout_pre0_en_get(), udma_ctrl_timeout_pre0_en_gets(), udma_ctrl_timeout_pre0_en_set(), udma_ctrl_timeout_pre0_get(), udma_ctrl_timeout_pre1_clr_get(), udma_ctrl_timeout_pre1_clr_gets(), udma_ctrl_timeout_pre1_clr_set(), udma_ctrl_timeout_pre1_cnt_get(), udma_ctrl_timeout_pre1_cnt_gets(), udma_ctrl_timeout_pre1_cnt_set(), udma_ctrl_timeout_pre1_en_get(), udma_ctrl_timeout_pre1_en_gets(), udma_ctrl_timeout_pre1_en_set(), udma_ctrl_timeout_pre1_get(), udma_ctrl_timeout_pre2_clr_get(), udma_ctrl_timeout_pre2_clr_gets(), udma_ctrl_timeout_pre2_clr_set(), udma_ctrl_timeout_pre2_cnt_get(), udma_ctrl_timeout_pre2_cnt_gets(), udma_ctrl_timeout_pre2_cnt_set(), udma_ctrl_timeout_pre2_en_get(), udma_ctrl_timeout_pre2_en_gets(), udma_ctrl_timeout_pre2_en_set(), udma_ctrl_timeout_pre2_get(), udma_ctrl_timeout_pre3_clr_get(), udma_ctrl_timeout_pre3_clr_gets(), udma_ctrl_timeout_pre3_clr_set(), udma_ctrl_timeout_pre3_cnt_get(), udma_ctrl_timeout_pre3_cnt_gets(), udma_ctrl_timeout_pre3_cnt_set(), udma_ctrl_timeout_pre3_en_get(), udma_ctrl_timeout_pre3_en_gets(), udma_ctrl_timeout_pre3_en_set(), udma_ctrl_timeout_pre3_get(), udma_ctrl_timeout_pre4_clr_get(), udma_ctrl_timeout_pre4_clr_gets(), udma_ctrl_timeout_pre4_clr_set(), udma_ctrl_timeout_pre4_cnt_get(), udma_ctrl_timeout_pre4_cnt_gets(), udma_ctrl_timeout_pre4_cnt_set(), udma_ctrl_timeout_pre4_en_get(), udma_ctrl_timeout_pre4_en_gets(), udma_ctrl_timeout_pre4_en_set(), udma_ctrl_timeout_pre4_get(), udma_ctrl_timeout_pre5_clr_get(), udma_ctrl_timeout_pre5_clr_gets(), udma_ctrl_timeout_pre5_clr_set(), udma_ctrl_timeout_pre5_cnt_get(), udma_ctrl_timeout_pre5_cnt_gets(), udma_ctrl_timeout_pre5_cnt_set(), udma_ctrl_timeout_pre5_en_get(), udma_ctrl_timeout_pre5_en_gets(), udma_ctrl_timeout_pre5_en_set(), udma_ctrl_timeout_pre5_get(), udma_ctrl_timeout_pre6_clr_get(), udma_ctrl_timeout_pre6_clr_gets(), udma_ctrl_timeout_pre6_clr_set(), udma_ctrl_timeout_pre6_cnt_get(), udma_ctrl_timeout_pre6_cnt_gets(), udma_ctrl_timeout_pre6_cnt_set(), udma_ctrl_timeout_pre6_en_get(), udma_ctrl_timeout_pre6_en_gets(), udma_ctrl_timeout_pre6_en_set(), udma_ctrl_timeout_pre6_get(), udma_ctrl_timeout_pre7_clr_get(), udma_ctrl_timeout_pre7_clr_gets(), udma_ctrl_timeout_pre7_clr_set(), udma_ctrl_timeout_pre7_cnt_get(), udma_ctrl_timeout_pre7_cnt_gets(), udma_ctrl_timeout_pre7_cnt_set(), udma_ctrl_timeout_pre7_en_get(), udma_ctrl_timeout_pre7_en_gets(), udma_ctrl_timeout_pre7_en_set(), udma_ctrl_timeout_pre7_get(), udma_ffc_conv_num_get(), udma_ffc_conv_rx_addr_get(), udma_ffc_conv_tx_addr_get(), udma_ffc_fl_format_get(), udma_ffc_fp_format_get(), udma_ffc_fp_prec_get(), udma_ffc_fp_scale_get(), udma_ffc_irq_en_get(), udma_ffc_mode_get(), udma_ffc_rx_dest_get(), udma_ffc_start_get(), udma_ffc_status_get(), udma_ffc_trans_mode_get(), udma_ffc_tx_dest_get(), udma_filter_reg_au_cfg_get(), udma_filter_reg_au_reg0_get(), udma_filter_reg_au_reg1_get(), udma_filter_reg_bincu_cnt_get(), udma_filter_reg_bincu_setup_get(), udma_filter_reg_bincu_th_get(), udma_filter_reg_bincu_val_get(), udma_filter_reg_filt_cmd_get(), udma_filter_reg_filt_get(), udma_filter_reg_rx_ch_add_get(), udma_filter_reg_rx_ch_cfg_get(), udma_filter_reg_rx_ch_len0_get(), udma_filter_reg_rx_ch_len1_get(), udma_filter_reg_rx_ch_len2_get(), udma_filter_reg_status_get(), udma_filter_reg_tx_ch0_add_get(), udma_filter_reg_tx_ch0_cfg_get(), udma_filter_reg_tx_ch0_len0_get(), udma_filter_reg_tx_ch0_len1_get(), udma_filter_reg_tx_ch0_len2_get(), udma_filter_reg_tx_ch1_add_get(), udma_filter_reg_tx_ch1_cfg_get(), udma_filter_reg_tx_ch1_len0_get(), udma_filter_reg_tx_ch1_len1_get(), udma_filter_reg_tx_ch1_len2_get(), udma_hyper_burst_enable_2d_enable_get(), udma_hyper_burst_enable_2d_enable_gets(), udma_hyper_burst_enable_2d_enable_set(), udma_hyper_burst_enable_2d_mode_get(), udma_hyper_burst_enable_2d_mode_gets(), udma_hyper_burst_enable_2d_mode_set(), udma_hyper_burst_enable_cs0_auto_burst_enable_get(), udma_hyper_burst_enable_cs0_auto_burst_enable_gets(), udma_hyper_burst_enable_cs0_auto_burst_enable_set(), udma_hyper_burst_enable_cs0_maximum_check_enable_get(), udma_hyper_burst_enable_cs0_maximum_check_enable_gets(), udma_hyper_burst_enable_cs0_maximum_check_enable_set(), udma_hyper_burst_enable_cs1_auto_burst_enable_get(), udma_hyper_burst_enable_cs1_auto_burst_enable_gets(), udma_hyper_burst_enable_cs1_auto_burst_enable_set(), udma_hyper_burst_enable_cs1_maximum_check_enable_get(), udma_hyper_burst_enable_cs1_maximum_check_enable_gets(), udma_hyper_burst_enable_cs1_maximum_check_enable_set(), udma_hyper_burst_enable_get(), udma_hyper_clk_div_data_get(), udma_hyper_clk_div_data_gets(), udma_hyper_clk_div_data_set(), udma_hyper_clk_div_get(), udma_hyper_clk_div_valid_get(), udma_hyper_clk_div_valid_gets(), udma_hyper_clk_div_valid_set(), udma_hyper_device_dt0_get(), udma_hyper_device_dt0_gets(), udma_hyper_device_dt0_set(), udma_hyper_device_dt1_get(), udma_hyper_device_dt1_gets(), udma_hyper_device_dt1_set(), udma_hyper_device_get(), udma_hyper_device_sdio_get(), udma_hyper_device_sdio_gets(), udma_hyper_device_sdio_set(), udma_hyper_device_type_get(), udma_hyper_device_type_gets(), udma_hyper_device_type_set(), udma_hyper_ext_addr_get(), udma_hyper_ext_addr_reg_access_get(), udma_hyper_ext_addr_reg_access_gets(), udma_hyper_ext_addr_reg_access_set(), udma_hyper_ext_addr_saddr_get(), udma_hyper_ext_addr_saddr_gets(), udma_hyper_ext_addr_saddr_set(), udma_hyper_irq_en_en_get(), udma_hyper_irq_en_en_gets(), udma_hyper_irq_en_en_set(), udma_hyper_irq_en_get(), udma_hyper_irq_en_xip_en_get(), udma_hyper_irq_en_xip_en_gets(), udma_hyper_irq_en_xip_en_set(), udma_hyper_line_2d_get(), udma_hyper_line_2d_line_get(), udma_hyper_line_2d_line_gets(), udma_hyper_mba0_get(), udma_hyper_mba0_mba0_get(), udma_hyper_mba0_mba0_gets(), udma_hyper_mba0_mba0_set(), udma_hyper_mba0_reserved_get(), udma_hyper_mba0_reserved_gets(), udma_hyper_mba0_reserved_set(), udma_hyper_mba1_get(), udma_hyper_mba1_mba1_get(), udma_hyper_mba1_mba1_gets(), udma_hyper_mba1_mba1_set(), udma_hyper_mba1_reserved_get(), udma_hyper_mba1_reserved_gets(), udma_hyper_mba1_reserved_set(), udma_hyper_ospi_alter_get(), udma_hyper_ospi_alter_mode0_get(), udma_hyper_ospi_alter_mode0_gets(), udma_hyper_ospi_alter_mode0_set(), udma_hyper_ospi_alter_mode1_get(), udma_hyper_ospi_alter_mode1_gets(), udma_hyper_ospi_alter_mode1_set(), udma_hyper_ospi_alter_xip_get(), udma_hyper_ospi_alter_xip_mode0_get(), udma_hyper_ospi_alter_xip_mode0_gets(), udma_hyper_ospi_alter_xip_mode0_set(), udma_hyper_ospi_alter_xip_mode1_get(), udma_hyper_ospi_alter_xip_mode1_gets(), udma_hyper_ospi_alter_xip_mode1_set(), udma_hyper_ospi_cfg_addr_dtr_str_get(), udma_hyper_ospi_cfg_addr_dtr_str_gets(), udma_hyper_ospi_cfg_addr_dtr_str_set(), udma_hyper_ospi_cfg_addr_size_get(), udma_hyper_ospi_cfg_addr_size_gets(), udma_hyper_ospi_cfg_addr_size_set(), udma_hyper_ospi_cfg_cmd_dtr_str_get(), udma_hyper_ospi_cfg_cmd_dtr_str_gets(), udma_hyper_ospi_cfg_cmd_dtr_str_set(), udma_hyper_ospi_cfg_cmd_size_get(), udma_hyper_ospi_cfg_cmd_size_gets(), udma_hyper_ospi_cfg_cmd_size_set(), udma_hyper_ospi_cfg_data_dtr_msb_get(), udma_hyper_ospi_cfg_data_dtr_msb_gets(), udma_hyper_ospi_cfg_data_dtr_msb_set(), udma_hyper_ospi_cfg_data_dtr_str_get(), udma_hyper_ospi_cfg_data_dtr_str_gets(), udma_hyper_ospi_cfg_data_dtr_str_set(), udma_hyper_ospi_cfg_get(), udma_hyper_ospi_cfg_line_get(), udma_hyper_ospi_cfg_line_gets(), udma_hyper_ospi_cfg_line_set(), udma_hyper_ospi_cfg_xip_addr_dtr_str_get(), udma_hyper_ospi_cfg_xip_addr_dtr_str_gets(), udma_hyper_ospi_cfg_xip_addr_dtr_str_set(), udma_hyper_ospi_cfg_xip_addr_size_get(), udma_hyper_ospi_cfg_xip_addr_size_gets(), udma_hyper_ospi_cfg_xip_addr_size_set(), udma_hyper_ospi_cfg_xip_cmd_dtr_str_get(), udma_hyper_ospi_cfg_xip_cmd_dtr_str_gets(), udma_hyper_ospi_cfg_xip_cmd_dtr_str_set(), udma_hyper_ospi_cfg_xip_cmd_size_get(), udma_hyper_ospi_cfg_xip_cmd_size_gets(), udma_hyper_ospi_cfg_xip_cmd_size_set(), udma_hyper_ospi_cfg_xip_data_dtr_msb_get(), udma_hyper_ospi_cfg_xip_data_dtr_msb_gets(), udma_hyper_ospi_cfg_xip_data_dtr_msb_set(), udma_hyper_ospi_cfg_xip_data_dtr_str_get(), udma_hyper_ospi_cfg_xip_data_dtr_str_gets(), udma_hyper_ospi_cfg_xip_data_dtr_str_set(), udma_hyper_ospi_cfg_xip_get(), udma_hyper_ospi_cfg_xip_line_get(), udma_hyper_ospi_cfg_xip_line_gets(), udma_hyper_ospi_cfg_xip_line_set(), udma_hyper_ospi_cmd_cmd_get(), udma_hyper_ospi_cmd_cmd_gets(), udma_hyper_ospi_cmd_cmd_set(), udma_hyper_ospi_cmd_get(), udma_hyper_ospi_cmd_sdio_cmd_op_get(), udma_hyper_ospi_cmd_sdio_cmd_op_gets(), udma_hyper_ospi_cmd_sdio_cmd_op_set(), udma_hyper_ospi_cmd_sdio_cmd_rsp_type_get(), udma_hyper_ospi_cmd_sdio_cmd_rsp_type_gets(), udma_hyper_ospi_cmd_sdio_cmd_rsp_type_set(), udma_hyper_ospi_cmd_xip_cmd_get(), udma_hyper_ospi_cmd_xip_cmd_gets(), udma_hyper_ospi_cmd_xip_cmd_set(), udma_hyper_ospi_cmd_xip_get(), udma_hyper_ospi_cmd_xip_sdio_cmd_op_get(), udma_hyper_ospi_cmd_xip_sdio_cmd_op_gets(), udma_hyper_ospi_cmd_xip_sdio_cmd_op_set(), udma_hyper_ospi_cmd_xip_sdio_cmd_rsp_type_get(), udma_hyper_ospi_cmd_xip_sdio_cmd_rsp_type_gets(), udma_hyper_ospi_cmd_xip_sdio_cmd_rsp_type_set(), udma_hyper_ospi_csn_auto_en_get(), udma_hyper_ospi_csn_auto_en_gets(), udma_hyper_ospi_csn_auto_en_set(), udma_hyper_ospi_csn_direct_ctrl_get(), udma_hyper_ospi_csn_direct_ctrl_gets(), udma_hyper_ospi_csn_direct_ctrl_set(), udma_hyper_ospi_csn_get(), udma_hyper_ospi_csn_index_get(), udma_hyper_ospi_csn_index_gets(), udma_hyper_ospi_csn_index_set(), udma_hyper_ospi_csn_reserved_get(), udma_hyper_ospi_csn_reserved_gets(), udma_hyper_ospi_csn_reserved_set(), udma_hyper_ospi_csn_sdio_auto_stop_get(), udma_hyper_ospi_csn_sdio_auto_stop_gets(), udma_hyper_ospi_csn_sdio_auto_stop_set(), udma_hyper_ospi_csn_sdio_block_num_get(), udma_hyper_ospi_csn_sdio_block_num_gets(), udma_hyper_ospi_csn_sdio_block_num_set(), udma_hyper_ospi_csn_sdio_block_size_get(), udma_hyper_ospi_csn_sdio_block_size_gets(), udma_hyper_ospi_csn_sdio_block_size_set(), udma_hyper_ospi_csn_sdio_data_quad_ddr_get(), udma_hyper_ospi_csn_sdio_data_quad_ddr_gets(), udma_hyper_ospi_csn_sdio_data_quad_ddr_set(), udma_hyper_ospi_csn_sdio_data_quad_get(), udma_hyper_ospi_csn_sdio_data_quad_gets(), udma_hyper_ospi_csn_sdio_data_quad_set(), udma_hyper_ospi_csn_value_get(), udma_hyper_ospi_csn_value_gets(), udma_hyper_ospi_csn_value_set(), udma_hyper_ospi_jedec_reset_get(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_en_get(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_en_gets(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_en_set(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_value_get(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_value_gets(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_value_set(), udma_hyper_ospi_ram_opt_get(), udma_hyper_ospi_ram_opt_opt_read_en_cs_get(), udma_hyper_ospi_ram_opt_opt_read_en_cs_gets(), udma_hyper_ospi_ram_opt_opt_read_en_cs_set(), udma_hyper_ospi_ram_opt_psram_addr_even_get(), udma_hyper_ospi_ram_opt_psram_addr_even_gets(), udma_hyper_ospi_ram_opt_psram_addr_even_set(), udma_hyper_ospi_ram_opt_psram_cmd_en_get(), udma_hyper_ospi_ram_opt_psram_cmd_en_gets(), udma_hyper_ospi_ram_opt_psram_cmd_en_set(), udma_hyper_ospi_ram_opt_psram_cross_boundary_en_get(), udma_hyper_ospi_ram_opt_psram_cross_boundary_en_gets(), udma_hyper_ospi_ram_opt_psram_cross_boundary_en_set(), udma_hyper_ospi_ram_opt_psram_read_bit_get(), udma_hyper_ospi_ram_opt_psram_read_bit_gets(), udma_hyper_ospi_ram_opt_psram_read_bit_set(), udma_hyper_ospi_ram_opt_real_addr_en_get(), udma_hyper_ospi_ram_opt_real_addr_en_gets(), udma_hyper_ospi_ram_opt_real_addr_en_set(), udma_hyper_ospi_reg_xip_get(), udma_hyper_ospi_reg_xip_xip_latency0_get(), udma_hyper_ospi_reg_xip_xip_latency0_gets(), udma_hyper_ospi_reg_xip_xip_latency0_set(), udma_hyper_ospi_reg_xip_xip_latency1_get(), udma_hyper_ospi_reg_xip_xip_latency1_gets(), udma_hyper_ospi_reg_xip_xip_latency1_set(), udma_hyper_rx_dest_dest_get(), udma_hyper_rx_dest_dest_gets(), udma_hyper_rx_dest_dest_set(), udma_hyper_rx_dest_dest_stream_get(), udma_hyper_rx_dest_dest_stream_gets(), udma_hyper_rx_dest_dest_stream_set(), udma_hyper_rx_dest_get(), udma_hyper_sdio_cmd_arg_arg_get(), udma_hyper_sdio_cmd_arg_arg_gets(), udma_hyper_sdio_cmd_arg_get(), udma_hyper_sdio_rsp0_get(), udma_hyper_sdio_rsp0_rsp0_get(), udma_hyper_sdio_rsp0_rsp0_gets(), udma_hyper_sdio_rsp1_get(), udma_hyper_sdio_rsp1_rsp1_get(), udma_hyper_sdio_rsp1_rsp1_gets(), udma_hyper_sdio_rsp2_get(), udma_hyper_sdio_rsp2_rsp2_get(), udma_hyper_sdio_rsp2_rsp2_gets(), udma_hyper_sdio_rsp3_get(), udma_hyper_sdio_rsp3_rsp3_get(), udma_hyper_sdio_rsp3_rsp3_gets(), udma_hyper_status_get(), udma_hyper_status_reserved_get(), udma_hyper_status_reserved_gets(), udma_hyper_status_reserved_set(), udma_hyper_status_rx_error_get(), udma_hyper_status_rx_error_gets(), udma_hyper_status_rx_error_set(), udma_hyper_status_rx_tx_end_get(), udma_hyper_status_rx_tx_end_gets(), udma_hyper_status_rx_tx_end_set(), udma_hyper_status_sdio_error_status_get(), udma_hyper_status_sdio_error_status_gets(), udma_hyper_status_sdio_error_status_set(), udma_hyper_status_sdio_rx_tx_end_get(), udma_hyper_status_sdio_rx_tx_end_gets(), udma_hyper_status_sdio_rx_tx_end_set(), udma_hyper_status_sdio_rx_tx_error_get(), udma_hyper_status_sdio_rx_tx_error_gets(), udma_hyper_status_sdio_rx_tx_error_set(), udma_hyper_status_tx_error_get(), udma_hyper_status_tx_error_gets(), udma_hyper_status_tx_error_set(), udma_hyper_stride_2d_get(), udma_hyper_stride_2d_stride_get(), udma_hyper_stride_2d_stride_gets(), udma_hyper_timing_cfg_additional_latency_autocheck_en_get(), udma_hyper_timing_cfg_additional_latency_autocheck_en_gets(), udma_hyper_timing_cfg_additional_latency_autocheck_en_set(), udma_hyper_timing_cfg_cs_max_get(), udma_hyper_timing_cfg_cs_max_gets(), udma_hyper_timing_cfg_cs_max_set(), udma_hyper_timing_cfg_get(), udma_hyper_timing_cfg_latency0_get(), udma_hyper_timing_cfg_latency0_gets(), udma_hyper_timing_cfg_latency0_set(), udma_hyper_timing_cfg_latency1_get(), udma_hyper_timing_cfg_latency1_gets(), udma_hyper_timing_cfg_latency1_set(), udma_hyper_timing_cfg_rw_recovery_get(), udma_hyper_timing_cfg_rw_recovery_gets(), udma_hyper_timing_cfg_rw_recovery_set(), udma_hyper_timing_cfg_rwds_delay_get(), udma_hyper_timing_cfg_rwds_delay_gets(), udma_hyper_timing_cfg_rwds_delay_set(), udma_hyper_trans_addr_addr_get(), udma_hyper_trans_addr_addr_gets(), udma_hyper_trans_addr_get(), udma_hyper_trans_cfg_get(), udma_hyper_trans_cfg_rxtx_get(), udma_hyper_trans_cfg_rxtx_gets(), udma_hyper_trans_cfg_rxtx_set(), udma_hyper_trans_cfg_valid_get(), udma_hyper_trans_cfg_valid_gets(), udma_hyper_trans_cfg_valid_set(), udma_hyper_trans_mode_auto_ena_get(), udma_hyper_trans_mode_auto_ena_gets(), udma_hyper_trans_mode_auto_ena_set(), udma_hyper_trans_mode_get(), udma_hyper_trans_mode_stream_en_get(), udma_hyper_trans_mode_stream_en_gets(), udma_hyper_trans_mode_stream_en_set(), udma_hyper_trans_mode_stream_xip_en_get(), udma_hyper_trans_mode_stream_xip_en_gets(), udma_hyper_trans_mode_stream_xip_en_set(), udma_hyper_trans_mode_xip_en_get(), udma_hyper_trans_mode_xip_en_gets(), udma_hyper_trans_mode_xip_en_set(), udma_hyper_trans_mode_xip_halted_get(), udma_hyper_trans_mode_xip_halted_gets(), udma_hyper_trans_mode_xip_halted_set(), udma_hyper_trans_size_get(), udma_hyper_trans_size_size_get(), udma_hyper_trans_size_size_gets(), udma_hyper_tx_dest_dest_get(), udma_hyper_tx_dest_dest_gets(), udma_hyper_tx_dest_dest_set(), udma_hyper_tx_dest_dest_stream_get(), udma_hyper_tx_dest_dest_stream_gets(), udma_hyper_tx_dest_dest_stream_set(), udma_hyper_tx_dest_get(), udma_i2c_foll_udma_rx_dest_reg_idx_get(), udma_i2c_foll_udma_tx_dest_reg_idx_get(), udma_i2c_lead_udma_rx_dest_reg_idx_get(), udma_i2c_lead_udma_tx_dest_reg_idx_get(), udma_i2c_status_reg_idx_get(), udma_i2c_status_reg_idx_status_foll_eof_rcv_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_eof_rcv_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_eof_rcv_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_eof_snd_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_eof_snd_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_eof_snd_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_error_arlo_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_error_arlo_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_error_arlo_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_error_framing_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_error_framing_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_error_framing_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_purge_event_o_idx_get(), udma_i2c_status_reg_idx_status_foll_purge_event_o_idx_gets(), udma_i2c_status_reg_idx_status_foll_purge_event_o_idx_set(), udma_i2c_status_reg_idx_status_foll_sof_rcv_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_sof_rcv_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_sof_rcv_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_sof_snd_event_i_idx_get(), udma_i2c_status_reg_idx_status_foll_sof_snd_event_i_idx_gets(), udma_i2c_status_reg_idx_status_foll_sof_snd_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_unlock_event_o_idx_get(), udma_i2c_status_reg_idx_status_foll_unlock_event_o_idx_gets(), udma_i2c_status_reg_idx_status_foll_unlock_event_o_idx_set(), udma_i2c_status_reg_idx_status_i2c_prescaler_set_div10_event_o_idx_get(), udma_i2c_status_reg_idx_status_i2c_prescaler_set_div10_event_o_idx_gets(), udma_i2c_status_reg_idx_status_i2c_prescaler_set_div10_event_o_idx_set(), udma_i2c_status_reg_idx_status_i2c_soft_reset_event_o_idx_get(), udma_i2c_status_reg_idx_status_i2c_soft_reset_event_o_idx_gets(), udma_i2c_status_reg_idx_status_i2c_soft_reset_event_o_idx_set(), udma_i2c_status_reg_idx_status_lead_command_event_i_idx_get(), udma_i2c_status_reg_idx_status_lead_command_event_i_idx_gets(), udma_i2c_status_reg_idx_status_lead_command_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_error_arlo_event_i_idx_get(), udma_i2c_status_reg_idx_status_lead_error_arlo_event_i_idx_gets(), udma_i2c_status_reg_idx_status_lead_error_arlo_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_error_framing_event_i_idx_get(), udma_i2c_status_reg_idx_status_lead_error_framing_event_i_idx_gets(), udma_i2c_status_reg_idx_status_lead_error_framing_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_error_nack_event_i_idx_get(), udma_i2c_status_reg_idx_status_lead_error_nack_event_i_idx_gets(), udma_i2c_status_reg_idx_status_lead_error_nack_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_purge_event_o_idx_get(), udma_i2c_status_reg_idx_status_lead_purge_event_o_idx_gets(), udma_i2c_status_reg_idx_status_lead_purge_event_o_idx_set(), udma_i2c_status_reg_idx_status_lead_unlock_event_o_idx_get(), udma_i2c_status_reg_idx_status_lead_unlock_event_o_idx_gets(), udma_i2c_status_reg_idx_status_lead_unlock_event_o_idx_set(), udma_i2c_udma_cmd_dest_reg_idx_get(), udma_i2s_clkcfg_setup_get(), udma_i2s_glb_setup_get(), udma_i2s_slot_cfg_0_get(), udma_i2s_slot_cfg_10_get(), udma_i2s_slot_cfg_11_get(), udma_i2s_slot_cfg_12_get(), udma_i2s_slot_cfg_13_get(), udma_i2s_slot_cfg_14_get(), udma_i2s_slot_cfg_15_get(), udma_i2s_slot_cfg_1_get(), udma_i2s_slot_cfg_2_get(), udma_i2s_slot_cfg_3_get(), udma_i2s_slot_cfg_4_get(), udma_i2s_slot_cfg_5_get(), udma_i2s_slot_cfg_6_get(), udma_i2s_slot_cfg_7_get(), udma_i2s_slot_cfg_8_get(), udma_i2s_slot_cfg_9_get(), udma_i2s_slot_cfg_get(), udma_i2s_slot_en_get(), udma_i2s_word_size_0_1_get(), udma_i2s_word_size_10_11_get(), udma_i2s_word_size_12_13_get(), udma_i2s_word_size_14_15_get(), udma_i2s_word_size_2_3_get(), udma_i2s_word_size_4_5_get(), udma_i2s_word_size_6_7_get(), udma_i2s_word_size_8_9_get(), udma_i2s_word_size_get(), udma_mram_clk_div_data_get(), udma_mram_clk_div_data_gets(), udma_mram_clk_div_data_set(), udma_mram_clk_div_enable_get(), udma_mram_clk_div_enable_gets(), udma_mram_clk_div_enable_set(), udma_mram_clk_div_get(), udma_mram_clk_div_valid_get(), udma_mram_clk_div_valid_gets(), udma_mram_clk_div_valid_set(), udma_mram_enable_2d_enable_get(), udma_mram_enable_2d_enable_gets(), udma_mram_enable_2d_enable_set(), udma_mram_enable_2d_get(), udma_mram_erase_addr_addr_lsb_get(), udma_mram_erase_addr_addr_lsb_gets(), udma_mram_erase_addr_addr_lsb_set(), udma_mram_erase_addr_addr_msb_get(), udma_mram_erase_addr_addr_msb_gets(), udma_mram_erase_addr_addr_msb_set(), udma_mram_erase_addr_get(), udma_mram_erase_size_get(), udma_mram_erase_size_size_get(), udma_mram_erase_size_size_gets(), udma_mram_erase_size_size_set(), udma_mram_ext_addr_addr_get(), udma_mram_ext_addr_addr_gets(), udma_mram_ext_addr_get(), udma_mram_ier_erase_en_get(), udma_mram_ier_erase_en_gets(), udma_mram_ier_erase_en_set(), udma_mram_ier_get(), udma_mram_ier_program_en_get(), udma_mram_ier_program_en_gets(), udma_mram_ier_program_en_set(), udma_mram_ier_rx_done_en_get(), udma_mram_ier_rx_done_en_gets(), udma_mram_ier_rx_done_en_set(), udma_mram_ier_rx_xip_done_en_get(), udma_mram_ier_rx_xip_done_en_gets(), udma_mram_ier_rx_xip_done_en_set(), udma_mram_ier_trim_config_en_get(), udma_mram_ier_trim_config_en_gets(), udma_mram_ier_trim_config_en_set(), udma_mram_ier_xip_erase_en_get(), udma_mram_ier_xip_erase_en_gets(), udma_mram_ier_xip_erase_en_set(), udma_mram_ier_xip_program_en_get(), udma_mram_ier_xip_program_en_gets(), udma_mram_ier_xip_program_en_set(), udma_mram_ier_xip_trim_config_en_get(), udma_mram_ier_xip_trim_config_en_gets(), udma_mram_ier_xip_trim_config_en_set(), udma_mram_isr_erase_done_get(), udma_mram_isr_erase_done_gets(), udma_mram_isr_erase_done_set(), udma_mram_isr_get(), udma_mram_isr_program_done_get(), udma_mram_isr_program_done_gets(), udma_mram_isr_program_done_set(), udma_mram_isr_rx_done_get(), udma_mram_isr_rx_done_gets(), udma_mram_isr_rx_done_set(), udma_mram_isr_trim_config_done_get(), udma_mram_isr_trim_config_done_gets(), udma_mram_isr_trim_config_done_set(), udma_mram_line_2d_get(), udma_mram_line_2d_line_get(), udma_mram_line_2d_line_gets(), udma_mram_mode_dpd_get(), udma_mram_mode_dpd_gets(), udma_mram_mode_dpd_set(), udma_mram_mode_eccbyps_get(), udma_mram_mode_eccbyps_gets(), udma_mram_mode_eccbyps_set(), udma_mram_mode_get(), udma_mram_mode_nvr_get(), udma_mram_mode_nvr_gets(), udma_mram_mode_nvr_set(), udma_mram_mode_operation_get(), udma_mram_mode_operation_gets(), udma_mram_mode_operation_set(), udma_mram_mode_porb_get(), udma_mram_mode_porb_gets(), udma_mram_mode_porb_set(), udma_mram_mode_retb_get(), udma_mram_mode_retb_gets(), udma_mram_mode_retb_set(), udma_mram_mode_rstb_get(), udma_mram_mode_rstb_gets(), udma_mram_mode_rstb_set(), udma_mram_mode_tmen_get(), udma_mram_mode_tmen_gets(), udma_mram_mode_tmen_set(), udma_mram_rx_dest_dest_get(), udma_mram_rx_dest_dest_gets(), udma_mram_rx_dest_dest_set(), udma_mram_rx_dest_get(), udma_mram_status_ec_err_get(), udma_mram_status_ec_err_gets(), udma_mram_status_ec_err_set(), udma_mram_status_erase_busy_get(), udma_mram_status_erase_busy_gets(), udma_mram_status_erase_busy_set(), udma_mram_status_get(), udma_mram_status_rx_busy_get(), udma_mram_status_rx_busy_gets(), udma_mram_status_rx_busy_set(), udma_mram_status_tx_busy_get(), udma_mram_status_tx_busy_gets(), udma_mram_status_tx_busy_set(), udma_mram_status_ue_err_get(), udma_mram_status_ue_err_gets(), udma_mram_status_ue_err_set(), udma_mram_stride_2d_get(), udma_mram_stride_2d_stride_get(), udma_mram_stride_2d_stride_gets(), udma_mram_timing_cfg_ads_time_cnt_get(), udma_mram_timing_cfg_ads_time_cnt_gets(), udma_mram_timing_cfg_ads_time_cnt_set(), udma_mram_timing_cfg_get(), udma_mram_timing_cfg_go_sup_time_cnt_get(), udma_mram_timing_cfg_go_sup_time_cnt_gets(), udma_mram_timing_cfg_go_sup_time_cnt_set(), udma_mram_timing_cfg_men_time_cnt_get(), udma_mram_timing_cfg_men_time_cnt_gets(), udma_mram_timing_cfg_men_time_cnt_set(), udma_mram_timing_cfg_pgs_time_cnt_get(), udma_mram_timing_cfg_pgs_time_cnt_gets(), udma_mram_timing_cfg_pgs_time_cnt_set(), udma_mram_timing_cfg_prog_time_cnt_get(), udma_mram_timing_cfg_prog_time_cnt_gets(), udma_mram_timing_cfg_prog_time_cnt_set(), udma_mram_timing_cfg_rw_time_cnt_get(), udma_mram_timing_cfg_rw_time_cnt_gets(), udma_mram_timing_cfg_rw_time_cnt_set(), udma_mram_timing_cfg_strobe_time_cnt_get(), udma_mram_timing_cfg_strobe_time_cnt_gets(), udma_mram_timing_cfg_strobe_time_cnt_set(), udma_mram_trans_addr_addr_get(), udma_mram_trans_addr_addr_gets(), udma_mram_trans_addr_get(), udma_mram_trans_cfg_get(), udma_mram_trans_cfg_rxtx_get(), udma_mram_trans_cfg_rxtx_gets(), udma_mram_trans_cfg_rxtx_set(), udma_mram_trans_cfg_valid_get(), udma_mram_trans_cfg_valid_gets(), udma_mram_trans_cfg_valid_set(), udma_mram_trans_mode_auto_ena_get(), udma_mram_trans_mode_auto_ena_gets(), udma_mram_trans_mode_auto_ena_set(), udma_mram_trans_mode_get(), udma_mram_trans_mode_reserved_get(), udma_mram_trans_mode_reserved_gets(), udma_mram_trans_mode_reserved_set(), udma_mram_trans_mode_xip_en_get(), udma_mram_trans_mode_xip_en_gets(), udma_mram_trans_mode_xip_en_set(), udma_mram_trans_mode_xip_halted_get(), udma_mram_trans_mode_xip_halted_gets(), udma_mram_trans_mode_xip_halted_set(), udma_mram_trans_size_get(), udma_mram_trans_size_size_get(), udma_mram_trans_size_size_gets(), udma_mram_trans_size_size_set(), udma_mram_tx_dest_dest_get(), udma_mram_tx_dest_dest_gets(), udma_mram_tx_dest_dest_set(), udma_mram_tx_dest_get(), udma_sdio_sdio_clk_div_get(), udma_sdio_sdio_cmd_arg_get(), udma_sdio_sdio_cmd_op_get(), udma_sdio_sdio_data_setup_get(), udma_sdio_sdio_rsp0_get(), udma_sdio_sdio_rsp1_get(), udma_sdio_sdio_rsp2_get(), udma_sdio_sdio_rsp3_get(), udma_sdio_sdio_rx_cfg_get(), udma_sdio_sdio_rx_initcfg_get(), udma_sdio_sdio_rx_saddr_get(), udma_sdio_sdio_rx_size_get(), udma_sdio_sdio_start_get(), udma_sdio_sdio_status_get(), udma_sdio_sdio_tx_cfg_get(), udma_sdio_sdio_tx_initcfg_get(), udma_sdio_sdio_tx_saddr_get(), udma_sdio_sdio_tx_size_get(), udma_spim_cmd_dest_get(), udma_spim_rx_dest_get(), udma_spim_status_get(), udma_spim_tx_dest_get(), udma_timestamp_reg_clk_cfg_clk_mux_en_get(), udma_timestamp_reg_clk_cfg_clk_mux_en_gets(), udma_timestamp_reg_clk_cfg_clk_mux_en_set(), udma_timestamp_reg_clk_cfg_clk_mux_get(), udma_timestamp_reg_clk_cfg_clk_mux_gets(), udma_timestamp_reg_clk_cfg_clk_mux_set(), udma_timestamp_reg_clk_cfg_get(), udma_timestamp_reg_clk_cfg_gpio_sel_get(), udma_timestamp_reg_clk_cfg_gpio_sel_gets(), udma_timestamp_reg_clk_cfg_gpio_sel_set(), udma_timestamp_reg_clk_cfg_prescaler_get(), udma_timestamp_reg_clk_cfg_prescaler_gets(), udma_timestamp_reg_clk_cfg_prescaler_set(), udma_timestamp_reg_clk_cfg_pwm_sel_get(), udma_timestamp_reg_clk_cfg_pwm_sel_gets(), udma_timestamp_reg_clk_cfg_pwm_sel_set(), udma_timestamp_reg_cmd_cnt_clr_get(), udma_timestamp_reg_cmd_cnt_clr_gets(), udma_timestamp_reg_cmd_cnt_clr_set(), udma_timestamp_reg_cmd_cnt_stop_get(), udma_timestamp_reg_cmd_cnt_stop_gets(), udma_timestamp_reg_cmd_cnt_stop_set(), udma_timestamp_reg_cmd_get(), udma_timestamp_reg_dest_get(), udma_timestamp_reg_dest_rx_dest_get(), udma_timestamp_reg_dest_rx_dest_gets(), udma_timestamp_reg_dest_rx_dest_set(), udma_timestamp_reg_setup_ch0_1_get(), udma_timestamp_reg_setup_ch0_1_input_en_ch0_get(), udma_timestamp_reg_setup_ch0_1_input_en_ch0_gets(), udma_timestamp_reg_setup_ch0_1_input_en_ch0_set(), udma_timestamp_reg_setup_ch0_1_input_en_ch1_get(), udma_timestamp_reg_setup_ch0_1_input_en_ch1_gets(), udma_timestamp_reg_setup_ch0_1_input_en_ch1_set(), udma_timestamp_reg_setup_ch0_1_input_sel_ch0_get(), udma_timestamp_reg_setup_ch0_1_input_sel_ch0_gets(), udma_timestamp_reg_setup_ch0_1_input_sel_ch0_set(), udma_timestamp_reg_setup_ch0_1_input_sel_ch1_get(), udma_timestamp_reg_setup_ch0_1_input_sel_ch1_gets(), udma_timestamp_reg_setup_ch0_1_input_sel_ch1_set(), udma_timestamp_reg_setup_ch0_1_input_type_ch0_get(), udma_timestamp_reg_setup_ch0_1_input_type_ch0_gets(), udma_timestamp_reg_setup_ch0_1_input_type_ch0_set(), udma_timestamp_reg_setup_ch0_1_input_type_ch1_get(), udma_timestamp_reg_setup_ch0_1_input_type_ch1_gets(), udma_timestamp_reg_setup_ch0_1_input_type_ch1_set(), udma_timestamp_reg_setup_ch2_3_get(), udma_timestamp_reg_setup_ch2_3_input_en_ch2_get(), udma_timestamp_reg_setup_ch2_3_input_en_ch2_gets(), udma_timestamp_reg_setup_ch2_3_input_en_ch2_set(), udma_timestamp_reg_setup_ch2_3_input_en_ch3_get(), udma_timestamp_reg_setup_ch2_3_input_en_ch3_gets(), udma_timestamp_reg_setup_ch2_3_input_en_ch3_set(), udma_timestamp_reg_setup_ch2_3_input_sel_ch2_get(), udma_timestamp_reg_setup_ch2_3_input_sel_ch2_gets(), udma_timestamp_reg_setup_ch2_3_input_sel_ch2_set(), udma_timestamp_reg_setup_ch2_3_input_sel_ch3_get(), udma_timestamp_reg_setup_ch2_3_input_sel_ch3_gets(), udma_timestamp_reg_setup_ch2_3_input_sel_ch3_set(), udma_timestamp_reg_setup_ch2_3_input_type_ch2_get(), udma_timestamp_reg_setup_ch2_3_input_type_ch2_gets(), udma_timestamp_reg_setup_ch2_3_input_type_ch2_set(), udma_timestamp_reg_setup_ch2_3_input_type_ch3_get(), udma_timestamp_reg_setup_ch2_3_input_type_ch3_gets(), udma_timestamp_reg_setup_ch2_3_input_type_ch3_set(), udma_timestamp_reg_setup_ch4_5_get(), udma_timestamp_reg_setup_ch4_5_input_en_ch4_get(), udma_timestamp_reg_setup_ch4_5_input_en_ch4_gets(), udma_timestamp_reg_setup_ch4_5_input_en_ch4_set(), udma_timestamp_reg_setup_ch4_5_input_en_ch5_get(), udma_timestamp_reg_setup_ch4_5_input_en_ch5_gets(), udma_timestamp_reg_setup_ch4_5_input_en_ch5_set(), udma_timestamp_reg_setup_ch4_5_input_sel_ch4_get(), udma_timestamp_reg_setup_ch4_5_input_sel_ch4_gets(), udma_timestamp_reg_setup_ch4_5_input_sel_ch4_set(), udma_timestamp_reg_setup_ch4_5_input_sel_ch5_get(), udma_timestamp_reg_setup_ch4_5_input_sel_ch5_gets(), udma_timestamp_reg_setup_ch4_5_input_sel_ch5_set(), udma_timestamp_reg_setup_ch4_5_input_type_ch4_get(), udma_timestamp_reg_setup_ch4_5_input_type_ch4_gets(), udma_timestamp_reg_setup_ch4_5_input_type_ch4_set(), udma_timestamp_reg_setup_ch4_5_input_type_ch5_get(), udma_timestamp_reg_setup_ch4_5_input_type_ch5_gets(), udma_timestamp_reg_setup_ch4_5_input_type_ch5_set(), udma_timestamp_reg_setup_ch6_7_get(), udma_timestamp_reg_setup_ch6_7_input_en_ch6_get(), udma_timestamp_reg_setup_ch6_7_input_en_ch6_gets(), udma_timestamp_reg_setup_ch6_7_input_en_ch6_set(), udma_timestamp_reg_setup_ch6_7_input_en_ch7_get(), udma_timestamp_reg_setup_ch6_7_input_en_ch7_gets(), udma_timestamp_reg_setup_ch6_7_input_en_ch7_set(), udma_timestamp_reg_setup_ch6_7_input_sel_ch6_get(), udma_timestamp_reg_setup_ch6_7_input_sel_ch6_gets(), udma_timestamp_reg_setup_ch6_7_input_sel_ch6_set(), udma_timestamp_reg_setup_ch6_7_input_sel_ch7_get(), udma_timestamp_reg_setup_ch6_7_input_sel_ch7_gets(), udma_timestamp_reg_setup_ch6_7_input_sel_ch7_set(), udma_timestamp_reg_setup_ch6_7_input_type_ch6_get(), udma_timestamp_reg_setup_ch6_7_input_type_ch6_gets(), udma_timestamp_reg_setup_ch6_7_input_type_ch6_set(), udma_timestamp_reg_setup_ch6_7_input_type_ch7_get(), udma_timestamp_reg_setup_ch6_7_input_type_ch7_gets(), udma_timestamp_reg_setup_ch6_7_input_type_ch7_set(), udma_timestamp_reg_setup_cnt_cnt_ext_en_get(), udma_timestamp_reg_setup_cnt_cnt_ext_en_gets(), udma_timestamp_reg_setup_cnt_cnt_ext_en_set(), udma_timestamp_reg_setup_cnt_cnt_ext_sel_get(), udma_timestamp_reg_setup_cnt_cnt_ext_sel_gets(), udma_timestamp_reg_setup_cnt_cnt_ext_sel_set(), udma_timestamp_reg_setup_cnt_cnt_ext_type_get(), udma_timestamp_reg_setup_cnt_cnt_ext_type_gets(), udma_timestamp_reg_setup_cnt_cnt_ext_type_set(), udma_timestamp_reg_setup_cnt_get(), udma_uart_error_get(), udma_uart_irq_en_get(), udma_uart_rx_dest_get(), udma_uart_setup_2_get(), udma_uart_setup_get(), udma_uart_status_get(), and udma_uart_tx_dest_get().
| #define GAP_WRITE | ( | base, | |
| offset, | |||
| value | |||
| ) |
Referenced by adv_timer_cg_ena_set(), adv_timer_cg_set(), adv_timer_ch_mux_ch_sel_0_set(), adv_timer_ch_mux_ch_sel_1_set(), adv_timer_ch_mux_ch_sel_2_set(), adv_timer_ch_mux_ch_sel_3_set(), adv_timer_ch_mux_ch_sel_4_set(), adv_timer_ch_mux_ch_sel_5_set(), adv_timer_ch_mux_ch_sel_6_set(), adv_timer_ch_mux_ch_sel_7_set(), adv_timer_ch_mux_set(), adv_timer_event_cfg_ena_set(), adv_timer_event_cfg_sel0_set(), adv_timer_event_cfg_sel1_set(), adv_timer_event_cfg_sel2_set(), adv_timer_event_cfg_sel3_set(), adv_timer_event_cfg_set(), adv_timer_t0_cmd_arm_set(), adv_timer_t0_cmd_reset_set(), adv_timer_t0_cmd_rfu_set(), adv_timer_t0_cmd_set(), adv_timer_t0_cmd_start_set(), adv_timer_t0_cmd_stop_set(), adv_timer_t0_cmd_update_set(), adv_timer_t0_config_clksel_set(), adv_timer_t0_config_insel_set(), adv_timer_t0_config_mode_set(), adv_timer_t0_config_presc_set(), adv_timer_t0_config_set(), adv_timer_t0_config_updownsel_set(), adv_timer_t0_counter_counter_set(), adv_timer_t0_counter_set(), adv_timer_t0_th_channel0_lut_set(), adv_timer_t0_th_channel0_mode_set(), adv_timer_t0_th_channel0_set(), adv_timer_t0_th_channel0_th_set(), adv_timer_t0_th_channel1_lut_set(), adv_timer_t0_th_channel1_mode_set(), adv_timer_t0_th_channel1_set(), adv_timer_t0_th_channel1_th_set(), adv_timer_t0_th_channel2_lut_set(), adv_timer_t0_th_channel2_mode_set(), adv_timer_t0_th_channel2_set(), adv_timer_t0_th_channel2_th_set(), adv_timer_t0_th_channel3_lut_set(), adv_timer_t0_th_channel3_mode_set(), adv_timer_t0_th_channel3_set(), adv_timer_t0_th_channel3_th_set(), adv_timer_t0_threshold_set(), adv_timer_t0_threshold_th_hi_set(), adv_timer_t0_threshold_th_lo_set(), adv_timer_t1_cmd_arm_set(), adv_timer_t1_cmd_reset_set(), adv_timer_t1_cmd_set(), adv_timer_t1_cmd_start_set(), adv_timer_t1_cmd_stop_set(), adv_timer_t1_cmd_update_set(), adv_timer_t1_config_clksel_set(), adv_timer_t1_config_insel_set(), adv_timer_t1_config_mode_set(), adv_timer_t1_config_presc_set(), adv_timer_t1_config_set(), adv_timer_t1_config_updownsel_set(), adv_timer_t1_counter_counter_set(), adv_timer_t1_counter_set(), adv_timer_t1_th_channel0_lut_set(), adv_timer_t1_th_channel0_mode_set(), adv_timer_t1_th_channel0_set(), adv_timer_t1_th_channel0_th_set(), adv_timer_t1_th_channel1_lut_set(), adv_timer_t1_th_channel1_mode_set(), adv_timer_t1_th_channel1_set(), adv_timer_t1_th_channel1_th_set(), adv_timer_t1_th_channel2_lut_set(), adv_timer_t1_th_channel2_mode_set(), adv_timer_t1_th_channel2_set(), adv_timer_t1_th_channel2_th_set(), adv_timer_t1_th_channel3_lut_set(), adv_timer_t1_th_channel3_mode_set(), adv_timer_t1_th_channel3_set(), adv_timer_t1_th_channel3_th_set(), adv_timer_t1_threshold_set(), adv_timer_t1_threshold_th_hi_set(), adv_timer_t1_threshold_th_lo_set(), adv_timer_t2_cmd_arm_set(), adv_timer_t2_cmd_reset_set(), adv_timer_t2_cmd_set(), adv_timer_t2_cmd_start_set(), adv_timer_t2_cmd_stop_set(), adv_timer_t2_cmd_update_set(), adv_timer_t2_config_clksel_set(), adv_timer_t2_config_insel_set(), adv_timer_t2_config_mode_set(), adv_timer_t2_config_presc_set(), adv_timer_t2_config_set(), adv_timer_t2_config_updownsel_set(), adv_timer_t2_counter_counter_set(), adv_timer_t2_counter_set(), adv_timer_t2_th_channel0_lut_set(), adv_timer_t2_th_channel0_mode_set(), adv_timer_t2_th_channel0_set(), adv_timer_t2_th_channel0_th_set(), adv_timer_t2_th_channel1_lut_set(), adv_timer_t2_th_channel1_mode_set(), adv_timer_t2_th_channel1_set(), adv_timer_t2_th_channel1_th_set(), adv_timer_t2_th_channel2_lut_set(), adv_timer_t2_th_channel2_mode_set(), adv_timer_t2_th_channel2_set(), adv_timer_t2_th_channel2_th_set(), adv_timer_t2_th_channel3_lut_set(), adv_timer_t2_th_channel3_mode_set(), adv_timer_t2_th_channel3_set(), adv_timer_t2_th_channel3_th_set(), adv_timer_t2_threshold_set(), adv_timer_t2_threshold_th_hi_set(), adv_timer_t2_threshold_th_lo_set(), adv_timer_t3_cmd_arm_set(), adv_timer_t3_cmd_reset_set(), adv_timer_t3_cmd_set(), adv_timer_t3_cmd_start_set(), adv_timer_t3_cmd_stop_set(), adv_timer_t3_cmd_update_set(), adv_timer_t3_config_clksel_set(), adv_timer_t3_config_insel_set(), adv_timer_t3_config_mode_set(), adv_timer_t3_config_presc_set(), adv_timer_t3_config_set(), adv_timer_t3_config_updownsel_set(), adv_timer_t3_counter_counter_set(), adv_timer_t3_counter_set(), adv_timer_t3_th_channel0_lut_set(), adv_timer_t3_th_channel0_mode_set(), adv_timer_t3_th_channel0_set(), adv_timer_t3_th_channel0_th_set(), adv_timer_t3_th_channel1_lut_set(), adv_timer_t3_th_channel1_mode_set(), adv_timer_t3_th_channel1_set(), adv_timer_t3_th_channel1_th_set(), adv_timer_t3_th_channel2_lut_set(), adv_timer_t3_th_channel2_mode_set(), adv_timer_t3_th_channel2_set(), adv_timer_t3_th_channel2_th_set(), adv_timer_t3_th_channel3_lut_set(), adv_timer_t3_th_channel3_mode_set(), adv_timer_t3_th_channel3_set(), adv_timer_t3_th_channel3_th_set(), adv_timer_t3_threshold_set(), adv_timer_t3_threshold_th_hi_set(), adv_timer_t3_threshold_th_lo_set(), apb_soc_ctrl_bootsel_set(), apb_soc_ctrl_cl_busy_set(), apb_soc_ctrl_cl_isolate_set(), apb_soc_ctrl_clk_div_clu_set(), apb_soc_ctrl_clk_div_i3c_set(), apb_soc_ctrl_clk_div_per_set(), apb_soc_ctrl_clk_div_soc_set(), apb_soc_ctrl_clk_en_quiddikey_set(), apb_soc_ctrl_clk_sel_set(), apb_soc_ctrl_corestatus_set(), apb_soc_ctrl_fc_boot_set(), apb_soc_ctrl_fc_fetch_set(), apb_soc_ctrl_info_set(), apb_soc_ctrl_jtagreg_set(), apb_soc_ctrl_padcfg0_set(), apb_soc_ctrl_padcfg10_set(), apb_soc_ctrl_padcfg11_set(), apb_soc_ctrl_padcfg12_set(), apb_soc_ctrl_padcfg13_set(), apb_soc_ctrl_padcfg14_set(), apb_soc_ctrl_padcfg15_set(), apb_soc_ctrl_padcfg16_set(), apb_soc_ctrl_padcfg17_set(), apb_soc_ctrl_padcfg18_set(), apb_soc_ctrl_padcfg19_set(), apb_soc_ctrl_padcfg1_set(), apb_soc_ctrl_padcfg20_set(), apb_soc_ctrl_padcfg21_set(), apb_soc_ctrl_padcfg22_set(), apb_soc_ctrl_padcfg23_set(), apb_soc_ctrl_padcfg2_set(), apb_soc_ctrl_padcfg3_set(), apb_soc_ctrl_padcfg4_set(), apb_soc_ctrl_padcfg5_set(), apb_soc_ctrl_padcfg6_set(), apb_soc_ctrl_padcfg7_set(), apb_soc_ctrl_padcfg8_set(), apb_soc_ctrl_padcfg9_set(), apb_soc_ctrl_padfun0_set(), apb_soc_ctrl_padfun1_set(), apb_soc_ctrl_padfun2_set(), apb_soc_ctrl_padfun3_set(), apb_soc_ctrl_padfun4_set(), apb_soc_ctrl_padfun5_set(), apb_soc_ctrl_reserved0_set(), apb_soc_ctrl_reserved10_set(), apb_soc_ctrl_reserved11_set(), apb_soc_ctrl_reserved12_set(), apb_soc_ctrl_reserved1_set(), apb_soc_ctrl_reserved2_set(), apb_soc_ctrl_reserved3_set(), apb_soc_ctrl_reserved4_set(), apb_soc_ctrl_reserved5_set(), apb_soc_ctrl_reserved6_set(), apb_soc_ctrl_reserved7_set(), apb_soc_ctrl_reserved8_set(), apb_soc_ctrl_reserved9_set(), apb_soc_ctrl_rwm_l2_intl_set(), apb_soc_ctrl_rwm_l2_pri_set(), apb_soc_ctrl_sleep_ctrl_old_set(), apb_soc_ctrl_sleep_ctrl_set(), apb_soc_ctrl_supervisor_dbg_set(), apb_soc_ctrl_wakeup_ctrl_set(), apb_soc_ctrl_wd_rst_set(), cl_dma_cmd_set(), cl_dma_status_set(), cluster_ctrl_unit_boot_addr0_set(), cluster_ctrl_unit_boot_addr1_set(), cluster_ctrl_unit_boot_addr2_set(), cluster_ctrl_unit_boot_addr3_set(), cluster_ctrl_unit_boot_addr4_set(), cluster_ctrl_unit_boot_addr5_set(), cluster_ctrl_unit_boot_addr6_set(), cluster_ctrl_unit_boot_addr7_set(), cluster_ctrl_unit_clock_gate_set(), cluster_ctrl_unit_dbg_halt_mask_set(), cluster_ctrl_unit_dbg_halt_status_set(), cluster_ctrl_unit_dbg_resume_set(), cluster_ctrl_unit_eoc_set(), cluster_ctrl_unit_fetch_en_set(), cluster_ctrl_unit_tcdm_arb_policy_ch0_rep_set(), cluster_ctrl_unit_tcdm_arb_policy_ch0_set(), cluster_ctrl_unit_tcdm_arb_policy_ch1_rep_set(), cluster_ctrl_unit_tcdm_arb_policy_ch1_set(), cluster_icache_ctrl_enable_l1_l15_prefetch_set(), cluster_icache_ctrl_enable_set(), cluster_icache_ctrl_enable_special_core_cache_set(), cluster_icache_ctrl_flush_set(), cluster_icache_ctrl_l0_flush_set(), cluster_icache_ctrl_sel_flush_set(), decompressor_bit_read_reg_bit_read_set(), decompressor_bit_read_reg_set(), decompressor_clock_enable_reg_clock_enable_set(), decompressor_clock_enable_reg_set(), decompressor_conf_reg_decompr_direction_set(), decompressor_conf_reg_decompr_mode_set(), decompressor_conf_reg_extension_type_set(), decompressor_conf_reg_item_bit_width_set(), decompressor_conf_reg_item_to_decompress_set(), decompressor_conf_reg_set(), decompressor_conf_reg_sign_extension_set(), decompressor_conf_reg_start_bit_set(), decompressor_conf_reg_start_byte_set(), decompressor_l2_addr_reg_l2_start_addr_set(), decompressor_l2_addr_reg_set(), decompressor_l2_count_reg_l2_linear_count_set(), decompressor_l2_count_reg_set(), decompressor_l2_stride_reg_l2_stride_count_set(), decompressor_l2_stride_reg_set(), decompressor_lut_write_reg_lut_addr_set(), decompressor_lut_write_reg_lut_data_set(), decompressor_lut_write_reg_set(), decompressor_mode_reg_set(), decompressor_mode_reg_transf_mode_set(), decompressor_push_cmd_reg_set(), decompressor_push_cmd_reg_trigger_set(), decompressor_soft_reset_reg_set(), decompressor_soft_reset_reg_soft_reset_set(), decompressor_special_symbol_reg_set(), decompressor_special_symbol_reg_special_symbol_set(), decompressor_status_reg_set(), decompressor_status_reg_status_set(), decompressor_tcdm_addr_reg_set(), decompressor_tcdm_addr_reg_tcdm_start_addr_set(), decompressor_tcdm_count_reg_set(), decompressor_tcdm_count_reg_tcdm_linear_count_set(), decompressor_tcdm_stride_reg_set(), decompressor_tcdm_stride_reg_tcdm_stride_count_set(), efuse_cfg_set(), efuse_cmd_set(), fc_icache_ctrl_enable_set(), fc_icache_ctrl_flush_set(), fc_icache_ctrl_sel_flush_set(), fc_icache_ctrl_status_set(), fc_itc_ack_clear_set(), fc_itc_ack_set(), fc_itc_ack_set_set(), fc_itc_fifo_set(), fc_itc_mask_clear_set(), fc_itc_mask_set(), fc_itc_mask_set_set(), fc_itc_status_clear_set(), fc_itc_status_set(), fc_itc_status_set_set(), fc_mpu_apb_rule0_set(), fc_mpu_apb_rule1_set(), fc_mpu_apb_rule2_set(), fc_mpu_apb_rule3_set(), fc_mpu_apb_rule4_set(), fc_mpu_apb_rule5_set(), fc_mpu_apb_rule6_set(), fc_mpu_apb_rule7_set(), fc_mpu_fc_tcdm_rule0_set(), fc_mpu_fc_tcdm_rule1_set(), fc_mpu_fc_tcdm_rule2_set(), fc_mpu_fc_tcdm_rule3_set(), fc_mpu_fc_tcdm_rule4_set(), fc_mpu_fc_tcdm_rule5_set(), fc_mpu_fc_tcdm_rule6_set(), fc_mpu_fc_tcdm_rule7_set(), fc_mpu_l2_rule0_set(), fc_mpu_l2_rule1_set(), fc_mpu_l2_rule2_set(), fc_mpu_l2_rule3_set(), fc_mpu_l2_rule4_set(), fc_mpu_l2_rule5_set(), fc_mpu_l2_rule6_set(), fc_mpu_l2_rule7_set(), fc_mpu_mpu_enable_set(), fll_ccr1_clk0_div_set(), fll_ccr1_clk1_div_set(), fll_ccr1_clk2_div_set(), fll_ccr1_clk3_div_set(), fll_ccr1_set(), fll_ccr2_ckg0_set(), fll_ccr2_ckg1_set(), fll_ccr2_ckg2_set(), fll_ccr2_ckg3_set(), fll_ccr2_clk0_sel_set(), fll_ccr2_clk1_sel_set(), fll_ccr2_clk2_sel_set(), fll_ccr2_clk3_sel_set(), fll_ccr2_set(), fll_drr_dco_max_set(), fll_drr_dco_min_set(), fll_drr_set(), fll_f0cr1_dco_en_set(), fll_f0cr1_itg_per_set(), fll_f0cr1_lock_tol_set(), fll_f0cr1_loop_gain_set(), fll_f0cr1_op_mode_set(), fll_f0cr1_set(), fll_f0cr1_stbl_set(), fll_f0cr1_ttm_en_set(), fll_f0cr2_dco_code_set(), fll_f0cr2_mfi_set(), fll_f0cr2_set(), fll_f1cr1_dco_en_set(), fll_f1cr1_itg_per_set(), fll_f1cr1_lock_tol_set(), fll_f1cr1_loop_gain_set(), fll_f1cr1_op_mode_set(), fll_f1cr1_set(), fll_f1cr1_stbl_set(), fll_f1cr1_ttm_en_set(), fll_f1cr2_dco_code_set(), fll_f1cr2_mfi_set(), fll_f1cr2_set(), fll_f2cr1_dco_en_set(), fll_f2cr1_itg_per_set(), fll_f2cr1_lock_tol_set(), fll_f2cr1_loop_gain_set(), fll_f2cr1_op_mode_set(), fll_f2cr1_set(), fll_f2cr1_stbl_set(), fll_f2cr1_ttm_en_set(), fll_f2cr2_dco_code_set(), fll_f2cr2_mfi_set(), fll_f2cr2_set(), fll_f3cr1_dco_en_set(), fll_f3cr1_itg_per_set(), fll_f3cr1_lock_tol_set(), fll_f3cr1_loop_gain_set(), fll_f3cr1_op_mode_set(), fll_f3cr1_set(), fll_f3cr1_stbl_set(), fll_f3cr1_ttm_en_set(), fll_f3cr2_dco_code_set(), fll_f3cr2_mfi_set(), fll_f3cr2_set(), fll_fcr1_set(), fll_fcr2_set(), fll_fsr_clmp_hi_err0_set(), fll_fsr_clmp_hi_err1_set(), fll_fsr_clmp_hi_err2_set(), fll_fsr_clmp_hi_err3_set(), fll_fsr_clmp_lo_err0_set(), fll_fsr_clmp_lo_err1_set(), fll_fsr_clmp_lo_err2_set(), fll_fsr_clmp_lo_err3_set(), fll_fsr_fdc_sat_err0_set(), fll_fsr_fdc_sat_err1_set(), fll_fsr_fdc_sat_err2_set(), fll_fsr_fdc_sat_err3_set(), fll_fsr_lock0_set(), fll_fsr_lock1_set(), fll_fsr_lock2_set(), fll_fsr_lock3_set(), fll_fsr_set(), fll_ttr_refresh_set(), fll_ttr_set(), gpio_gpioen_00_31_gpioen_set(), gpio_gpioen_00_31_set(), gpio_gpioen_32_63_gpioen_set(), gpio_gpioen_32_63_set(), gpio_gpioen_64_95_gpioen_set(), gpio_gpioen_64_95_set(), gpio_gpioen_set(), gpio_inten_00_31_inten_set(), gpio_inten_00_31_set(), gpio_inten_32_63_inten_set(), gpio_inten_32_63_set(), gpio_inten_64_95_inten_set(), gpio_inten_64_95_set(), gpio_inten_set(), gpio_intstatus_00_31_intstatus_set(), gpio_intstatus_00_31_set(), gpio_intstatus_32_63_intstatus_set(), gpio_intstatus_32_63_set(), gpio_intstatus_64_95_intstatus_set(), gpio_intstatus_64_95_set(), gpio_intstatus_set(), gpio_inttype_00_15_inttype_set(), gpio_inttype_00_15_set(), gpio_inttype_16_31_inttype_set(), gpio_inttype_16_31_set(), gpio_inttype_32_47_inttype_set(), gpio_inttype_32_47_set(), gpio_inttype_48_63_inttype_set(), gpio_inttype_48_63_set(), gpio_inttype_64_79_inttype_set(), gpio_inttype_64_79_set(), gpio_inttype_80_95_inttype_set(), gpio_inttype_80_95_set(), gpio_inttype_set(), gpio_padcfg_00_03_padcfg_set(), gpio_padcfg_00_03_set(), gpio_padcfg_04_07_padcfg_set(), gpio_padcfg_04_07_set(), gpio_padcfg_08_11_padcfg_set(), gpio_padcfg_08_11_set(), gpio_padcfg_12_15_padcfg_set(), gpio_padcfg_12_15_set(), gpio_padcfg_16_19_padcfg_set(), gpio_padcfg_16_19_set(), gpio_padcfg_20_23_padcfg_set(), gpio_padcfg_20_23_set(), gpio_padcfg_24_27_padcfg_set(), gpio_padcfg_24_27_set(), gpio_padcfg_28_31_padcfg_set(), gpio_padcfg_28_31_set(), gpio_padcfg_32_35_padcfg_set(), gpio_padcfg_32_35_set(), gpio_padcfg_36_39_padcfg_set(), gpio_padcfg_36_39_set(), gpio_padcfg_40_43_padcfg_set(), gpio_padcfg_40_43_set(), gpio_padcfg_44_47_padcfg_set(), gpio_padcfg_44_47_set(), gpio_padcfg_48_51_padcfg_set(), gpio_padcfg_48_51_set(), gpio_padcfg_52_55_padcfg_set(), gpio_padcfg_52_55_set(), gpio_padcfg_56_59_padcfg_set(), gpio_padcfg_56_59_set(), gpio_padcfg_60_63_padcfg_set(), gpio_padcfg_60_63_set(), gpio_padcfg_64_67_padcfg_set(), gpio_padcfg_64_67_set(), gpio_padcfg_68_71_padcfg_set(), gpio_padcfg_68_71_set(), gpio_padcfg_72_75_padcfg_set(), gpio_padcfg_72_75_set(), gpio_padcfg_76_79_padcfg_set(), gpio_padcfg_76_79_set(), gpio_padcfg_80_83_padcfg_set(), gpio_padcfg_80_83_set(), gpio_padcfg_84_87_padcfg_set(), gpio_padcfg_84_87_set(), gpio_padcfg_88_91_padcfg_set(), gpio_padcfg_88_91_set(), gpio_padcfg_92_95_padcfg_set(), gpio_padcfg_92_95_set(), gpio_padcfg_set(), gpio_paddir_00_31_paddir_set(), gpio_paddir_00_31_set(), gpio_paddir_32_63_paddir_set(), gpio_paddir_32_63_set(), gpio_paddir_64_95_paddir_set(), gpio_paddir_64_95_set(), gpio_paddir_set(), gpio_padin_00_31_padin_set(), gpio_padin_00_31_set(), gpio_padin_32_63_padin_set(), gpio_padin_32_63_set(), gpio_padin_64_95_padin_set(), gpio_padin_64_95_set(), gpio_padin_set(), gpio_padout_00_31_padout_set(), gpio_padout_00_31_set(), gpio_padout_32_63_padout_set(), gpio_padout_32_63_set(), gpio_padout_64_95_padout_set(), gpio_padout_64_95_set(), gpio_padout_clear(), gpio_padout_set(), gpio_padoutclr_00_31_padoutclr_set(), gpio_padoutclr_00_31_set(), gpio_padoutclr_32_63_padoutclr_set(), gpio_padoutclr_32_63_set(), gpio_padoutclr_64_95_padoutclr_set(), gpio_padoutclr_64_95_set(), gpio_padoutset_00_31_padoutset_set(), gpio_padoutset_00_31_set(), gpio_padoutset_32_63_padoutset_set(), gpio_padoutset_32_63_set(), gpio_padoutset_64_95_padoutset_set(), gpio_padoutset_64_95_set(), hal_cl_boot_addr_set(), hal_cl_eu_barrier_setup(), hal_cl_eu_barrier_trigger(), hal_cl_eu_dispatch_fifo_push(), hal_cl_eu_dispatch_team_config(), hal_cl_eu_evt_clear(), hal_cl_eu_evt_mask_clear(), hal_cl_eu_evt_mask_set(), hal_cl_eu_glob_sw_trig(), hal_cl_eu_irq_mask_clear(), hal_cl_eu_irq_mask_set(), hal_cl_eu_mutex_init(), hal_cl_eu_mutex_unlock(), hal_udma_ctrl_timeout_mode_set(), hal_udma_ctrl_timeout_prescaler_reset(), hal_udma_ctrl_timeout_prescaler_set(), hal_udma_ctrl_timeout_timeout_set(), hal_udma_ctrl_timeout_timeout_start(), hal_udma_ctrl_timeout_timeout_stop(), hwce_acquire_set(), hwce_finished_jobs_set(), hwce_gen_config0_set(), hwce_gen_config1_set(), hwce_gen_config2_set(), hwce_gen_config3_set(), hwce_job_config0_aliased_set(), hwce_job_config0_ctx0_set(), hwce_job_config0_ctx1_set(), hwce_job_config1_aliased_set(), hwce_job_config1_ctx0_set(), hwce_job_config1_ctx1_set(), hwce_job_config2_aliased_set(), hwce_job_config2_ctx0_set(), hwce_job_config2_ctx1_set(), hwce_offloader_id_set(), hwce_running_job_set(), hwce_soft_clear_set(), hwce_status_set(), hwce_sw_evt_set(), hwce_trigger_set(), hwce_w_base_addr_aliased_set(), hwce_w_base_addr_ctx0_set(), hwce_w_base_addr_ctx1_set(), hwce_x_feat_stride_length_aliased_set(), hwce_x_feat_stride_length_ctx0_set(), hwce_x_feat_stride_length_ctx1_set(), hwce_x_in_base_addr_aliased_set(), hwce_x_in_base_addr_ctx0_set(), hwce_x_in_base_addr_ctx1_set(), hwce_x_line_stride_length_aliased_set(), hwce_x_line_stride_length_ctx0_set(), hwce_x_line_stride_length_ctx1_set(), hwce_x_trans_size_aliased_set(), hwce_x_trans_size_ctx0_set(), hwce_x_trans_size_ctx1_set(), hwce_y_feat_stride_length_aliased_set(), hwce_y_feat_stride_length_ctx0_set(), hwce_y_feat_stride_length_ctx1_set(), hwce_y_in_0_base_addr_aliased_set(), hwce_y_in_0_base_addr_ctx0_set(), hwce_y_in_0_base_addr_ctx1_set(), hwce_y_in_1_base_addr_aliased_set(), hwce_y_in_1_base_addr_ctx0_set(), hwce_y_in_1_base_addr_ctx1_set(), hwce_y_in_2_base_addr_aliased_set(), hwce_y_in_2_base_addr_ctx0_set(), hwce_y_in_2_base_addr_ctx1_set(), hwce_y_line_stride_length_aliased_set(), hwce_y_line_stride_length_ctx0_set(), hwce_y_line_stride_length_ctx1_set(), hwce_y_out_0_base_addr_aliased_set(), hwce_y_out_0_base_addr_ctx0_set(), hwce_y_out_0_base_addr_ctx1_set(), hwce_y_out_1_base_addr_aliased_set(), hwce_y_out_1_base_addr_ctx0_set(), hwce_y_out_1_base_addr_ctx1_set(), hwce_y_out_2_base_addr_aliased_set(), hwce_y_out_2_base_addr_ctx0_set(), hwce_y_out_2_base_addr_ctx1_set(), hwce_y_trans_size_aliased_set(), hwce_y_trans_size_ctx0_set(), hwce_y_trans_size_ctx1_set(), i3c_bus_avail_timer_reg_set(), i3c_bus_free_timer_reg_set(), i3c_cmd_tr_req_reg_1_set(), i3c_cmd_tr_req_reg_2_set(), i3c_data_rx_fifo_reg_set(), i3c_data_tx_fifo_reg_set(), i3c_device_addr_table_reg0_set(), i3c_device_addr_table_reg10_set(), i3c_device_addr_table_reg11_set(), i3c_device_addr_table_reg1_set(), i3c_device_addr_table_reg2_set(), i3c_device_addr_table_reg3_set(), i3c_device_addr_table_reg4_set(), i3c_device_addr_table_reg5_set(), i3c_device_addr_table_reg6_set(), i3c_device_addr_table_reg7_set(), i3c_device_addr_table_reg8_set(), i3c_device_addr_table_reg9_set(), i3c_device_char_table_reg0_0_set(), i3c_device_char_table_reg0_10_set(), i3c_device_char_table_reg0_11_set(), i3c_device_char_table_reg0_1_set(), i3c_device_char_table_reg0_2_set(), i3c_device_char_table_reg0_3_set(), i3c_device_char_table_reg0_4_set(), i3c_device_char_table_reg0_5_set(), i3c_device_char_table_reg0_6_set(), i3c_device_char_table_reg0_7_set(), i3c_device_char_table_reg0_8_set(), i3c_device_char_table_reg0_9_set(), i3c_device_char_table_reg1_0_set(), i3c_device_char_table_reg1_10_set(), i3c_device_char_table_reg1_11_set(), i3c_device_char_table_reg1_1_set(), i3c_device_char_table_reg1_2_set(), i3c_device_char_table_reg1_3_set(), i3c_device_char_table_reg1_4_set(), i3c_device_char_table_reg1_5_set(), i3c_device_char_table_reg1_6_set(), i3c_device_char_table_reg1_7_set(), i3c_device_char_table_reg1_8_set(), i3c_device_char_table_reg1_9_set(), i3c_device_char_table_reg2_0_set(), i3c_device_char_table_reg2_10_set(), i3c_device_char_table_reg2_11_set(), i3c_device_char_table_reg2_1_set(), i3c_device_char_table_reg2_2_set(), i3c_device_char_table_reg2_3_set(), i3c_device_char_table_reg2_4_set(), i3c_device_char_table_reg2_5_set(), i3c_device_char_table_reg2_6_set(), i3c_device_char_table_reg2_7_set(), i3c_device_char_table_reg2_8_set(), i3c_device_char_table_reg2_9_set(), i3c_device_char_table_reg3_0_set(), i3c_device_char_table_reg3_10_set(), i3c_device_char_table_reg3_11_set(), i3c_device_char_table_reg3_1_set(), i3c_device_char_table_reg3_2_set(), i3c_device_char_table_reg3_3_set(), i3c_device_char_table_reg3_4_set(), i3c_device_char_table_reg3_5_set(), i3c_device_char_table_reg3_6_set(), i3c_device_char_table_reg3_7_set(), i3c_device_char_table_reg3_8_set(), i3c_device_char_table_reg3_9_set(), i3c_ibi_data_reg_set(), i3c_ibi_resp_reg_set(), i3c_irq_status_reg_set(), i3c_mst_cntl_en_reg_set(), i3c_resp_reg_set(), i3c_tcas_timer_reg_set(), i3c_tcbp_timer_reg_set(), i3c_tcbsr_timer_reg_set(), i3c_tds_timer_reg_set(), i3c_thd_ddr_timer_reg_set(), i3c_thd_pp_timer_reg_set(), i3c_thd_sta_timer_reg_set(), i3c_thigh_od_timer_reg_set(), i3c_thigh_pp_timer_reg_set(), i3c_thigh_timer_reg_set(), i3c_tidle_timer_reg_set(), i3c_tlow_od_timer_reg_set(), i3c_tlow_pp_timer_reg_set(), i3c_tlow_timer_reg_set(), i3c_tsco_timer_reg_set(), i3c_tsu_sta_timer_reg_set(), i3c_tsu_stop_timer_reg_set(), i3c_tvd_data_timer_reg_set(), non_secured_riscv_debug_cause_set(), non_secured_riscv_debug_csr_hwlp0c_set(), non_secured_riscv_debug_csr_hwlp0e_set(), non_secured_riscv_debug_csr_hwlp0s_set(), non_secured_riscv_debug_csr_hwlp1c_set(), non_secured_riscv_debug_csr_hwlp1e_set(), non_secured_riscv_debug_csr_hwlp1s_set(), non_secured_riscv_debug_csr_mcause_set(), non_secured_riscv_debug_csr_mepc_set(), non_secured_riscv_debug_csr_mhartid_set(), non_secured_riscv_debug_csr_mstatus_set(), non_secured_riscv_debug_csr_mtvec_set(), non_secured_riscv_debug_csr_pccr_set(), non_secured_riscv_debug_csr_pcer_set(), non_secured_riscv_debug_csr_pcmr_set(), non_secured_riscv_debug_csr_privlv_set(), non_secured_riscv_debug_csr_uhartid_set(), non_secured_riscv_debug_ctrl_set(), non_secured_riscv_debug_gpr0_set(), non_secured_riscv_debug_gpr10_set(), non_secured_riscv_debug_gpr11_set(), non_secured_riscv_debug_gpr12_set(), non_secured_riscv_debug_gpr13_set(), non_secured_riscv_debug_gpr14_set(), non_secured_riscv_debug_gpr15_set(), non_secured_riscv_debug_gpr16_set(), non_secured_riscv_debug_gpr17_set(), non_secured_riscv_debug_gpr18_set(), non_secured_riscv_debug_gpr19_set(), non_secured_riscv_debug_gpr1_set(), non_secured_riscv_debug_gpr20_set(), non_secured_riscv_debug_gpr21_set(), non_secured_riscv_debug_gpr22_set(), non_secured_riscv_debug_gpr23_set(), non_secured_riscv_debug_gpr24_set(), non_secured_riscv_debug_gpr25_set(), non_secured_riscv_debug_gpr26_set(), non_secured_riscv_debug_gpr27_set(), non_secured_riscv_debug_gpr28_set(), non_secured_riscv_debug_gpr29_set(), non_secured_riscv_debug_gpr2_set(), non_secured_riscv_debug_gpr30_set(), non_secured_riscv_debug_gpr31_set(), non_secured_riscv_debug_gpr3_set(), non_secured_riscv_debug_gpr4_set(), non_secured_riscv_debug_gpr5_set(), non_secured_riscv_debug_gpr6_set(), non_secured_riscv_debug_gpr7_set(), non_secured_riscv_debug_gpr8_set(), non_secured_riscv_debug_gpr9_set(), non_secured_riscv_debug_hit_set(), non_secured_riscv_debug_ie_set(), non_secured_riscv_debug_npc_set(), non_secured_riscv_debug_ppc_set(), power_manager_dlcpd_idl_ifr_set(), power_manager_dlcpd_idn_ifr_set(), power_manager_dlcpd_ifr_set(), power_manager_dlcpd_imr_set(), power_manager_dlcpd_iok_ifr_set(), power_manager_dlcpd_iup_ifr_set(), power_manager_dlcpd_mpacr_set(), power_manager_dlcpd_mpadr_set(), power_manager_dlcpd_msr_set(), quiddikey_ar_set(), quiddikey_cr_set(), quiddikey_dir_set(), quiddikey_dor_set(), quiddikey_hw_id_set(), quiddikey_hw_info_set(), quiddikey_hw_ruc0_set(), quiddikey_hw_ruc1_set(), quiddikey_hw_setting_set(), quiddikey_hw_ver_set(), quiddikey_ier_set(), quiddikey_if_sr_set(), quiddikey_imr_set(), quiddikey_isr_set(), quiddikey_key_dest_set(), quiddikey_misc_set(), quiddikey_sr_set(), quiddikey_test_set(), rtc_apb_cr_set(), rtc_apb_dr_set(), rtc_apb_icr_set(), rtc_apb_ifr_set(), rtc_apb_imr_set(), rtc_apb_sr_set(), rtc_reserved_set(), secured_riscv_debug_cause_set(), secured_riscv_debug_csr_hwlp0c_set(), secured_riscv_debug_csr_hwlp0e_set(), secured_riscv_debug_csr_hwlp0s_set(), secured_riscv_debug_csr_hwlp1c_set(), secured_riscv_debug_csr_hwlp1e_set(), secured_riscv_debug_csr_hwlp1s_set(), secured_riscv_debug_csr_mcause_set(), secured_riscv_debug_csr_mepc_set(), secured_riscv_debug_csr_mhartid_set(), secured_riscv_debug_csr_mstatus_set(), secured_riscv_debug_csr_mtvec_set(), secured_riscv_debug_csr_pccr_set(), secured_riscv_debug_csr_pcer_set(), secured_riscv_debug_csr_pcmr_set(), secured_riscv_debug_csr_privlv_set(), secured_riscv_debug_csr_ucause_set(), secured_riscv_debug_csr_uepc_set(), secured_riscv_debug_csr_uhartid_set(), secured_riscv_debug_csr_ustatus_set(), secured_riscv_debug_csr_utvec_set(), secured_riscv_debug_ctrl_set(), secured_riscv_debug_gpr0_set(), secured_riscv_debug_gpr10_set(), secured_riscv_debug_gpr11_set(), secured_riscv_debug_gpr12_set(), secured_riscv_debug_gpr13_set(), secured_riscv_debug_gpr14_set(), secured_riscv_debug_gpr15_set(), secured_riscv_debug_gpr16_set(), secured_riscv_debug_gpr17_set(), secured_riscv_debug_gpr18_set(), secured_riscv_debug_gpr19_set(), secured_riscv_debug_gpr1_set(), secured_riscv_debug_gpr20_set(), secured_riscv_debug_gpr21_set(), secured_riscv_debug_gpr22_set(), secured_riscv_debug_gpr23_set(), secured_riscv_debug_gpr24_set(), secured_riscv_debug_gpr25_set(), secured_riscv_debug_gpr26_set(), secured_riscv_debug_gpr27_set(), secured_riscv_debug_gpr28_set(), secured_riscv_debug_gpr29_set(), secured_riscv_debug_gpr2_set(), secured_riscv_debug_gpr30_set(), secured_riscv_debug_gpr31_set(), secured_riscv_debug_gpr3_set(), secured_riscv_debug_gpr4_set(), secured_riscv_debug_gpr5_set(), secured_riscv_debug_gpr6_set(), secured_riscv_debug_gpr7_set(), secured_riscv_debug_gpr8_set(), secured_riscv_debug_gpr9_set(), secured_riscv_debug_hit_set(), secured_riscv_debug_ie_set(), secured_riscv_debug_npc_set(), secured_riscv_debug_ppc_set(), soc_ctrl_padcfg_set(), soc_ctrl_padfun_set(), soc_eu_cl_mask_lsb_set(), soc_eu_cl_mask_msb_set(), soc_eu_err_lsb_set(), soc_eu_err_msb_set(), soc_eu_fc_mask_lsb_set(), soc_eu_fc_mask_msb_set(), soc_eu_pr_mask_lsb_set(), soc_eu_pr_mask_msb_set(), soc_eu_sw_event_set(), soc_eu_timer1_sel_hi_set(), soc_eu_timer1_sel_lo_set(), soc_eu_timer2_sel_hi_set(), soc_eu_timer2_sel_lo_set(), timer_unit_cfg_hi_set(), timer_unit_cfg_lo_set(), timer_unit_cmp_hi_set(), timer_unit_cmp_lo_set(), timer_unit_cnt_hi_set(), timer_unit_cnt_lo_set(), timer_unit_reset_hi_set(), timer_unit_reset_lo_set(), timer_unit_start_hi_set(), timer_unit_start_lo_set(), udma_aes_cfg_mode_set(), udma_aes_cfg_set(), udma_aes_dest_rx_dest_set(), udma_aes_dest_set(), udma_aes_dest_tx_dest_set(), udma_aes_iv0_0_set(), udma_aes_iv0_1_set(), udma_aes_iv0_2_set(), udma_aes_iv0_3_set(), udma_aes_key0_0_set(), udma_aes_key0_1_set(), udma_aes_key0_2_set(), udma_aes_key0_3_set(), udma_aes_key0_4_set(), udma_aes_key0_5_set(), udma_aes_key0_6_set(), udma_aes_key0_7_set(), udma_aes_setup_block_rst_set(), udma_aes_setup_ecb_cbc_set(), udma_aes_setup_enc_dec_set(), udma_aes_setup_fifo_clr_set(), udma_aes_setup_key_init_set(), udma_aes_setup_key_type_set(), udma_aes_setup_reserved_set(), udma_aes_setup_set(), udma_asrc_ctrl_cfg_0_clk_en_set(), udma_asrc_ctrl_cfg_0_fs_in_set(), udma_asrc_ctrl_cfg_0_fs_out_set(), udma_asrc_ctrl_cfg_0_lock_wnd_set(), udma_asrc_ctrl_cfg_0_rstn_set(), udma_asrc_ctrl_cfg_0_set(), udma_asrc_ctrl_cfg_1_clk_en_set(), udma_asrc_ctrl_cfg_1_fs_in_set(), udma_asrc_ctrl_cfg_1_fs_out_set(), udma_asrc_ctrl_cfg_1_lock_wnd_set(), udma_asrc_ctrl_cfg_1_rstn_set(), udma_asrc_ctrl_cfg_1_set(), udma_asrc_ctrl_cfg_set(), udma_asrc_lane_cfg_0_ch_en_set(), udma_asrc_lane_cfg_0_clk_en_set(), udma_asrc_lane_cfg_0_ctrl_mux_set(), udma_asrc_lane_cfg_0_drop_on_wait_set(), udma_asrc_lane_cfg_0_rstn_set(), udma_asrc_lane_cfg_0_set(), udma_asrc_lane_cfg_0_use_stream_in_set(), udma_asrc_lane_cfg_0_use_stream_out_set(), udma_asrc_lane_cfg_0_wait_lock_in_set(), udma_asrc_lane_cfg_0_wait_lock_out_set(), udma_asrc_lane_cfg_1_ch_en_set(), udma_asrc_lane_cfg_1_clk_en_set(), udma_asrc_lane_cfg_1_ctrl_mux_set(), udma_asrc_lane_cfg_1_drop_on_wait_set(), udma_asrc_lane_cfg_1_rstn_set(), udma_asrc_lane_cfg_1_set(), udma_asrc_lane_cfg_1_use_stream_in_set(), udma_asrc_lane_cfg_1_use_stream_out_set(), udma_asrc_lane_cfg_1_wait_lock_in_set(), udma_asrc_lane_cfg_1_wait_lock_out_set(), udma_asrc_lane_cfg_2_ch_en_set(), udma_asrc_lane_cfg_2_clk_en_set(), udma_asrc_lane_cfg_2_ctrl_mux_set(), udma_asrc_lane_cfg_2_drop_on_wait_set(), udma_asrc_lane_cfg_2_rstn_set(), udma_asrc_lane_cfg_2_set(), udma_asrc_lane_cfg_2_use_stream_in_set(), udma_asrc_lane_cfg_2_use_stream_out_set(), udma_asrc_lane_cfg_2_wait_lock_in_set(), udma_asrc_lane_cfg_2_wait_lock_out_set(), udma_asrc_lane_cfg_3_ch_en_set(), udma_asrc_lane_cfg_3_clk_en_set(), udma_asrc_lane_cfg_3_ctrl_mux_set(), udma_asrc_lane_cfg_3_drop_on_wait_set(), udma_asrc_lane_cfg_3_rstn_set(), udma_asrc_lane_cfg_3_set(), udma_asrc_lane_cfg_3_use_stream_in_set(), udma_asrc_lane_cfg_3_use_stream_out_set(), udma_asrc_lane_cfg_3_wait_lock_in_set(), udma_asrc_lane_cfg_3_wait_lock_out_set(), udma_asrc_lane_cfg_set(), udma_asrc_lane_idin_0_id_ch0_set(), udma_asrc_lane_idin_0_id_ch1_set(), udma_asrc_lane_idin_0_id_ch2_set(), udma_asrc_lane_idin_0_id_ch3_set(), udma_asrc_lane_idin_0_set(), udma_asrc_lane_idin_1_id_ch0_set(), udma_asrc_lane_idin_1_id_ch1_set(), udma_asrc_lane_idin_1_id_ch2_set(), udma_asrc_lane_idin_1_id_ch3_set(), udma_asrc_lane_idin_1_set(), udma_asrc_lane_idin_2_id_ch0_set(), udma_asrc_lane_idin_2_id_ch1_set(), udma_asrc_lane_idin_2_id_ch2_set(), udma_asrc_lane_idin_2_id_ch3_set(), udma_asrc_lane_idin_2_set(), udma_asrc_lane_idin_3_id_ch0_set(), udma_asrc_lane_idin_3_id_ch1_set(), udma_asrc_lane_idin_3_id_ch2_set(), udma_asrc_lane_idin_3_id_ch3_set(), udma_asrc_lane_idin_3_set(), udma_asrc_lane_idout_0_id_ch0_set(), udma_asrc_lane_idout_0_id_ch1_set(), udma_asrc_lane_idout_0_id_ch2_set(), udma_asrc_lane_idout_0_id_ch3_set(), udma_asrc_lane_idout_0_set(), udma_asrc_lane_idout_1_id_ch0_set(), udma_asrc_lane_idout_1_id_ch1_set(), udma_asrc_lane_idout_1_id_ch2_set(), udma_asrc_lane_idout_1_id_ch3_set(), udma_asrc_lane_idout_1_set(), udma_asrc_lane_idout_2_id_ch0_set(), udma_asrc_lane_idout_2_id_ch1_set(), udma_asrc_lane_idout_2_id_ch2_set(), udma_asrc_lane_idout_2_id_ch3_set(), udma_asrc_lane_idout_2_set(), udma_asrc_lane_idout_3_id_ch0_set(), udma_asrc_lane_idout_3_id_ch1_set(), udma_asrc_lane_idout_3_id_ch2_set(), udma_asrc_lane_idout_3_id_ch3_set(), udma_asrc_lane_idout_3_set(), udma_asrc_mem2mem_cfg_ch_en_set(), udma_asrc_mem2mem_cfg_clk_en_set(), udma_asrc_mem2mem_cfg_ctx_id_set(), udma_asrc_mem2mem_cfg_fs_in_set(), udma_asrc_mem2mem_cfg_fs_out_set(), udma_asrc_mem2mem_cfg_restore_set(), udma_asrc_mem2mem_cfg_rstn_set(), udma_asrc_mem2mem_cfg_set(), udma_asrc_mem2mem_cfg_store_set(), udma_asrc_mem2mem_id_m2m_in_ch0_set(), udma_asrc_mem2mem_id_m2m_in_ch1_set(), udma_asrc_mem2mem_id_m2m_out_ch0_set(), udma_asrc_mem2mem_id_m2m_out_ch1_set(), udma_asrc_mem2mem_id_set(), udma_asrc_mem2mem_ratio_m2m_ratio_en_set(), udma_asrc_mem2mem_ratio_m2m_ratio_set(), udma_asrc_mem2mem_ratio_set(), udma_asrc_status_lock_set(), udma_asrc_status_set(), udma_core_2d_addrgen_cfg_bytes_left_bytes_left_set(), udma_core_2d_addrgen_cfg_bytes_left_set(), udma_core_2d_addrgen_cfg_ctrl_cont_set(), udma_core_2d_addrgen_cfg_ctrl_en_set(), udma_core_2d_addrgen_cfg_ctrl_set(), udma_core_2d_addrgen_cfg_ctrl_stop_set(), udma_core_2d_addrgen_cfg_curr_addr_curr_addr_set(), udma_core_2d_addrgen_cfg_curr_addr_set(), udma_core_2d_addrgen_cfg_row_len_row_len_set(), udma_core_2d_addrgen_cfg_row_len_set(), udma_core_2d_addrgen_cfg_sa_buf0_sa_addr0_set(), udma_core_2d_addrgen_cfg_sa_buf0_set(), udma_core_2d_addrgen_cfg_sa_buf1_sa_addr1_set(), udma_core_2d_addrgen_cfg_sa_buf1_set(), udma_core_2d_addrgen_cfg_size_set(), udma_core_2d_addrgen_cfg_size_size_set(), udma_core_2d_addrgen_cfg_stride_set(), udma_core_2d_addrgen_cfg_stride_stride_set(), udma_core_fifo_cfg_ctrl_en_set(), udma_core_fifo_cfg_ctrl_set(), udma_core_fifo_cfg_ctrl_stop_set(), udma_core_fifo_cfg_ctrl_timeout_mon_set(), udma_core_fifo_cfg_evt_en_set(), udma_core_fifo_cfg_evt_num_bytes_set(), udma_core_fifo_cfg_evt_set(), udma_core_fifo_cfg_fifo_fill_set(), udma_core_fifo_cfg_sa_buffer_set(), udma_core_fifo_cfg_size_set(), udma_core_lin_addrgen_cfg_bytes_left_set(), udma_core_lin_addrgen_cfg_ctrl_set(), udma_core_lin_addrgen_cfg_curr_addr_set(), udma_core_lin_addrgen_cfg_sa_buf0_set(), udma_core_lin_addrgen_cfg_sa_buf1_set(), udma_core_lin_addrgen_cfg_size_set(), udma_cpi_cam_cfg_glob_en_set(), udma_cpi_cam_cfg_glob_format_set(), udma_cpi_cam_cfg_glob_framedrop_en_set(), udma_cpi_cam_cfg_glob_framedrop_val_set(), udma_cpi_cam_cfg_glob_frameslice_en_set(), udma_cpi_cam_cfg_glob_set(), udma_cpi_cam_cfg_ll_frameslice_llx_set(), udma_cpi_cam_cfg_ll_frameslice_lly_set(), udma_cpi_cam_cfg_ll_set(), udma_cpi_cam_cfg_rgb_sequence_set(), udma_cpi_cam_cfg_rgb_set(), udma_cpi_cam_cfg_size_rowlen_set(), udma_cpi_cam_cfg_size_set(), udma_cpi_cam_cfg_ur_frameslice_urx_set(), udma_cpi_cam_cfg_ur_frameslice_ury_set(), udma_cpi_cam_cfg_ur_set(), udma_cpi_cam_hsync_polarity_hsync_polarity_set(), udma_cpi_cam_rx_datasize_rx_datasize_set(), udma_cpi_cam_rx_datasize_set(), udma_cpi_cam_rx_dest_rx_dest_set(), udma_cpi_cam_rx_dest_set(), udma_cpi_cam_sync_polarity_set(), udma_cpi_cam_vsync_polarity_vsync_polarity_set(), udma_ctrl_cfg_cg_clr_set(), udma_ctrl_cfg_cg_set(), udma_ctrl_cfg_cg_set_set(), udma_ctrl_cfg_event_cmp_evt0_set(), udma_ctrl_cfg_event_cmp_evt1_set(), udma_ctrl_cfg_event_cmp_evt2_set(), udma_ctrl_cfg_event_cmp_evt3_set(), udma_ctrl_cfg_event_set(), udma_ctrl_cfg_rstn_clr_set(), udma_ctrl_cfg_rstn_set(), udma_ctrl_cfg_rstn_set_set(), udma_ctrl_datamove0_size_en_set(), udma_ctrl_datamove0_size_set(), udma_ctrl_datamove0_size_size_set(), udma_ctrl_datamove0_size_stop_set(), udma_ctrl_datamove1_size_en_set(), udma_ctrl_datamove1_size_set(), udma_ctrl_datamove1_size_size_set(), udma_ctrl_datamove1_size_stop_set(), udma_ctrl_datamove_cfg_dest_id_0_set(), udma_ctrl_datamove_cfg_dest_id_1_set(), udma_ctrl_datamove_cfg_set(), udma_ctrl_datamove_cfg_source_id_0_set(), udma_ctrl_datamove_cfg_source_id_1_set(), udma_ctrl_fifo_cfg_pop_id_set(), udma_ctrl_fifo_cfg_push_id_set(), udma_ctrl_fifo_cfg_set(), udma_ctrl_fifo_pushpop_16_set(), udma_ctrl_fifo_pushpop_24_set(), udma_ctrl_fifo_pushpop_32_set(), udma_ctrl_fifo_pushpop_8_set(), udma_ctrl_stream_cfg_set(), udma_ctrl_timeout_ch0_cnt_set(), udma_ctrl_timeout_ch0_en_set(), udma_ctrl_timeout_ch0_mode_set(), udma_ctrl_timeout_ch0_set(), udma_ctrl_timeout_ch0_source_id_set(), udma_ctrl_timeout_ch1_cnt_set(), udma_ctrl_timeout_ch1_en_set(), udma_ctrl_timeout_ch1_mode_set(), udma_ctrl_timeout_ch1_set(), udma_ctrl_timeout_ch1_source_id_set(), udma_ctrl_timeout_ch2_cnt_set(), udma_ctrl_timeout_ch2_en_set(), udma_ctrl_timeout_ch2_mode_set(), udma_ctrl_timeout_ch2_set(), udma_ctrl_timeout_ch2_source_id_set(), udma_ctrl_timeout_ch3_cnt_set(), udma_ctrl_timeout_ch3_en_set(), udma_ctrl_timeout_ch3_mode_set(), udma_ctrl_timeout_ch3_set(), udma_ctrl_timeout_ch3_source_id_set(), udma_ctrl_timeout_ch4_cnt_set(), udma_ctrl_timeout_ch4_en_set(), udma_ctrl_timeout_ch4_mode_set(), udma_ctrl_timeout_ch4_set(), udma_ctrl_timeout_ch4_source_id_set(), udma_ctrl_timeout_ch5_cnt_set(), udma_ctrl_timeout_ch5_en_set(), udma_ctrl_timeout_ch5_mode_set(), udma_ctrl_timeout_ch5_set(), udma_ctrl_timeout_ch5_source_id_set(), udma_ctrl_timeout_ch6_cnt_set(), udma_ctrl_timeout_ch6_en_set(), udma_ctrl_timeout_ch6_mode_set(), udma_ctrl_timeout_ch6_set(), udma_ctrl_timeout_ch6_source_id_set(), udma_ctrl_timeout_ch7_cnt_set(), udma_ctrl_timeout_ch7_en_set(), udma_ctrl_timeout_ch7_mode_set(), udma_ctrl_timeout_ch7_set(), udma_ctrl_timeout_ch7_source_id_set(), udma_ctrl_timeout_pre0_clr_set(), udma_ctrl_timeout_pre0_cnt_set(), udma_ctrl_timeout_pre0_en_set(), udma_ctrl_timeout_pre0_set(), udma_ctrl_timeout_pre1_clr_set(), udma_ctrl_timeout_pre1_cnt_set(), udma_ctrl_timeout_pre1_en_set(), udma_ctrl_timeout_pre1_set(), udma_ctrl_timeout_pre2_clr_set(), udma_ctrl_timeout_pre2_cnt_set(), udma_ctrl_timeout_pre2_en_set(), udma_ctrl_timeout_pre2_set(), udma_ctrl_timeout_pre3_clr_set(), udma_ctrl_timeout_pre3_cnt_set(), udma_ctrl_timeout_pre3_en_set(), udma_ctrl_timeout_pre3_set(), udma_ctrl_timeout_pre4_clr_set(), udma_ctrl_timeout_pre4_cnt_set(), udma_ctrl_timeout_pre4_en_set(), udma_ctrl_timeout_pre4_set(), udma_ctrl_timeout_pre5_clr_set(), udma_ctrl_timeout_pre5_cnt_set(), udma_ctrl_timeout_pre5_en_set(), udma_ctrl_timeout_pre5_set(), udma_ctrl_timeout_pre6_clr_set(), udma_ctrl_timeout_pre6_cnt_set(), udma_ctrl_timeout_pre6_en_set(), udma_ctrl_timeout_pre6_set(), udma_ctrl_timeout_pre7_clr_set(), udma_ctrl_timeout_pre7_cnt_set(), udma_ctrl_timeout_pre7_en_set(), udma_ctrl_timeout_pre7_set(), udma_ffc_conv_num_set(), udma_ffc_conv_rx_addr_set(), udma_ffc_conv_tx_addr_set(), udma_ffc_fl_format_set(), udma_ffc_fp_format_set(), udma_ffc_fp_prec_set(), udma_ffc_fp_scale_set(), udma_ffc_irq_en_set(), udma_ffc_mode_set(), udma_ffc_rx_dest_set(), udma_ffc_start_set(), udma_ffc_status_set(), udma_ffc_trans_mode_set(), udma_ffc_tx_dest_set(), udma_filter_reg_au_cfg_set(), udma_filter_reg_au_reg0_set(), udma_filter_reg_au_reg1_set(), udma_filter_reg_bincu_cnt_set(), udma_filter_reg_bincu_setup_set(), udma_filter_reg_bincu_th_set(), udma_filter_reg_bincu_val_set(), udma_filter_reg_filt_cmd_set(), udma_filter_reg_filt_set(), udma_filter_reg_rx_ch_add_set(), udma_filter_reg_rx_ch_cfg_set(), udma_filter_reg_rx_ch_len0_set(), udma_filter_reg_rx_ch_len1_set(), udma_filter_reg_rx_ch_len2_set(), udma_filter_reg_status_set(), udma_filter_reg_tx_ch0_add_set(), udma_filter_reg_tx_ch0_cfg_set(), udma_filter_reg_tx_ch0_len0_set(), udma_filter_reg_tx_ch0_len1_set(), udma_filter_reg_tx_ch0_len2_set(), udma_filter_reg_tx_ch1_add_set(), udma_filter_reg_tx_ch1_cfg_set(), udma_filter_reg_tx_ch1_len0_set(), udma_filter_reg_tx_ch1_len1_set(), udma_filter_reg_tx_ch1_len2_set(), udma_hyper_burst_enable_2d_enable_set(), udma_hyper_burst_enable_2d_mode_set(), udma_hyper_burst_enable_cs0_auto_burst_enable_set(), udma_hyper_burst_enable_cs0_maximum_check_enable_set(), udma_hyper_burst_enable_cs1_auto_burst_enable_set(), udma_hyper_burst_enable_cs1_maximum_check_enable_set(), udma_hyper_burst_enable_set(), udma_hyper_clk_div_data_set(), udma_hyper_clk_div_set(), udma_hyper_clk_div_valid_set(), udma_hyper_device_dt0_set(), udma_hyper_device_dt1_set(), udma_hyper_device_sdio_set(), udma_hyper_device_set(), udma_hyper_device_type_set(), udma_hyper_ext_addr_reg_access_set(), udma_hyper_ext_addr_saddr_set(), udma_hyper_ext_addr_set(), udma_hyper_irq_en_en_set(), udma_hyper_irq_en_set(), udma_hyper_irq_en_xip_en_set(), udma_hyper_line_2d_line_set(), udma_hyper_line_2d_set(), udma_hyper_mba0_mba0_set(), udma_hyper_mba0_reserved_set(), udma_hyper_mba0_set(), udma_hyper_mba1_mba1_set(), udma_hyper_mba1_reserved_set(), udma_hyper_mba1_set(), udma_hyper_ospi_alter_mode0_set(), udma_hyper_ospi_alter_mode1_set(), udma_hyper_ospi_alter_set(), udma_hyper_ospi_alter_xip_mode0_set(), udma_hyper_ospi_alter_xip_mode1_set(), udma_hyper_ospi_alter_xip_set(), udma_hyper_ospi_cfg_addr_dtr_str_set(), udma_hyper_ospi_cfg_addr_size_set(), udma_hyper_ospi_cfg_cmd_dtr_str_set(), udma_hyper_ospi_cfg_cmd_size_set(), udma_hyper_ospi_cfg_data_dtr_msb_set(), udma_hyper_ospi_cfg_data_dtr_str_set(), udma_hyper_ospi_cfg_line_set(), udma_hyper_ospi_cfg_set(), udma_hyper_ospi_cfg_xip_addr_dtr_str_set(), udma_hyper_ospi_cfg_xip_addr_size_set(), udma_hyper_ospi_cfg_xip_cmd_dtr_str_set(), udma_hyper_ospi_cfg_xip_cmd_size_set(), udma_hyper_ospi_cfg_xip_data_dtr_msb_set(), udma_hyper_ospi_cfg_xip_data_dtr_str_set(), udma_hyper_ospi_cfg_xip_line_set(), udma_hyper_ospi_cfg_xip_set(), udma_hyper_ospi_cmd_cmd_set(), udma_hyper_ospi_cmd_sdio_cmd_op_set(), udma_hyper_ospi_cmd_sdio_cmd_rsp_type_set(), udma_hyper_ospi_cmd_set(), udma_hyper_ospi_cmd_xip_cmd_set(), udma_hyper_ospi_cmd_xip_sdio_cmd_op_set(), udma_hyper_ospi_cmd_xip_sdio_cmd_rsp_type_set(), udma_hyper_ospi_cmd_xip_set(), udma_hyper_ospi_csn_auto_en_set(), udma_hyper_ospi_csn_direct_ctrl_set(), udma_hyper_ospi_csn_index_set(), udma_hyper_ospi_csn_reserved_set(), udma_hyper_ospi_csn_sdio_auto_stop_set(), udma_hyper_ospi_csn_sdio_block_num_set(), udma_hyper_ospi_csn_sdio_block_size_set(), udma_hyper_ospi_csn_sdio_data_quad_ddr_set(), udma_hyper_ospi_csn_sdio_data_quad_set(), udma_hyper_ospi_csn_set(), udma_hyper_ospi_csn_value_set(), udma_hyper_ospi_jedec_reset_set(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_en_set(), udma_hyper_ospi_jedec_reset_user_ctrl_sdo0_value_set(), udma_hyper_ospi_ram_opt_opt_read_en_cs_set(), udma_hyper_ospi_ram_opt_psram_addr_even_set(), udma_hyper_ospi_ram_opt_psram_cmd_en_set(), udma_hyper_ospi_ram_opt_psram_cross_boundary_en_set(), udma_hyper_ospi_ram_opt_psram_read_bit_set(), udma_hyper_ospi_ram_opt_real_addr_en_set(), udma_hyper_ospi_ram_opt_set(), udma_hyper_ospi_reg_xip_set(), udma_hyper_ospi_reg_xip_xip_latency0_set(), udma_hyper_ospi_reg_xip_xip_latency1_set(), udma_hyper_rx_dest_dest_set(), udma_hyper_rx_dest_dest_stream_set(), udma_hyper_rx_dest_set(), udma_hyper_sdio_cmd_arg_arg_set(), udma_hyper_sdio_cmd_arg_set(), udma_hyper_sdio_rsp0_rsp0_set(), udma_hyper_sdio_rsp0_set(), udma_hyper_sdio_rsp1_rsp1_set(), udma_hyper_sdio_rsp1_set(), udma_hyper_sdio_rsp2_rsp2_set(), udma_hyper_sdio_rsp2_set(), udma_hyper_sdio_rsp3_rsp3_set(), udma_hyper_sdio_rsp3_set(), udma_hyper_status_reserved_set(), udma_hyper_status_rx_error_set(), udma_hyper_status_rx_tx_end_set(), udma_hyper_status_sdio_error_status_set(), udma_hyper_status_sdio_rx_tx_end_set(), udma_hyper_status_sdio_rx_tx_error_set(), udma_hyper_status_set(), udma_hyper_status_tx_error_set(), udma_hyper_stride_2d_set(), udma_hyper_stride_2d_stride_set(), udma_hyper_timing_cfg_additional_latency_autocheck_en_set(), udma_hyper_timing_cfg_cs_max_set(), udma_hyper_timing_cfg_latency0_set(), udma_hyper_timing_cfg_latency1_set(), udma_hyper_timing_cfg_rw_recovery_set(), udma_hyper_timing_cfg_rwds_delay_set(), udma_hyper_timing_cfg_set(), udma_hyper_trans_addr_addr_set(), udma_hyper_trans_addr_set(), udma_hyper_trans_cfg_rxtx_set(), udma_hyper_trans_cfg_set(), udma_hyper_trans_cfg_valid_set(), udma_hyper_trans_mode_auto_ena_set(), udma_hyper_trans_mode_set(), udma_hyper_trans_mode_stream_en_set(), udma_hyper_trans_mode_stream_xip_en_set(), udma_hyper_trans_mode_xip_en_set(), udma_hyper_trans_mode_xip_halted_set(), udma_hyper_trans_size_set(), udma_hyper_trans_size_size_set(), udma_hyper_tx_dest_dest_set(), udma_hyper_tx_dest_dest_stream_set(), udma_hyper_tx_dest_set(), udma_i2c_foll_udma_rx_dest_reg_idx_set(), udma_i2c_foll_udma_tx_dest_reg_idx_set(), udma_i2c_lead_udma_rx_dest_reg_idx_set(), udma_i2c_lead_udma_tx_dest_reg_idx_set(), udma_i2c_status_reg_idx_set(), udma_i2c_status_reg_idx_status_foll_eof_rcv_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_eof_snd_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_error_arlo_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_error_framing_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_purge_event_o_idx_set(), udma_i2c_status_reg_idx_status_foll_sof_rcv_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_sof_snd_event_i_idx_set(), udma_i2c_status_reg_idx_status_foll_unlock_event_o_idx_set(), udma_i2c_status_reg_idx_status_i2c_prescaler_set_div10_event_o_idx_set(), udma_i2c_status_reg_idx_status_i2c_soft_reset_event_o_idx_set(), udma_i2c_status_reg_idx_status_lead_command_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_error_arlo_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_error_framing_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_error_nack_event_i_idx_set(), udma_i2c_status_reg_idx_status_lead_purge_event_o_idx_set(), udma_i2c_status_reg_idx_status_lead_unlock_event_o_idx_set(), udma_i2c_udma_cmd_dest_reg_idx_set(), udma_i2s_clkcfg_setup_set(), udma_i2s_glb_setup_set(), udma_i2s_slot_cfg_0_set(), udma_i2s_slot_cfg_10_set(), udma_i2s_slot_cfg_11_set(), udma_i2s_slot_cfg_12_set(), udma_i2s_slot_cfg_13_set(), udma_i2s_slot_cfg_14_set(), udma_i2s_slot_cfg_15_set(), udma_i2s_slot_cfg_1_set(), udma_i2s_slot_cfg_2_set(), udma_i2s_slot_cfg_3_set(), udma_i2s_slot_cfg_4_set(), udma_i2s_slot_cfg_5_set(), udma_i2s_slot_cfg_6_set(), udma_i2s_slot_cfg_7_set(), udma_i2s_slot_cfg_8_set(), udma_i2s_slot_cfg_9_set(), udma_i2s_slot_cfg_set(), udma_i2s_slot_en_set(), udma_i2s_word_size_0_1_set(), udma_i2s_word_size_10_11_set(), udma_i2s_word_size_12_13_set(), udma_i2s_word_size_14_15_set(), udma_i2s_word_size_2_3_set(), udma_i2s_word_size_4_5_set(), udma_i2s_word_size_6_7_set(), udma_i2s_word_size_8_9_set(), udma_i2s_word_size_set(), udma_mram_clk_div_data_set(), udma_mram_clk_div_enable_set(), udma_mram_clk_div_set(), udma_mram_clk_div_valid_set(), udma_mram_enable_2d_enable_set(), udma_mram_enable_2d_set(), udma_mram_erase_addr_addr_lsb_set(), udma_mram_erase_addr_addr_msb_set(), udma_mram_erase_addr_set(), udma_mram_erase_size_set(), udma_mram_erase_size_size_set(), udma_mram_ext_addr_addr_set(), udma_mram_ext_addr_set(), udma_mram_ier_erase_en_set(), udma_mram_ier_program_en_set(), udma_mram_ier_rx_done_en_set(), udma_mram_ier_rx_xip_done_en_set(), udma_mram_ier_set(), udma_mram_ier_trim_config_en_set(), udma_mram_ier_xip_erase_en_set(), udma_mram_ier_xip_program_en_set(), udma_mram_ier_xip_trim_config_en_set(), udma_mram_isr_erase_done_set(), udma_mram_isr_program_done_set(), udma_mram_isr_rx_done_set(), udma_mram_isr_set(), udma_mram_isr_trim_config_done_set(), udma_mram_line_2d_line_set(), udma_mram_line_2d_set(), udma_mram_mode_dpd_set(), udma_mram_mode_eccbyps_set(), udma_mram_mode_nvr_set(), udma_mram_mode_operation_set(), udma_mram_mode_porb_set(), udma_mram_mode_retb_set(), udma_mram_mode_rstb_set(), udma_mram_mode_set(), udma_mram_mode_tmen_set(), udma_mram_rx_dest_dest_set(), udma_mram_rx_dest_set(), udma_mram_status_ec_err_set(), udma_mram_status_erase_busy_set(), udma_mram_status_rx_busy_set(), udma_mram_status_set(), udma_mram_status_tx_busy_set(), udma_mram_status_ue_err_set(), udma_mram_stride_2d_set(), udma_mram_stride_2d_stride_set(), udma_mram_timing_cfg_ads_time_cnt_set(), udma_mram_timing_cfg_go_sup_time_cnt_set(), udma_mram_timing_cfg_men_time_cnt_set(), udma_mram_timing_cfg_pgs_time_cnt_set(), udma_mram_timing_cfg_prog_time_cnt_set(), udma_mram_timing_cfg_rw_time_cnt_set(), udma_mram_timing_cfg_set(), udma_mram_timing_cfg_strobe_time_cnt_set(), udma_mram_trans_addr_addr_set(), udma_mram_trans_addr_set(), udma_mram_trans_cfg_rxtx_set(), udma_mram_trans_cfg_set(), udma_mram_trans_cfg_valid_set(), udma_mram_trans_mode_auto_ena_set(), udma_mram_trans_mode_reserved_set(), udma_mram_trans_mode_set(), udma_mram_trans_mode_xip_en_set(), udma_mram_trans_mode_xip_halted_set(), udma_mram_trans_size_set(), udma_mram_trans_size_size_set(), udma_mram_tx_dest_dest_set(), udma_mram_tx_dest_set(), udma_sdio_sdio_clk_div_set(), udma_sdio_sdio_cmd_arg_set(), udma_sdio_sdio_cmd_op_set(), udma_sdio_sdio_data_setup_set(), udma_sdio_sdio_rsp0_set(), udma_sdio_sdio_rsp1_set(), udma_sdio_sdio_rsp2_set(), udma_sdio_sdio_rsp3_set(), udma_sdio_sdio_rx_cfg_set(), udma_sdio_sdio_rx_initcfg_set(), udma_sdio_sdio_rx_saddr_set(), udma_sdio_sdio_rx_size_set(), udma_sdio_sdio_start_set(), udma_sdio_sdio_status_set(), udma_sdio_sdio_tx_cfg_set(), udma_sdio_sdio_tx_initcfg_set(), udma_sdio_sdio_tx_saddr_set(), udma_sdio_sdio_tx_size_set(), udma_spim_cmd_dest_set(), udma_spim_rx_dest_set(), udma_spim_status_set(), udma_spim_tx_dest_set(), udma_timestamp_reg_clk_cfg_clk_mux_en_set(), udma_timestamp_reg_clk_cfg_clk_mux_set(), udma_timestamp_reg_clk_cfg_gpio_sel_set(), udma_timestamp_reg_clk_cfg_prescaler_set(), udma_timestamp_reg_clk_cfg_pwm_sel_set(), udma_timestamp_reg_clk_cfg_set(), udma_timestamp_reg_cmd_cnt_clr_set(), udma_timestamp_reg_cmd_cnt_stop_set(), udma_timestamp_reg_cmd_set(), udma_timestamp_reg_dest_rx_dest_set(), udma_timestamp_reg_dest_set(), udma_timestamp_reg_setup_ch0_1_input_en_ch0_set(), udma_timestamp_reg_setup_ch0_1_input_en_ch1_set(), udma_timestamp_reg_setup_ch0_1_input_sel_ch0_set(), udma_timestamp_reg_setup_ch0_1_input_sel_ch1_set(), udma_timestamp_reg_setup_ch0_1_input_type_ch0_set(), udma_timestamp_reg_setup_ch0_1_input_type_ch1_set(), udma_timestamp_reg_setup_ch0_1_set(), udma_timestamp_reg_setup_ch2_3_input_en_ch2_set(), udma_timestamp_reg_setup_ch2_3_input_en_ch3_set(), udma_timestamp_reg_setup_ch2_3_input_sel_ch2_set(), udma_timestamp_reg_setup_ch2_3_input_sel_ch3_set(), udma_timestamp_reg_setup_ch2_3_input_type_ch2_set(), udma_timestamp_reg_setup_ch2_3_input_type_ch3_set(), udma_timestamp_reg_setup_ch2_3_set(), udma_timestamp_reg_setup_ch4_5_input_en_ch4_set(), udma_timestamp_reg_setup_ch4_5_input_en_ch5_set(), udma_timestamp_reg_setup_ch4_5_input_sel_ch4_set(), udma_timestamp_reg_setup_ch4_5_input_sel_ch5_set(), udma_timestamp_reg_setup_ch4_5_input_type_ch4_set(), udma_timestamp_reg_setup_ch4_5_input_type_ch5_set(), udma_timestamp_reg_setup_ch4_5_set(), udma_timestamp_reg_setup_ch6_7_input_en_ch6_set(), udma_timestamp_reg_setup_ch6_7_input_en_ch7_set(), udma_timestamp_reg_setup_ch6_7_input_sel_ch6_set(), udma_timestamp_reg_setup_ch6_7_input_sel_ch7_set(), udma_timestamp_reg_setup_ch6_7_input_type_ch6_set(), udma_timestamp_reg_setup_ch6_7_input_type_ch7_set(), udma_timestamp_reg_setup_ch6_7_set(), udma_timestamp_reg_setup_cnt_cnt_ext_en_set(), udma_timestamp_reg_setup_cnt_cnt_ext_sel_set(), udma_timestamp_reg_setup_cnt_cnt_ext_type_set(), udma_timestamp_reg_setup_cnt_set(), udma_uart_error_set(), udma_uart_irq_en_set(), udma_uart_rx_dest_set(), udma_uart_setup_2_set(), udma_uart_setup_set(), udma_uart_status_set(), and udma_uart_tx_dest_set().
| #define GAP_WRITE_VOL | ( | base, | |
| offset, | |||
| value | |||
| ) |
|
inlinestatic |
| static unsigned int unsigned int Offset |
