Macros
#define	ARCHI_FC_CID

#define	ARCHI_HAS_FC_TCDM

#define	ARCHI_HAS_FC_ALIAS

#define	FC_TCDM_SIZE

#define	ARCHI_HAS_L2_ALIAS

#define	L2_SHARED_SIZE

#define	ROM_SIZE

#define	FLL_OFFSET

#define	GPIO_OFFSET

#define	UDMA_OFFSET

#define	APB_SOC_CTRL_OFFSET

#define	ADV_TIMER_OFFSET

#define	SOC_EU_OFFSET

#define	DLC_OFFSET

#define	RTC_BASE_OFFSET

#define	EFUSE_OFFSET

#define	ARCHI_REF_CLOCK_LOG2

#define	ARCHI_REF_CLOCK

#define	ARCHI_FLL_REF_CLOCK_LOG2

#define	ARCHI_FLL_REF_CLOCK

#define	ARCHI_FREQ_INIT

#define	ARCHI_NB_FLL

#define	FLL_SIZE_LOG2

#define	FLL_SIZE

#define	FLL_ID_PERIPH

#define	FLL_ID_FC

#define	FLL_ID_CL

#define	UDMA_HAS_SPIM

#define	UDMA_HAS_HYPER

#define	UDMA_HAS_UART

#define	UDMA_HAS_I2C

#define	UDMA_HAS_DMACPY

#define	UDMA_HAS_I2S

#define	UDMA_HAS_CPI

#define	UDMA_NB_SPIM

#define	UDMA_NB_HYPER

#define	UDMA_NB_UART

#define	UDMA_NB_I2C

#define	UDMA_NB_DMACPY

#define	UDMA_NB_I2S

#define	UDMA_NB_CPI

#define	UDMA_NB_PERIPH

#define	UDMA_PERIPH_SIZE_LOG2

#define	UDMA_PERIPH_SIZE

#define	UDMA_SPIM_ID(id)

#define	UDMA_HYPER_ID(id)

#define	UDMA_UART_ID(id)

#define	UDMA_I2C_ID(id)

#define	UDMA_DMACPY_ID(id)

#define	UDMA_I2S_ID(id)

#define	UDMA_CPI_ID(id)

#define	ARCHI_NB_PAD

#define	ARCHI_NB_GPIO

#define	ARCHI_NB_PWM

#define	ARCHI_NB_CHANNEL_PER_PWM

#define	ARCHI_HAS_CLUSTER

#define	ARCHI_CL_CID(id)

#define	ARCHI_CLUSTER_NB_PE

#define	ARCHI_CLUSTER_PE_MASK

#define	ARCHI_CLUSTER_MASTER_CORE

#define	ARCHI_CLUSTER_SYNC_BARR_ID

#define	ARCHI_CLUSTER_SIZE

#define	ARCHI_HAS_CL_L1_ALIAS

#define	CL_L1_SIZE

#define	ARCHI_HAS_CL_L1_TS

#define	ARCHI_CL_L1_TS_OFFSET

#define	CL_CTRL_OFFSET

#define	CL_TIMER_OFFSET

#define	CL_GLOB_EU_CORE_OFFSET

#define	CL_GLOB_EU_BARRIER_OFFSET

#define	CL_GLOB_EU_SW_EVENT_OFFSET

#define	CL_GLOB_EU_SOC_EVENT_OFFSET

#define	CL_GLOB_EU_DISPATCH_OFFSET

#define	CL_HWCE_OFFSET

#define	CL_ICACHE_CTRL_OFFSET

#define	CL_DMA_OFFSET

#define	CL_DEMUX_PERIPH_OFFSET

#define	CL_DEMUX_EU_CORE_OFFSET

#define	CL_DEMUX_EU_LOOP_OFFSET

#define	CL_DEMUX_EU_DISPATCH_OFFSET

#define	CL_DEMUX_EU_MUTEX_OFFSET

#define	CL_DEMUX_EU_SW_EVENT_OFFSET

#define	CL_DEMUX_EU_BARRIER_OFFSET

#define	CL_DEMUX_DMA_OFFSET

Macro Definition Documentation

#define ADV_TIMER_OFFSET

#define APB_SOC_CTRL_OFFSET

#define ARCHI_CL_CID ( id )

Referenced by __cluster_start().

#define ARCHI_CL_L1_TS_OFFSET

#define ARCHI_CLUSTER_MASTER_CORE

Referenced by __cluster_start(), pi_cl_team_fork(), pi_cl_team_prepare_fork(), and pi_cl_team_preset_fork().

#define ARCHI_CLUSTER_NB_PE

Referenced by __pi_send_task_to_cl(), and cl_pop_cluster_task().

#define ARCHI_CLUSTER_PE_MASK

Referenced by hal_cl_ctrl_fetch_enable(), hal_cl_fetch_enable(), hal_cl_icache_disable(), hal_cl_icache_flush(), and hal_cl_l1_shared_prefetch_disable().

#define ARCHI_CLUSTER_SIZE

#define ARCHI_CLUSTER_SYNC_BARR_ID

Referenced by pi_cl_team_fork(), pi_cl_team_prepare_fork(), and pi_cl_team_preset_fork().

#define ARCHI_FC_CID

#define ARCHI_FLL_REF_CLOCK

Referenced by __pi_fll_frequency_from_mult_div_get(), and pi_udma_timeout_config_set().

#define ARCHI_FLL_REF_CLOCK_LOG2

#define ARCHI_FREQ_INIT

Referenced by __pi_pmu_init(), and pi_pmu_init().

#define ARCHI_HAS_CL_L1_ALIAS

#define ARCHI_HAS_CL_L1_TS

#define ARCHI_HAS_CLUSTER

#define ARCHI_HAS_FC_ALIAS

#define ARCHI_HAS_FC_TCDM

#define ARCHI_HAS_L2_ALIAS

#define ARCHI_NB_CHANNEL_PER_PWM

Referenced by __pi_pwm_freq_cb().

#define ARCHI_NB_FLL

#define ARCHI_NB_GPIO

#define ARCHI_NB_PAD

#define ARCHI_NB_PWM

#define ARCHI_REF_CLOCK

#define ARCHI_REF_CLOCK_LOG2

#define CL_CTRL_OFFSET

#define CL_DEMUX_DMA_OFFSET

#define CL_DEMUX_EU_BARRIER_OFFSET

#define CL_DEMUX_EU_CORE_OFFSET

#define CL_DEMUX_EU_DISPATCH_OFFSET

#define CL_DEMUX_EU_LOOP_OFFSET

#define CL_DEMUX_EU_MUTEX_OFFSET

#define CL_DEMUX_EU_SW_EVENT_OFFSET

#define CL_DEMUX_PERIPH_OFFSET

#define CL_DMA_OFFSET

#define CL_GLOB_EU_BARRIER_OFFSET

#define CL_GLOB_EU_CORE_OFFSET

#define CL_GLOB_EU_DISPATCH_OFFSET

#define CL_GLOB_EU_SOC_EVENT_OFFSET

#define CL_GLOB_EU_SW_EVENT_OFFSET

#define CL_HWCE_OFFSET

#define CL_ICACHE_CTRL_OFFSET

#define CL_L1_SIZE

#define CL_TIMER_OFFSET

#define DLC_OFFSET

#define EFUSE_OFFSET

#define FC_TCDM_SIZE

#define FLL_ID_CL

Referenced by pi_freq_get(), and pi_freq_set().

#define FLL_ID_FC

Referenced by __pi_pmu_init(), pi_fll_frequency_set(), pi_freq_get(), pi_freq_set(), and pi_pmu_init().

#define FLL_ID_PERIPH

Referenced by pi_freq_get(), pi_freq_set(), and pi_pmu_init().

#define FLL_OFFSET

#define FLL_SIZE

#define FLL_SIZE_LOG2

#define GPIO_OFFSET

#define L2_SHARED_SIZE

#define ROM_SIZE

#define RTC_BASE_OFFSET

#define SOC_EU_OFFSET

#define UDMA_CPI_ID ( id )

Referenced by __pi_cpi_close(), __pi_cpi_handler(), and __pi_cpi_open().

#define UDMA_DMACPY_ID ( id )

Referenced by __pi_dmacpy_handler(), and __pi_dmacpy_open().

#define UDMA_HAS_CPI

#define UDMA_HAS_DMACPY

#define UDMA_HAS_HYPER

#define UDMA_HAS_I2C

#define UDMA_HAS_I2S

#define UDMA_HAS_SPIM

#define UDMA_HAS_UART

#define UDMA_HYPER_ID ( id )

Referenced by __pi_hyper_close(), __pi_hyper_open(), __pi_octospi_close(), __pi_octospi_open(), hyper_handler(), pi_hyper_close(), and pi_hyper_open().

#define UDMA_I2C_ID ( id )

Referenced by __pi_i2c_close(), __pi_i2c_handler(), __pi_i2c_open(), __pi_i2c_slave_close(), and __pi_i2c_slave_open().

#define UDMA_I2S_ID ( id )

Referenced by __pi_i2s_close(), __pi_i2s_handler(), and __pi_i2s_open().

#define UDMA_NB_CPI

#define UDMA_NB_DMACPY

#define UDMA_NB_HYPER

#define UDMA_NB_I2C

#define UDMA_NB_I2S

#define UDMA_NB_PERIPH

#define UDMA_NB_SPIM

#define UDMA_NB_UART

#define UDMA_OFFSET

#define UDMA_PERIPH_SIZE

#define UDMA_PERIPH_SIZE_LOG2

#define UDMA_SPIM_ID ( id )

Referenced by __pi_spi_close(), __pi_spi_open(), spim_rx_handler(), and spim_tx_handler().

#define UDMA_UART_ID ( id )

Referenced by __pi_uart_close(), __pi_uart_handler(), and __pi_uart_open().

Macros

Macro Definition Documentation