gap8/pmsis/include/pmsis/targets/periph/cluster/cluster_event_unit/cluster_event_unit_offset.h File Reference

Macros
#define	CLUSTER_DEMUX_EU_CORE_OFFSET
#define	CLUSTER_DEMUX_EU_LOOP_OFFSET
#define	CLUSTER_DEMUX_EU_DISPATCH_OFFSET
#define	CLUSTER_DEMUX_EU_MUTEX_OFFSET
#define	CLUSTER_DEMUX_EU_SW_EVENT_OFFSET
#define	CLUSTER_DEMUX_EU_BARRIER_OFFSET
#define	CL_DEMUX_EU_CORE_EVENT_MASK
#define	CL_DEMUX_EU_CORE_EVENT_MASK_AND
#define	CL_DEMUX_EU_CORE_EVENT_MASK_OR
#define	CL_DEMUX_EU_CORE_IRQ_MASK
#define	CL_DEMUX_EU_CORE_IRQ_MASK_AND
#define	CL_DEMUX_EU_CORE_IRQ_MASK_OR
#define	CL_DEMUX_EU_CORE_STATUS
#define	CL_DEMUX_EU_CORE_BUFFER
#define	CL_DEMUX_EU_CORE_BUFFER_MASKED
#define	CL_DEMUX_EU_CORE_BUFFER_IRQ_MASKED
#define	CL_DEMUX_EU_CORE_BUFFER_CLEAR
#define	CL_DEMUX_EU_CORE_SW_EVT_MASK
#define	CL_DEMUX_EU_CORE_SW_EVT_MASK_AND
#define	CL_DEMUX_EU_CORE_SW_EVT_MASK_OR
#define	CL_DEMUX_EU_CORE_EVENT_WAIT
#define	CL_DEMUX_EU_CORE_EVENT_WAIT_CLEAR
#define	CL_DEMUX_EU_CORE_SEC_IRQ_MASK
#define	CL_DEMUX_EU_CORE_SEC_IRQ_MASK_AND
#define	CL_DEMUX_EU_CORE_SEC_IRQ_MASK_OR
#define	CL_DEMUX_EU_LOOP_STATE
#define	CL_DEMUX_EU_LOOP_START
#define	CL_DEMUX_EU_LOOP_END
#define	CL_DEMUX_EU_LOOP_INCR
#define	CL_DEMUX_EU_LOOP_CHUNK
#define	CL_DEMUX_EU_LOOP_EPOCH
#define	CL_DEMUX_EU_LOOP_SINGLE
#define	CL_DEMUX_EU_DISPATCH_FIFO_ACCESS
#define	CL_DEMUX_EU_DISPATCH_TEAM_CONFIG
#define	CL_DEMUX_EU_MUTEX_MUTEX
#define	CL_DEMUX_EU_SW_EVT_TRIGGER
#define	CL_DEMUX_EU_SW_EVT_TRIGGER_WAIT
#define	CL_DEMUX_EU_SW_EVT_TRIGGER_WAIT_CLEAR
#define	CL_DEMUX_EU_HW_BARRIER_TRIGGER_MASK
#define	CL_DEMUX_EU_HW_BARRIER_STATUS
#define	CL_DEMUX_EU_HW_BARRIER_STATUS_SUMMARY
#define	CL_DEMUX_EU_HW_BARRIER_TARGET_MASK
#define	CL_DEMUX_EU_HW_BARRIER_TRIGGER
#define	CL_DEMUX_EU_HW_BARRIER_TRIGGER_SELF
#define	CL_DEMUX_EU_HW_BARRIER_TRIGGER_WAIT
#define	CL_DEMUX_EU_HW_BARRIER_TRIGGER_WAIT_CLEAR
#define	CL_DEMUX_EU_HW_BARRIER_SIZE

Macro Definition Documentation

#define CL_DEMUX_EU_CORE_BUFFER

Referenced by hal_cl_eu_evt_irq_status().

#define CL_DEMUX_EU_CORE_BUFFER_CLEAR

Referenced by hal_cl_eu_evt_clear().

#define CL_DEMUX_EU_CORE_BUFFER_IRQ_MASKED

Referenced by hal_cl_eu_irq_status().

#define CL_DEMUX_EU_CORE_BUFFER_MASKED

Referenced by hal_cl_eu_evt_status().

#define CL_DEMUX_EU_CORE_EVENT_MASK

Event_Unit Core Demux

#define CL_DEMUX_EU_CORE_EVENT_MASK_AND

Referenced by hal_cl_eu_evt_mask_clear().

#define CL_DEMUX_EU_CORE_EVENT_MASK_OR

Referenced by hal_cl_eu_evt_mask_set().

#define CL_DEMUX_EU_CORE_EVENT_WAIT

Referenced by hal_cl_eu_evt_wait().

#define CL_DEMUX_EU_CORE_EVENT_WAIT_CLEAR

Referenced by hal_cl_eu_evt_wait_and_clear().

#define CL_DEMUX_EU_CORE_IRQ_MASK

#define CL_DEMUX_EU_CORE_IRQ_MASK_AND

Referenced by hal_cl_eu_irq_mask_clear().

#define CL_DEMUX_EU_CORE_IRQ_MASK_OR

Referenced by hal_cl_eu_irq_mask_set().

#define CL_DEMUX_EU_CORE_SEC_IRQ_MASK

#define CL_DEMUX_EU_CORE_SEC_IRQ_MASK_AND

#define CL_DEMUX_EU_CORE_SEC_IRQ_MASK_OR

#define CL_DEMUX_EU_CORE_STATUS

#define CL_DEMUX_EU_CORE_SW_EVT_MASK

#define CL_DEMUX_EU_CORE_SW_EVT_MASK_AND

#define CL_DEMUX_EU_CORE_SW_EVT_MASK_OR

#define CL_DEMUX_EU_DISPATCH_FIFO_ACCESS

Event_Unit Dispatch Demux

Referenced by hal_cl_eu_dispatch_fifo_pop(), and hal_cl_eu_dispatch_fifo_push().

#define CL_DEMUX_EU_DISPATCH_TEAM_CONFIG

Referenced by hal_cl_eu_dispatch_team_config().

#define CL_DEMUX_EU_HW_BARRIER_SIZE

#define CL_DEMUX_EU_HW_BARRIER_STATUS

Referenced by hal_cl_eu_barrier_status().

#define CL_DEMUX_EU_HW_BARRIER_STATUS_SUMMARY

#define CL_DEMUX_EU_HW_BARRIER_TARGET_MASK

Referenced by hal_cl_eu_barrier_setup().

#define CL_DEMUX_EU_HW_BARRIER_TRIGGER

Referenced by hal_cl_eu_barrier_trigger().

#define CL_DEMUX_EU_HW_BARRIER_TRIGGER_MASK

Event_Unit Barrier Demux

Referenced by hal_cl_eu_barrier_setup(), and hal_cl_eu_barrier_team_get().

#define CL_DEMUX_EU_HW_BARRIER_TRIGGER_SELF

Referenced by hal_cl_eu_barrier_trigger_self().

#define CL_DEMUX_EU_HW_BARRIER_TRIGGER_WAIT

Referenced by hal_cl_eu_barrier_trigger_wait().

#define CL_DEMUX_EU_HW_BARRIER_TRIGGER_WAIT_CLEAR

Referenced by hal_cl_eu_barrier_trigger_wait_clear().

#define CL_DEMUX_EU_LOOP_CHUNK

#define CL_DEMUX_EU_LOOP_END

#define CL_DEMUX_EU_LOOP_EPOCH

#define CL_DEMUX_EU_LOOP_INCR

#define CL_DEMUX_EU_LOOP_SINGLE

#define CL_DEMUX_EU_LOOP_START

#define CL_DEMUX_EU_LOOP_STATE

Event_Unit Loop Demux

#define CL_DEMUX_EU_MUTEX_MUTEX

Event_Unit Mutex Demux

Referenced by hal_cl_eu_mutex_init(), hal_cl_eu_mutex_lock(), and hal_cl_eu_mutex_unlock().

#define CL_DEMUX_EU_SW_EVT_TRIGGER

Event_Unit SW_Events Demux

Referenced by hal_cl_eu_glob_sw_trig().

#define CL_DEMUX_EU_SW_EVT_TRIGGER_WAIT

#define CL_DEMUX_EU_SW_EVT_TRIGGER_WAIT_CLEAR

#define CLUSTER_DEMUX_EU_BARRIER_OFFSET

#define CLUSTER_DEMUX_EU_CORE_OFFSET

Event_Unit Demux offset

#define CLUSTER_DEMUX_EU_DISPATCH_OFFSET

#define CLUSTER_DEMUX_EU_LOOP_OFFSET

#define CLUSTER_DEMUX_EU_MUTEX_OFFSET

#define CLUSTER_DEMUX_EU_SW_EVENT_OFFSET