FreeRTOS port on GAP8/RISC-V
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Functions | |
static uint32_t | hal_eu_read32 (uint32_t base, uint32_t offset) |
Clock-gated load. More... | |
static void | hal_cl_eu_evt_mask_set (uint32_t mask) |
EU_Core. More... | |
static void | hal_cl_eu_evt_mask_clear (uint32_t mask) |
static void | hal_cl_eu_irq_mask_set (uint32_t mask) |
static void | hal_cl_eu_irq_mask_clear (uint32_t mask) |
static uint32_t | hal_cl_eu_evt_irq_status (void) |
Events and IRQs status. More... | |
static uint32_t | hal_cl_eu_evt_status (void) |
Event status. More... | |
static uint32_t | hal_cl_eu_irq_status (void) |
IRQs status. More... | |
static void | hal_cl_eu_evt_clear (uint32_t mask) |
Clear event status. More... | |
static uint32_t | hal_cl_eu_evt_wait (void) |
Wait and sleep. More... | |
static uint32_t | hal_cl_eu_evt_wait_and_clear (void) |
Wait and sleep. More... | |
static void | hal_cl_eu_evt_mask_wait (uint32_t event_mask) |
static void | hal_cl_eu_evt_mask_wait_clear (uint32_t event_mask) |
static void | hal_cl_eu_dispatch_fifo_push (uint32_t message) |
EU_Dispatch. More... | |
static uint32_t | hal_cl_eu_dispatch_fifo_pop (void) |
static void | hal_cl_eu_dispatch_team_config (uint32_t team_mask) |
static void | hal_cl_eu_mutex_init (uint32_t mutex_id) |
EU_HW_Mutex. More... | |
static void | hal_cl_eu_mutex_lock (uint32_t mutex_id) |
static void | hal_cl_eu_mutex_unlock (uint32_t mutex_id) |
static void | hal_cl_eu_glob_sw_trig (uint32_t cluster_id, uint32_t sw_event, uint32_t core_mask) |
EU_SW_Trig. More... | |
static void | hal_cl_eu_barrier_setup (uint32_t barrier_id, uint32_t core_mask) |
EU_HW_Barrier. More... | |
static uint32_t | hal_cl_eu_barrier_team_get (uint32_t barrier_id) |
static uint32_t | hal_cl_eu_barrier_status (uint32_t barrier_id) |
static void | hal_cl_eu_barrier_trigger (uint32_t barrier_id, uint32_t core_mask) |
static uint32_t | hal_cl_eu_barrier_trigger_self (uint32_t barrier_id) |
static uint32_t | hal_cl_eu_barrier_trigger_wait (uint32_t barrier_id) |
static uint32_t | hal_cl_eu_barrier_trigger_wait_clear (uint32_t barrier_id) |
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Functions to use to config/access cluster barrier.
Setup a barrier for a mask of cores. Get current status of barrier. Trigger barrier with a mask. Trigger barrier with core_id of core calling func. Trigger barrier with core_id of core calling func and sleep. Trigger barrier with core_id of core calling func and sleep and clear buffer.
References CL_DEMUX_EU_HW_BARRIER_TARGET_MASK, CL_DEMUX_EU_HW_BARRIER_TRIGGER_MASK, and hal_write32().
Referenced by pi_cl_team_fork(), and pi_cl_team_prepare_fork().
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References CL_DEMUX_EU_HW_BARRIER_STATUS, and hal_eu_read32().
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References CL_DEMUX_EU_HW_BARRIER_TRIGGER_MASK, and hal_read32().
Referenced by pi_cl_team_nb_cores(), and pi_cl_team_preset_fork().
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References CL_DEMUX_EU_HW_BARRIER_TRIGGER, and hal_write32().
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References CL_DEMUX_EU_HW_BARRIER_TRIGGER_SELF, and hal_eu_read32().
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References CL_DEMUX_EU_HW_BARRIER_TRIGGER_WAIT, and hal_eu_read32().
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References CL_DEMUX_EU_HW_BARRIER_TRIGGER_WAIT_CLEAR, and hal_eu_read32().
Referenced by pi_cl_team_barrier(), pi_cl_team_fork(), and pi_cl_team_preset_fork().
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References CL_DEMUX_EU_DISPATCH_FIFO_ACCESS, and hal_read32().
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Functions to dispatch messages/info to cores. Used by cluster core master to send cluster task info to slaves.
Push a message to slave cores. Pop a message, by slave cores. Configure cores that will receive messages.
References CL_DEMUX_EU_DISPATCH_FIFO_ACCESS, and hal_write32().
Referenced by pi_cl_team_fork(), and pi_cl_team_preset_fork().
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References CL_DEMUX_EU_DISPATCH_TEAM_CONFIG, and hal_write32().
Referenced by pi_cl_team_fork(), and pi_cl_team_prepare_fork().
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Clears the corresponding buffered bit in eu_core_buffer to 0. If the corresponding event line is active in the same cycle where the clear operation gets effective, the bit still does get cleared to 0.
References CL_DEMUX_EU_CORE_BUFFER_CLEAR, and hal_write32().
Referenced by hal_cl_eu_evt_mask_wait_clear().
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This register contains one bit per event, 1 means the event is set. This register is a buffer, which means if an event is received while its bit is already at 1, the event is somehow lost as the bit stays at 1. Thus events should be used as Linux signals.
References CL_DEMUX_EU_CORE_BUFFER, and hal_eu_read32().
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References CL_DEMUX_EU_CORE_EVENT_MASK_AND, and hal_write32().
Referenced by hal_cl_eu_evt_mask_wait(), and hal_cl_eu_evt_mask_wait_clear().
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Function to acces cluster event unit.
Set event mask . Clear event mask. Set IRQ mask. Clear IRQ mask. Wait for event, used for synchro. Wait for event and clear, used for synchro.
References CL_DEMUX_EU_CORE_EVENT_MASK_OR, and hal_write32().
Referenced by cl_cluster_exec_loop(), hal_cl_eu_evt_mask_wait(), and hal_cl_eu_evt_mask_wait_clear().
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References hal_cl_eu_evt_mask_clear(), hal_cl_eu_evt_mask_set(), and hal_cl_eu_evt_wait().
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Same as hal_cl_eu_evt_irq_status(), with the content ANDed with current event mask, so that only relevant events (that can wake-up the core) are shown. It can for example be used to know which events must be handled after a core wake-up as the core has been waken-up due to one of them.
References CL_DEMUX_EU_CORE_BUFFER_MASKED, and hal_eu_read32().
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Reading this register will stop the clock of the core until at least one event with the corresponding mask bit set to 1 occurs. The read content of this register is identical to that of eu_core_buffer_masked.
References CL_DEMUX_EU_CORE_EVENT_WAIT, and hal_eu_read32().
Referenced by hal_cl_eu_evt_mask_wait(), and hal_cl_eu_evt_mask_wait_clear().
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Reading from this register has the same effect as reading from eu_core_event_wait. In addition, the bits of eu_core_buffer that are set to 1 in eu_core_mask will be cleared to 0 after the read.
References CL_DEMUX_EU_CORE_EVENT_WAIT_CLEAR, and hal_eu_read32().
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Functions to use to trigger a SW IRQ from FC to cluster.
Trigger a SW IRQ to cores of a given cluster.
References CL_DEMUX_EU_SW_EVT_TRIGGER, hal_write32(), and offset.
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References CL_DEMUX_EU_CORE_IRQ_MASK_AND, and hal_write32().
Referenced by __pi_cl_dma_decompressor_shutdown().
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References CL_DEMUX_EU_CORE_IRQ_MASK_OR, and hal_write32().
Referenced by __pi_cl_dma_decompressor_wakeup().
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Same as hal_cl_eu_evt_irq_status(), with the content ANDed with current event IRQ mask, so that only relevant events (that can wake-up the core) are shown. It can for example be used to know which events must be handled after a core wake-up as the core has been waken-up due to one of them.
References CL_DEMUX_EU_CORE_BUFFER_IRQ_MASKED, and hal_eu_read32().
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Functions to lock/unlock cluster HW mutex.
Initialize mutex. Lock mutex. Unlock mutex.
References CL_DEMUX_EU_MUTEX_MUTEX, hal_compiler_barrier(), and hal_write32().
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References CL_DEMUX_EU_MUTEX_MUTEX, and hal_eu_read32().
Referenced by pi_cl_team_critical_enter().
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References CL_DEMUX_EU_MUTEX_MUTEX, hal_compiler_barrier(), and hal_write32().
Referenced by pi_cl_team_critical_exit().
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On architectures that support it, this executes the special p.elw instruction which is used to put the core in idle mode until it receives an event. On other architectures, it executes a classic read which has the same effect but does not handle correctly interrupts while the core is sleeping.
base | Base address of the event unit. |
offset | Offset in the event unit where to load from. Depending on this offset, this will trigger different behaviors (barrier, wait, wait&clear, etc). |
References hal_compiler_barrier(), and Catch::Generators::value().
Referenced by hal_cl_eu_barrier_status(), hal_cl_eu_barrier_trigger_self(), hal_cl_eu_barrier_trigger_wait(), hal_cl_eu_barrier_trigger_wait_clear(), hal_cl_eu_evt_irq_status(), hal_cl_eu_evt_status(), hal_cl_eu_evt_wait(), hal_cl_eu_evt_wait_and_clear(), hal_cl_eu_irq_status(), and hal_cl_eu_mutex_lock().