udma_timestamp_regfields.h File Reference

Macros
#define	UDMA_TIMESTAMP_REG_DEST_RX_DEST_BIT
#define	UDMA_TIMESTAMP_REG_DEST_RX_DEST_WIDTH
#define	UDMA_TIMESTAMP_REG_DEST_RX_DEST_MASK
#define	UDMA_TIMESTAMP_REG_DEST_RX_DEST_RESET
#define	UDMA_TIMESTAMP_REG_CMD_CNT_CLR_BIT
#define	UDMA_TIMESTAMP_REG_CMD_CNT_CLR_WIDTH
#define	UDMA_TIMESTAMP_REG_CMD_CNT_CLR_MASK
#define	UDMA_TIMESTAMP_REG_CMD_CNT_CLR_RESET
#define	UDMA_TIMESTAMP_REG_CMD_CNT_STOP_BIT
#define	UDMA_TIMESTAMP_REG_CMD_CNT_STOP_WIDTH
#define	UDMA_TIMESTAMP_REG_CMD_CNT_STOP_MASK
#define	UDMA_TIMESTAMP_REG_CMD_CNT_STOP_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_SEL_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_SEL_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_SEL_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_SEL_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_TYPE_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_TYPE_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_TYPE_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_TYPE_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_EN_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_EN_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_EN_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_EN_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH0_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH0_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH0_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH0_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH0_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH0_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH0_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH0_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH0_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH0_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH0_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH0_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH1_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH1_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH1_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH1_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH1_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH1_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH1_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH1_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH1_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH1_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH1_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH1_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH2_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH2_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH2_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH2_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH2_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH2_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH2_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH2_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH2_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH2_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH2_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH2_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH3_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH3_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH3_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH3_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH3_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH3_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH3_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH3_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH3_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH3_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH3_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH3_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH4_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH4_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH4_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH4_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH4_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH4_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH4_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH4_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH4_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH4_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH4_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH4_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH5_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH5_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH5_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH5_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH5_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH5_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH5_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH5_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH5_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH5_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH5_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH5_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH6_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH6_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH6_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH6_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH6_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH6_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH6_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH6_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH6_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH6_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH6_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH6_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH7_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH7_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH7_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH7_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH7_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH7_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH7_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH7_RESET
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH7_BIT
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH7_WIDTH
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH7_MASK
#define	UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH7_RESET
#define	UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_BIT
#define	UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_WIDTH
#define	UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_MASK
#define	UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_RESET
#define	UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_EN_BIT
#define	UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_EN_WIDTH
#define	UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_EN_MASK
#define	UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_EN_RESET
#define	UDMA_TIMESTAMP_REG_CLK_CFG_PWM_SEL_BIT
#define	UDMA_TIMESTAMP_REG_CLK_CFG_PWM_SEL_WIDTH
#define	UDMA_TIMESTAMP_REG_CLK_CFG_PWM_SEL_MASK
#define	UDMA_TIMESTAMP_REG_CLK_CFG_PWM_SEL_RESET
#define	UDMA_TIMESTAMP_REG_CLK_CFG_GPIO_SEL_BIT
#define	UDMA_TIMESTAMP_REG_CLK_CFG_GPIO_SEL_WIDTH
#define	UDMA_TIMESTAMP_REG_CLK_CFG_GPIO_SEL_MASK
#define	UDMA_TIMESTAMP_REG_CLK_CFG_GPIO_SEL_RESET
#define	UDMA_TIMESTAMP_REG_CLK_CFG_PRESCALER_BIT
#define	UDMA_TIMESTAMP_REG_CLK_CFG_PRESCALER_WIDTH
#define	UDMA_TIMESTAMP_REG_CLK_CFG_PRESCALER_MASK
#define	UDMA_TIMESTAMP_REG_CLK_CFG_PRESCALER_RESET

Macro Definition Documentation

#define UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_BIT

#define UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_EN_BIT

#define UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_EN_MASK

#define UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_EN_RESET

#define UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_EN_WIDTH

#define UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_MASK

#define UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_RESET

#define UDMA_TIMESTAMP_REG_CLK_CFG_CLK_MUX_WIDTH

#define UDMA_TIMESTAMP_REG_CLK_CFG_GPIO_SEL_BIT

#define UDMA_TIMESTAMP_REG_CLK_CFG_GPIO_SEL_MASK

#define UDMA_TIMESTAMP_REG_CLK_CFG_GPIO_SEL_RESET

#define UDMA_TIMESTAMP_REG_CLK_CFG_GPIO_SEL_WIDTH

#define UDMA_TIMESTAMP_REG_CLK_CFG_PRESCALER_BIT

#define UDMA_TIMESTAMP_REG_CLK_CFG_PRESCALER_MASK

#define UDMA_TIMESTAMP_REG_CLK_CFG_PRESCALER_RESET

#define UDMA_TIMESTAMP_REG_CLK_CFG_PRESCALER_WIDTH

#define UDMA_TIMESTAMP_REG_CLK_CFG_PWM_SEL_BIT

#define UDMA_TIMESTAMP_REG_CLK_CFG_PWM_SEL_MASK

#define UDMA_TIMESTAMP_REG_CLK_CFG_PWM_SEL_RESET

#define UDMA_TIMESTAMP_REG_CLK_CFG_PWM_SEL_WIDTH

#define UDMA_TIMESTAMP_REG_CMD_CNT_CLR_BIT

#define UDMA_TIMESTAMP_REG_CMD_CNT_CLR_MASK

#define UDMA_TIMESTAMP_REG_CMD_CNT_CLR_RESET

#define UDMA_TIMESTAMP_REG_CMD_CNT_CLR_WIDTH

#define UDMA_TIMESTAMP_REG_CMD_CNT_STOP_BIT

#define UDMA_TIMESTAMP_REG_CMD_CNT_STOP_MASK

#define UDMA_TIMESTAMP_REG_CMD_CNT_STOP_RESET

#define UDMA_TIMESTAMP_REG_CMD_CNT_STOP_WIDTH

#define UDMA_TIMESTAMP_REG_DEST_RX_DEST_BIT

#define UDMA_TIMESTAMP_REG_DEST_RX_DEST_MASK

#define UDMA_TIMESTAMP_REG_DEST_RX_DEST_RESET

#define UDMA_TIMESTAMP_REG_DEST_RX_DEST_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH0_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH0_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH0_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH0_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH1_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH1_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH1_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_EN_CH1_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH0_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH0_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH0_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH0_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH1_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH1_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH1_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_SEL_CH1_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH0_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH0_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH0_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH0_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH1_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH1_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH1_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH0_1_INPUT_TYPE_CH1_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH2_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH2_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH2_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH2_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH3_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH3_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH3_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_EN_CH3_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH2_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH2_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH2_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH2_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH3_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH3_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH3_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_SEL_CH3_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH2_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH2_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH2_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH2_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH3_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH3_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH3_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH2_3_INPUT_TYPE_CH3_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH4_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH4_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH4_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH4_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH5_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH5_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH5_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_EN_CH5_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH4_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH4_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH4_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH4_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH5_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH5_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH5_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_SEL_CH5_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH4_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH4_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH4_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH4_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH5_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH5_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH5_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH4_5_INPUT_TYPE_CH5_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH6_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH6_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH6_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH6_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH7_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH7_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH7_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_EN_CH7_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH6_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH6_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH6_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH6_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH7_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH7_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH7_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_SEL_CH7_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH6_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH6_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH6_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH6_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH7_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH7_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH7_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CH6_7_INPUT_TYPE_CH7_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_EN_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_EN_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_EN_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_EN_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_SEL_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_SEL_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_SEL_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_SEL_WIDTH

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_TYPE_BIT

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_TYPE_MASK

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_TYPE_RESET

#define UDMA_TIMESTAMP_REG_SETUP_CNT_CNT_EXT_TYPE_WIDTH