FreeRTOS port on GAP8/RISC-V
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#define UDMA_I2S_CLKCFG_SETUP_CLK_DIV_BIT |
#define UDMA_I2S_CLKCFG_SETUP_CLK_DIV_MASK |
#define UDMA_I2S_CLKCFG_SETUP_CLK_DIV_RESET |
#define UDMA_I2S_CLKCFG_SETUP_CLK_DIV_WIDTH |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EDGE_BIT |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EDGE_MASK |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EDGE_RESET |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EDGE_WIDTH |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EN_BIT |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EN_MASK |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EN_RESET |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EN_WIDTH |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EXT_SRC_BIT |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EXT_SRC_MASK |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EXT_SRC_RESET |
#define UDMA_I2S_CLKCFG_SETUP_CLK_EXT_SRC_WIDTH |
#define UDMA_I2S_CLKCFG_SETUP_CLK_SRC_BIT |
#define UDMA_I2S_CLKCFG_SETUP_CLK_SRC_MASK |
#define UDMA_I2S_CLKCFG_SETUP_CLK_SRC_RESET |
#define UDMA_I2S_CLKCFG_SETUP_CLK_SRC_WIDTH |
#define UDMA_I2S_CLKCFG_SETUP_WS_EDGE_BIT |
#define UDMA_I2S_CLKCFG_SETUP_WS_EDGE_MASK |
#define UDMA_I2S_CLKCFG_SETUP_WS_EDGE_RESET |
#define UDMA_I2S_CLKCFG_SETUP_WS_EDGE_WIDTH |
#define UDMA_I2S_CLKCFG_SETUP_WS_EXT_SRC_BIT |
#define UDMA_I2S_CLKCFG_SETUP_WS_EXT_SRC_MASK |
#define UDMA_I2S_CLKCFG_SETUP_WS_EXT_SRC_RESET |
#define UDMA_I2S_CLKCFG_SETUP_WS_EXT_SRC_WIDTH |
#define UDMA_I2S_CLKCFG_SETUP_WS_SRC_BIT |
#define UDMA_I2S_CLKCFG_SETUP_WS_SRC_MASK |
#define UDMA_I2S_CLKCFG_SETUP_WS_SRC_RESET |
#define UDMA_I2S_CLKCFG_SETUP_WS_SRC_WIDTH |
#define UDMA_I2S_CLKCFG_SETUP_WS_TYPE_BIT |
#define UDMA_I2S_CLKCFG_SETUP_WS_TYPE_MASK |
#define UDMA_I2S_CLKCFG_SETUP_WS_TYPE_RESET |
#define UDMA_I2S_CLKCFG_SETUP_WS_TYPE_WIDTH |
#define UDMA_I2S_GLB_SETUP_FRAME_LENGTH_BIT |
#define UDMA_I2S_GLB_SETUP_FRAME_LENGTH_MASK |
#define UDMA_I2S_GLB_SETUP_FRAME_LENGTH_RESET |
#define UDMA_I2S_GLB_SETUP_FRAME_LENGTH_WIDTH |
#define UDMA_I2S_GLB_SETUP_FULL_DUPLEX_EN_BIT |
#define UDMA_I2S_GLB_SETUP_FULL_DUPLEX_EN_MASK |
#define UDMA_I2S_GLB_SETUP_FULL_DUPLEX_EN_RESET |
#define UDMA_I2S_GLB_SETUP_FULL_DUPLEX_EN_WIDTH |
#define UDMA_I2S_GLB_SETUP_GLOBAL_EN_BIT |
#define UDMA_I2S_GLB_SETUP_GLOBAL_EN_MASK |
#define UDMA_I2S_GLB_SETUP_GLOBAL_EN_RESET |
#define UDMA_I2S_GLB_SETUP_GLOBAL_EN_WIDTH |
#define UDMA_I2S_GLB_SETUP_PDM_2CH_BIT |
#define UDMA_I2S_GLB_SETUP_PDM_2CH_MASK |
#define UDMA_I2S_GLB_SETUP_PDM_2CH_RESET |
#define UDMA_I2S_GLB_SETUP_PDM_2CH_WIDTH |
#define UDMA_I2S_GLB_SETUP_PDM_EN_BIT |
#define UDMA_I2S_GLB_SETUP_PDM_EN_MASK |
#define UDMA_I2S_GLB_SETUP_PDM_EN_RESET |
#define UDMA_I2S_GLB_SETUP_PDM_EN_WIDTH |
#define UDMA_I2S_GLB_SETUP_SLOT_WIDTH_BIT |
#define UDMA_I2S_GLB_SETUP_SLOT_WIDTH_MASK |
#define UDMA_I2S_GLB_SETUP_SLOT_WIDTH_RESET |
#define UDMA_I2S_GLB_SETUP_SLOT_WIDTH_WIDTH |
#define UDMA_I2S_GLB_SETUP_WS_DELAY_BIT |
#define UDMA_I2S_GLB_SETUP_WS_DELAY_MASK |
#define UDMA_I2S_GLB_SETUP_WS_DELAY_RESET |
#define UDMA_I2S_GLB_SETUP_WS_DELAY_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_0_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_0_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_0_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_0_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_0_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_0_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_0_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_0_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_0_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_0_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_0_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_0_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_0_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_0_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_0_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_0_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_0_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_0_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_0_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_0_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_0_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_0_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_0_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_0_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_0_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_0_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_0_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_0_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_0_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_0_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_0_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_0_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_0_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_0_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_0_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_0_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_0_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_0_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_0_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_0_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_10_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_10_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_10_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_10_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_10_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_10_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_10_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_10_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_10_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_10_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_10_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_10_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_10_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_10_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_10_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_10_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_10_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_10_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_10_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_10_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_10_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_10_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_10_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_10_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_10_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_10_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_10_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_10_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_10_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_10_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_10_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_10_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_10_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_10_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_10_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_10_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_10_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_10_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_10_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_10_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_11_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_11_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_11_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_11_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_11_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_11_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_11_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_11_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_11_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_11_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_11_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_11_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_11_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_11_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_11_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_11_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_11_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_11_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_11_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_11_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_11_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_11_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_11_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_11_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_11_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_11_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_11_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_11_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_11_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_11_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_11_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_11_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_11_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_11_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_11_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_11_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_11_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_11_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_11_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_11_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_12_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_12_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_12_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_12_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_12_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_12_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_12_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_12_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_12_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_12_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_12_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_12_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_12_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_12_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_12_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_12_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_12_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_12_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_12_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_12_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_12_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_12_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_12_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_12_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_12_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_12_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_12_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_12_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_12_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_12_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_12_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_12_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_12_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_12_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_12_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_12_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_12_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_12_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_12_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_12_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_13_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_13_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_13_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_13_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_13_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_13_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_13_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_13_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_13_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_13_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_13_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_13_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_13_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_13_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_13_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_13_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_13_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_13_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_13_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_13_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_13_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_13_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_13_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_13_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_13_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_13_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_13_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_13_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_13_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_13_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_13_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_13_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_13_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_13_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_13_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_13_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_13_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_13_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_13_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_13_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_14_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_14_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_14_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_14_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_14_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_14_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_14_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_14_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_14_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_14_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_14_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_14_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_14_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_14_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_14_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_14_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_14_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_14_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_14_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_14_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_14_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_14_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_14_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_14_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_14_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_14_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_14_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_14_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_14_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_14_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_14_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_14_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_14_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_14_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_14_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_14_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_14_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_14_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_14_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_14_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_15_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_15_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_15_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_15_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_15_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_15_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_15_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_15_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_15_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_15_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_15_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_15_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_15_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_15_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_15_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_15_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_15_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_15_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_15_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_15_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_15_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_15_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_15_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_15_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_15_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_15_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_15_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_15_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_15_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_15_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_15_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_15_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_15_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_15_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_15_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_15_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_15_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_15_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_15_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_15_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_1_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_1_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_1_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_1_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_1_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_1_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_1_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_1_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_1_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_1_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_1_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_1_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_1_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_1_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_1_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_1_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_1_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_1_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_1_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_1_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_1_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_1_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_1_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_1_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_1_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_1_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_1_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_1_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_1_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_1_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_1_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_1_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_1_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_1_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_1_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_1_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_1_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_1_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_1_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_1_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_2_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_2_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_2_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_2_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_2_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_2_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_2_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_2_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_2_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_2_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_2_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_2_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_2_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_2_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_2_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_2_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_2_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_2_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_2_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_2_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_2_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_2_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_2_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_2_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_2_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_2_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_2_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_2_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_2_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_2_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_2_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_2_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_2_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_2_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_2_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_2_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_2_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_2_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_2_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_2_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_3_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_3_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_3_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_3_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_3_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_3_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_3_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_3_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_3_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_3_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_3_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_3_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_3_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_3_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_3_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_3_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_3_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_3_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_3_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_3_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_3_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_3_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_3_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_3_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_3_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_3_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_3_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_3_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_3_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_3_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_3_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_3_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_3_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_3_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_3_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_3_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_3_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_3_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_3_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_3_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_4_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_4_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_4_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_4_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_4_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_4_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_4_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_4_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_4_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_4_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_4_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_4_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_4_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_4_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_4_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_4_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_4_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_4_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_4_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_4_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_4_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_4_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_4_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_4_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_4_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_4_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_4_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_4_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_4_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_4_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_4_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_4_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_4_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_4_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_4_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_4_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_4_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_4_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_4_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_4_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_5_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_5_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_5_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_5_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_5_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_5_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_5_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_5_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_5_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_5_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_5_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_5_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_5_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_5_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_5_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_5_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_5_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_5_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_5_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_5_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_5_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_5_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_5_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_5_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_5_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_5_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_5_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_5_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_5_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_5_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_5_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_5_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_5_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_5_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_5_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_5_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_5_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_5_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_5_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_5_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_6_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_6_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_6_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_6_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_6_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_6_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_6_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_6_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_6_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_6_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_6_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_6_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_6_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_6_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_6_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_6_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_6_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_6_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_6_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_6_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_6_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_6_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_6_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_6_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_6_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_6_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_6_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_6_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_6_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_6_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_6_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_6_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_6_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_6_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_6_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_6_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_6_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_6_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_6_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_6_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_7_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_7_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_7_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_7_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_7_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_7_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_7_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_7_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_7_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_7_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_7_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_7_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_7_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_7_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_7_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_7_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_7_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_7_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_7_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_7_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_7_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_7_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_7_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_7_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_7_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_7_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_7_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_7_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_7_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_7_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_7_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_7_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_7_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_7_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_7_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_7_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_7_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_7_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_7_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_7_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_8_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_8_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_8_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_8_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_8_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_8_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_8_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_8_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_8_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_8_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_8_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_8_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_8_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_8_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_8_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_8_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_8_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_8_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_8_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_8_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_8_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_8_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_8_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_8_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_8_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_8_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_8_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_8_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_8_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_8_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_8_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_8_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_8_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_8_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_8_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_8_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_8_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_8_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_8_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_8_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_BYP_BIT |
#define UDMA_I2S_SLOT_CFG_9_BYP_MASK |
#define UDMA_I2S_SLOT_CFG_9_BYP_RESET |
#define UDMA_I2S_SLOT_CFG_9_BYP_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_ID_RX_BIT |
#define UDMA_I2S_SLOT_CFG_9_ID_RX_MASK |
#define UDMA_I2S_SLOT_CFG_9_ID_RX_RESET |
#define UDMA_I2S_SLOT_CFG_9_ID_RX_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_RX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_9_RX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_9_RX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_9_RX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_RX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_9_RX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_9_RX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_9_RX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_RX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_9_RX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_9_RX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_9_RX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_RX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_9_RX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_9_RX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_9_RX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_RX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_9_RX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_9_RX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_9_RX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_TX_DSIZE_BIT |
#define UDMA_I2S_SLOT_CFG_9_TX_DSIZE_MASK |
#define UDMA_I2S_SLOT_CFG_9_TX_DSIZE_RESET |
#define UDMA_I2S_SLOT_CFG_9_TX_DSIZE_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_TX_EN_BIT |
#define UDMA_I2S_SLOT_CFG_9_TX_EN_MASK |
#define UDMA_I2S_SLOT_CFG_9_TX_EN_RESET |
#define UDMA_I2S_SLOT_CFG_9_TX_EN_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_TX_ID_BIT |
#define UDMA_I2S_SLOT_CFG_9_TX_ID_MASK |
#define UDMA_I2S_SLOT_CFG_9_TX_ID_RESET |
#define UDMA_I2S_SLOT_CFG_9_TX_ID_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_TX_LEFT_ALIGN_BIT |
#define UDMA_I2S_SLOT_CFG_9_TX_LEFT_ALIGN_MASK |
#define UDMA_I2S_SLOT_CFG_9_TX_LEFT_ALIGN_RESET |
#define UDMA_I2S_SLOT_CFG_9_TX_LEFT_ALIGN_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_TX_MSB_FIRST_BIT |
#define UDMA_I2S_SLOT_CFG_9_TX_MSB_FIRST_MASK |
#define UDMA_I2S_SLOT_CFG_9_TX_MSB_FIRST_RESET |
#define UDMA_I2S_SLOT_CFG_9_TX_MSB_FIRST_WIDTH |
#define UDMA_I2S_SLOT_CFG_9_TX_SIGN_BIT |
#define UDMA_I2S_SLOT_CFG_9_TX_SIGN_MASK |
#define UDMA_I2S_SLOT_CFG_9_TX_SIGN_RESET |
#define UDMA_I2S_SLOT_CFG_9_TX_SIGN_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_0_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_0_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_0_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_0_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_10_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_10_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_10_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_10_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_11_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_11_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_11_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_11_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_12_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_12_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_12_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_12_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_13_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_13_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_13_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_13_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_14_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_14_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_14_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_14_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_15_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_15_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_15_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_15_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_1_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_1_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_1_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_1_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_2_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_2_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_2_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_2_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_3_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_3_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_3_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_3_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_4_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_4_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_4_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_4_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_5_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_5_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_5_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_5_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_6_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_6_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_6_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_6_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_7_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_7_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_7_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_7_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_8_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_8_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_8_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_8_WIDTH |
#define UDMA_I2S_SLOT_EN_SLOT_EN_9_BIT |
#define UDMA_I2S_SLOT_EN_SLOT_EN_9_MASK |
#define UDMA_I2S_SLOT_EN_SLOT_EN_9_RESET |
#define UDMA_I2S_SLOT_EN_SLOT_EN_9_WIDTH |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_RX_0_BIT |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_RX_0_MASK |
Referenced by hal_udma_i2s_word_size_rx_set().
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_RX_0_RESET |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_RX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_RX_1_BIT |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_RX_1_MASK |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_RX_1_RESET |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_RX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_TX_0_BIT |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_TX_0_MASK |
Referenced by hal_udma_i2s_word_size_tx_set().
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_TX_0_RESET |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_TX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_TX_1_BIT |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_TX_1_MASK |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_TX_1_RESET |
#define UDMA_I2S_WORD_SIZE_0_1_WORD_SIZE_TX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_RX_0_BIT |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_RX_0_MASK |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_RX_0_RESET |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_RX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_RX_1_BIT |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_RX_1_MASK |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_RX_1_RESET |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_RX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_TX_0_BIT |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_TX_0_MASK |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_TX_0_RESET |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_TX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_TX_1_BIT |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_TX_1_MASK |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_TX_1_RESET |
#define UDMA_I2S_WORD_SIZE_10_11_WORD_SIZE_TX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_RX_0_BIT |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_RX_0_MASK |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_RX_0_RESET |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_RX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_RX_1_BIT |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_RX_1_MASK |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_RX_1_RESET |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_RX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_TX_0_BIT |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_TX_0_MASK |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_TX_0_RESET |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_TX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_TX_1_BIT |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_TX_1_MASK |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_TX_1_RESET |
#define UDMA_I2S_WORD_SIZE_12_13_WORD_SIZE_TX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_RX_0_BIT |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_RX_0_MASK |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_RX_0_RESET |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_RX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_RX_1_BIT |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_RX_1_MASK |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_RX_1_RESET |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_RX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_TX_0_BIT |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_TX_0_MASK |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_TX_0_RESET |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_TX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_TX_1_BIT |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_TX_1_MASK |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_TX_1_RESET |
#define UDMA_I2S_WORD_SIZE_14_15_WORD_SIZE_TX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_RX_0_BIT |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_RX_0_MASK |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_RX_0_RESET |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_RX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_RX_1_BIT |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_RX_1_MASK |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_RX_1_RESET |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_RX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_TX_0_BIT |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_TX_0_MASK |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_TX_0_RESET |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_TX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_TX_1_BIT |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_TX_1_MASK |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_TX_1_RESET |
#define UDMA_I2S_WORD_SIZE_2_3_WORD_SIZE_TX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_RX_0_BIT |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_RX_0_MASK |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_RX_0_RESET |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_RX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_RX_1_BIT |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_RX_1_MASK |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_RX_1_RESET |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_RX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_TX_0_BIT |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_TX_0_MASK |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_TX_0_RESET |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_TX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_TX_1_BIT |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_TX_1_MASK |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_TX_1_RESET |
#define UDMA_I2S_WORD_SIZE_4_5_WORD_SIZE_TX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_RX_0_BIT |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_RX_0_MASK |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_RX_0_RESET |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_RX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_RX_1_BIT |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_RX_1_MASK |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_RX_1_RESET |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_RX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_TX_0_BIT |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_TX_0_MASK |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_TX_0_RESET |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_TX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_TX_1_BIT |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_TX_1_MASK |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_TX_1_RESET |
#define UDMA_I2S_WORD_SIZE_6_7_WORD_SIZE_TX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_RX_0_BIT |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_RX_0_MASK |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_RX_0_RESET |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_RX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_RX_1_BIT |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_RX_1_MASK |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_RX_1_RESET |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_RX_1_WIDTH |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_TX_0_BIT |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_TX_0_MASK |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_TX_0_RESET |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_TX_0_WIDTH |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_TX_1_BIT |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_TX_1_MASK |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_TX_1_RESET |
#define UDMA_I2S_WORD_SIZE_8_9_WORD_SIZE_TX_1_WIDTH |