udma_i2c_regfields.h File Reference

Macros
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_RCV_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_RCV_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_RCV_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_RCV_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_SND_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_SND_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_SND_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_SND_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_RCV_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_RCV_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_RCV_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_RCV_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_SND_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_SND_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_SND_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_SND_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_ARLO_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_ARLO_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_ARLO_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_ARLO_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_FRAMING_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_FRAMING_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_FRAMING_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_FRAMING_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_UNLOCK_EVENT_O_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_UNLOCK_EVENT_O_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_UNLOCK_EVENT_O_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_UNLOCK_EVENT_O_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_PURGE_EVENT_O_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_PURGE_EVENT_O_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_PURGE_EVENT_O_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_PURGE_EVENT_O_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_NACK_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_NACK_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_NACK_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_NACK_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_ARLO_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_ARLO_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_ARLO_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_ARLO_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_FRAMING_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_FRAMING_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_FRAMING_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_FRAMING_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_COMMAND_EVENT_I_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_COMMAND_EVENT_I_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_COMMAND_EVENT_I_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_COMMAND_EVENT_I_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_UNLOCK_EVENT_O_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_UNLOCK_EVENT_O_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_UNLOCK_EVENT_O_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_UNLOCK_EVENT_O_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_PURGE_EVENT_O_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_PURGE_EVENT_O_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_PURGE_EVENT_O_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_PURGE_EVENT_O_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_SOFT_RESET_EVENT_O_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_SOFT_RESET_EVENT_O_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_SOFT_RESET_EVENT_O_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_SOFT_RESET_EVENT_O_IDX_RESET
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_PRESCALER_SET_DIV10_EVENT_O_IDX_BIT
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_PRESCALER_SET_DIV10_EVENT_O_IDX_WIDTH
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_PRESCALER_SET_DIV10_EVENT_O_IDX_MASK
#define	UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_PRESCALER_SET_DIV10_EVENT_O_IDX_RESET

Macro Definition Documentation

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_RCV_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_RCV_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_RCV_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_RCV_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_SND_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_SND_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_SND_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_EOF_SND_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_ARLO_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_ARLO_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_ARLO_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_ARLO_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_FRAMING_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_FRAMING_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_FRAMING_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_ERROR_FRAMING_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_PURGE_EVENT_O_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_PURGE_EVENT_O_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_PURGE_EVENT_O_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_PURGE_EVENT_O_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_RCV_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_RCV_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_RCV_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_RCV_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_SND_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_SND_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_SND_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_SOF_SND_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_UNLOCK_EVENT_O_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_UNLOCK_EVENT_O_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_UNLOCK_EVENT_O_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_FOLL_UNLOCK_EVENT_O_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_PRESCALER_SET_DIV10_EVENT_O_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_PRESCALER_SET_DIV10_EVENT_O_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_PRESCALER_SET_DIV10_EVENT_O_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_PRESCALER_SET_DIV10_EVENT_O_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_SOFT_RESET_EVENT_O_IDX_BIT

Referenced by __pi_i2c_timeout_abort().

#define UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_SOFT_RESET_EVENT_O_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_SOFT_RESET_EVENT_O_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_I2C_SOFT_RESET_EVENT_O_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_COMMAND_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_COMMAND_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_COMMAND_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_COMMAND_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_ARLO_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_ARLO_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_ARLO_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_ARLO_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_FRAMING_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_FRAMING_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_FRAMING_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_FRAMING_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_NACK_EVENT_I_IDX_BIT

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_NACK_EVENT_I_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_NACK_EVENT_I_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_ERROR_NACK_EVENT_I_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_PURGE_EVENT_O_IDX_BIT

Referenced by __pi_i2c_timeout_abort().

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_PURGE_EVENT_O_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_PURGE_EVENT_O_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_PURGE_EVENT_O_IDX_WIDTH

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_UNLOCK_EVENT_O_IDX_BIT

Referenced by __pi_i2c_timeout_abort().

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_UNLOCK_EVENT_O_IDX_MASK

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_UNLOCK_EVENT_O_IDX_RESET

#define UDMA_I2C_STATUS_REG_IDX_STATUS_LEAD_UNLOCK_EVENT_O_IDX_WIDTH