udma_hyper_regfields.h File Reference

Macros
#define	UDMA_HYPER_RX_DEST_DEST_BIT
#define	UDMA_HYPER_RX_DEST_DEST_WIDTH
#define	UDMA_HYPER_RX_DEST_DEST_MASK
#define	UDMA_HYPER_RX_DEST_DEST_RESET
#define	UDMA_HYPER_RX_DEST_DEST_STREAM_BIT
#define	UDMA_HYPER_RX_DEST_DEST_STREAM_WIDTH
#define	UDMA_HYPER_RX_DEST_DEST_STREAM_MASK
#define	UDMA_HYPER_RX_DEST_DEST_STREAM_RESET
#define	UDMA_HYPER_TX_DEST_DEST_BIT
#define	UDMA_HYPER_TX_DEST_DEST_WIDTH
#define	UDMA_HYPER_TX_DEST_DEST_MASK
#define	UDMA_HYPER_TX_DEST_DEST_RESET
#define	UDMA_HYPER_TX_DEST_DEST_STREAM_BIT
#define	UDMA_HYPER_TX_DEST_DEST_STREAM_WIDTH
#define	UDMA_HYPER_TX_DEST_DEST_STREAM_MASK
#define	UDMA_HYPER_TX_DEST_DEST_STREAM_RESET
#define	UDMA_HYPER_TRANS_MODE_AUTO_ENA_BIT
#define	UDMA_HYPER_TRANS_MODE_AUTO_ENA_WIDTH
#define	UDMA_HYPER_TRANS_MODE_AUTO_ENA_MASK
#define	UDMA_HYPER_TRANS_MODE_AUTO_ENA_RESET
#define	UDMA_HYPER_TRANS_MODE_XIP_EN_BIT
#define	UDMA_HYPER_TRANS_MODE_XIP_EN_WIDTH
#define	UDMA_HYPER_TRANS_MODE_XIP_EN_MASK
#define	UDMA_HYPER_TRANS_MODE_XIP_EN_RESET
#define	UDMA_HYPER_TRANS_MODE_STREAM_EN_BIT
#define	UDMA_HYPER_TRANS_MODE_STREAM_EN_WIDTH
#define	UDMA_HYPER_TRANS_MODE_STREAM_EN_MASK
#define	UDMA_HYPER_TRANS_MODE_STREAM_EN_RESET
#define	UDMA_HYPER_TRANS_MODE_STREAM_XIP_EN_BIT
#define	UDMA_HYPER_TRANS_MODE_STREAM_XIP_EN_WIDTH
#define	UDMA_HYPER_TRANS_MODE_STREAM_XIP_EN_MASK
#define	UDMA_HYPER_TRANS_MODE_STREAM_XIP_EN_RESET
#define	UDMA_HYPER_TRANS_MODE_XIP_HALTED_BIT
#define	UDMA_HYPER_TRANS_MODE_XIP_HALTED_WIDTH
#define	UDMA_HYPER_TRANS_MODE_XIP_HALTED_MASK
#define	UDMA_HYPER_TRANS_MODE_XIP_HALTED_RESET
#define	UDMA_HYPER_TRANS_ADDR_ADDR_BIT
#define	UDMA_HYPER_TRANS_ADDR_ADDR_WIDTH
#define	UDMA_HYPER_TRANS_ADDR_ADDR_MASK
#define	UDMA_HYPER_TRANS_ADDR_ADDR_RESET
#define	UDMA_HYPER_TRANS_SIZE_SIZE_BIT
#define	UDMA_HYPER_TRANS_SIZE_SIZE_WIDTH
#define	UDMA_HYPER_TRANS_SIZE_SIZE_MASK
#define	UDMA_HYPER_TRANS_SIZE_SIZE_RESET
#define	UDMA_HYPER_TRANS_CFG_RXTX_BIT
#define	UDMA_HYPER_TRANS_CFG_RXTX_WIDTH
#define	UDMA_HYPER_TRANS_CFG_RXTX_MASK
#define	UDMA_HYPER_TRANS_CFG_RXTX_RESET
#define	UDMA_HYPER_TRANS_CFG_VALID_BIT
#define	UDMA_HYPER_TRANS_CFG_VALID_WIDTH
#define	UDMA_HYPER_TRANS_CFG_VALID_MASK
#define	UDMA_HYPER_TRANS_CFG_VALID_RESET
#define	UDMA_HYPER_OSPI_CMD_XIP_CMD_BIT
#define	UDMA_HYPER_OSPI_CMD_XIP_CMD_WIDTH
#define	UDMA_HYPER_OSPI_CMD_XIP_CMD_MASK
#define	UDMA_HYPER_OSPI_CMD_XIP_CMD_RESET
#define	UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_RSP_TYPE_BIT
#define	UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_RSP_TYPE_WIDTH
#define	UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_RSP_TYPE_MASK
#define	UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_RSP_TYPE_RESET
#define	UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_OP_BIT
#define	UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_OP_WIDTH
#define	UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_OP_MASK
#define	UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_OP_RESET
#define	UDMA_HYPER_OSPI_CFG_XIP_CMD_SIZE_BIT
#define	UDMA_HYPER_OSPI_CFG_XIP_CMD_SIZE_WIDTH
#define	UDMA_HYPER_OSPI_CFG_XIP_CMD_SIZE_MASK
#define	UDMA_HYPER_OSPI_CFG_XIP_CMD_SIZE_RESET
#define	UDMA_HYPER_OSPI_CFG_XIP_ADDR_SIZE_BIT
#define	UDMA_HYPER_OSPI_CFG_XIP_ADDR_SIZE_WIDTH
#define	UDMA_HYPER_OSPI_CFG_XIP_ADDR_SIZE_MASK
#define	UDMA_HYPER_OSPI_CFG_XIP_ADDR_SIZE_RESET
#define	UDMA_HYPER_OSPI_CFG_XIP_LINE_BIT
#define	UDMA_HYPER_OSPI_CFG_XIP_LINE_WIDTH
#define	UDMA_HYPER_OSPI_CFG_XIP_LINE_MASK
#define	UDMA_HYPER_OSPI_CFG_XIP_LINE_RESET
#define	UDMA_HYPER_OSPI_CFG_XIP_CMD_DTR_STR_BIT
#define	UDMA_HYPER_OSPI_CFG_XIP_CMD_DTR_STR_WIDTH
#define	UDMA_HYPER_OSPI_CFG_XIP_CMD_DTR_STR_MASK
#define	UDMA_HYPER_OSPI_CFG_XIP_CMD_DTR_STR_RESET
#define	UDMA_HYPER_OSPI_CFG_XIP_ADDR_DTR_STR_BIT
#define	UDMA_HYPER_OSPI_CFG_XIP_ADDR_DTR_STR_WIDTH
#define	UDMA_HYPER_OSPI_CFG_XIP_ADDR_DTR_STR_MASK
#define	UDMA_HYPER_OSPI_CFG_XIP_ADDR_DTR_STR_RESET
#define	UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_STR_BIT
#define	UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_STR_WIDTH
#define	UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_STR_MASK
#define	UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_STR_RESET
#define	UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_MSB_BIT
#define	UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_MSB_WIDTH
#define	UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_MSB_MASK
#define	UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_MSB_RESET
#define	UDMA_HYPER_EXT_ADDR_SADDR_BIT
#define	UDMA_HYPER_EXT_ADDR_SADDR_WIDTH
#define	UDMA_HYPER_EXT_ADDR_SADDR_MASK
#define	UDMA_HYPER_EXT_ADDR_SADDR_RESET
#define	UDMA_HYPER_EXT_ADDR_REG_ACCESS_BIT
#define	UDMA_HYPER_EXT_ADDR_REG_ACCESS_WIDTH
#define	UDMA_HYPER_EXT_ADDR_REG_ACCESS_MASK
#define	UDMA_HYPER_EXT_ADDR_REG_ACCESS_RESET
#define	UDMA_HYPER_TIMING_CFG_LATENCY0_BIT
#define	UDMA_HYPER_TIMING_CFG_LATENCY0_WIDTH
#define	UDMA_HYPER_TIMING_CFG_LATENCY0_MASK
#define	UDMA_HYPER_TIMING_CFG_LATENCY0_RESET
#define	UDMA_HYPER_TIMING_CFG_LATENCY1_BIT
#define	UDMA_HYPER_TIMING_CFG_LATENCY1_WIDTH
#define	UDMA_HYPER_TIMING_CFG_LATENCY1_MASK
#define	UDMA_HYPER_TIMING_CFG_LATENCY1_RESET
#define	UDMA_HYPER_TIMING_CFG_RW_RECOVERY_BIT
#define	UDMA_HYPER_TIMING_CFG_RW_RECOVERY_WIDTH
#define	UDMA_HYPER_TIMING_CFG_RW_RECOVERY_MASK
#define	UDMA_HYPER_TIMING_CFG_RW_RECOVERY_RESET
#define	UDMA_HYPER_TIMING_CFG_RWDS_DELAY_BIT
#define	UDMA_HYPER_TIMING_CFG_RWDS_DELAY_WIDTH
#define	UDMA_HYPER_TIMING_CFG_RWDS_DELAY_MASK
#define	UDMA_HYPER_TIMING_CFG_RWDS_DELAY_RESET
#define	UDMA_HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_BIT
#define	UDMA_HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_WIDTH
#define	UDMA_HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_MASK
#define	UDMA_HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_RESET
#define	UDMA_HYPER_TIMING_CFG_CS_MAX_BIT
#define	UDMA_HYPER_TIMING_CFG_CS_MAX_WIDTH
#define	UDMA_HYPER_TIMING_CFG_CS_MAX_MASK
#define	UDMA_HYPER_TIMING_CFG_CS_MAX_RESET
#define	UDMA_HYPER_MBA0_RESERVED_BIT
#define	UDMA_HYPER_MBA0_RESERVED_WIDTH
#define	UDMA_HYPER_MBA0_RESERVED_MASK
#define	UDMA_HYPER_MBA0_RESERVED_RESET
#define	UDMA_HYPER_MBA0_MBA0_BIT
#define	UDMA_HYPER_MBA0_MBA0_WIDTH
#define	UDMA_HYPER_MBA0_MBA0_MASK
#define	UDMA_HYPER_MBA0_MBA0_RESET
#define	UDMA_HYPER_MBA1_RESERVED_BIT
#define	UDMA_HYPER_MBA1_RESERVED_WIDTH
#define	UDMA_HYPER_MBA1_RESERVED_MASK
#define	UDMA_HYPER_MBA1_RESERVED_RESET
#define	UDMA_HYPER_MBA1_MBA1_BIT
#define	UDMA_HYPER_MBA1_MBA1_WIDTH
#define	UDMA_HYPER_MBA1_MBA1_MASK
#define	UDMA_HYPER_MBA1_MBA1_RESET
#define	UDMA_HYPER_DEVICE_TYPE_BIT
#define	UDMA_HYPER_DEVICE_TYPE_WIDTH
#define	UDMA_HYPER_DEVICE_TYPE_MASK
#define	UDMA_HYPER_DEVICE_TYPE_RESET
#define	UDMA_HYPER_DEVICE_DT0_BIT
#define	UDMA_HYPER_DEVICE_DT0_WIDTH
#define	UDMA_HYPER_DEVICE_DT0_MASK
#define	UDMA_HYPER_DEVICE_DT0_RESET
#define	UDMA_HYPER_DEVICE_DT1_BIT
#define	UDMA_HYPER_DEVICE_DT1_WIDTH
#define	UDMA_HYPER_DEVICE_DT1_MASK
#define	UDMA_HYPER_DEVICE_DT1_RESET
#define	UDMA_HYPER_DEVICE_SDIO_BIT
#define	UDMA_HYPER_DEVICE_SDIO_WIDTH
#define	UDMA_HYPER_DEVICE_SDIO_MASK
#define	UDMA_HYPER_DEVICE_SDIO_RESET
#define	UDMA_HYPER_OSPI_CMD_CMD_BIT
#define	UDMA_HYPER_OSPI_CMD_CMD_WIDTH
#define	UDMA_HYPER_OSPI_CMD_CMD_MASK
#define	UDMA_HYPER_OSPI_CMD_CMD_RESET
#define	UDMA_HYPER_OSPI_CMD_SDIO_CMD_RSP_TYPE_BIT
#define	UDMA_HYPER_OSPI_CMD_SDIO_CMD_RSP_TYPE_WIDTH
#define	UDMA_HYPER_OSPI_CMD_SDIO_CMD_RSP_TYPE_MASK
#define	UDMA_HYPER_OSPI_CMD_SDIO_CMD_RSP_TYPE_RESET
#define	UDMA_HYPER_OSPI_CMD_SDIO_CMD_OP_BIT
#define	UDMA_HYPER_OSPI_CMD_SDIO_CMD_OP_WIDTH
#define	UDMA_HYPER_OSPI_CMD_SDIO_CMD_OP_MASK
#define	UDMA_HYPER_OSPI_CMD_SDIO_CMD_OP_RESET
#define	UDMA_HYPER_OSPI_ALTER_MODE0_BIT
#define	UDMA_HYPER_OSPI_ALTER_MODE0_WIDTH
#define	UDMA_HYPER_OSPI_ALTER_MODE0_MASK
#define	UDMA_HYPER_OSPI_ALTER_MODE0_RESET
#define	UDMA_HYPER_OSPI_ALTER_MODE1_BIT
#define	UDMA_HYPER_OSPI_ALTER_MODE1_WIDTH
#define	UDMA_HYPER_OSPI_ALTER_MODE1_MASK
#define	UDMA_HYPER_OSPI_ALTER_MODE1_RESET
#define	UDMA_HYPER_OSPI_CFG_CMD_SIZE_BIT
#define	UDMA_HYPER_OSPI_CFG_CMD_SIZE_WIDTH
#define	UDMA_HYPER_OSPI_CFG_CMD_SIZE_MASK
#define	UDMA_HYPER_OSPI_CFG_CMD_SIZE_RESET
#define	UDMA_HYPER_OSPI_CFG_ADDR_SIZE_BIT
#define	UDMA_HYPER_OSPI_CFG_ADDR_SIZE_WIDTH
#define	UDMA_HYPER_OSPI_CFG_ADDR_SIZE_MASK
#define	UDMA_HYPER_OSPI_CFG_ADDR_SIZE_RESET
#define	UDMA_HYPER_OSPI_CFG_LINE_BIT
#define	UDMA_HYPER_OSPI_CFG_LINE_WIDTH
#define	UDMA_HYPER_OSPI_CFG_LINE_MASK
#define	UDMA_HYPER_OSPI_CFG_LINE_RESET
#define	UDMA_HYPER_OSPI_CFG_CMD_DTR_STR_BIT
#define	UDMA_HYPER_OSPI_CFG_CMD_DTR_STR_WIDTH
#define	UDMA_HYPER_OSPI_CFG_CMD_DTR_STR_MASK
#define	UDMA_HYPER_OSPI_CFG_CMD_DTR_STR_RESET
#define	UDMA_HYPER_OSPI_CFG_ADDR_DTR_STR_BIT
#define	UDMA_HYPER_OSPI_CFG_ADDR_DTR_STR_WIDTH
#define	UDMA_HYPER_OSPI_CFG_ADDR_DTR_STR_MASK
#define	UDMA_HYPER_OSPI_CFG_ADDR_DTR_STR_RESET
#define	UDMA_HYPER_OSPI_CFG_DATA_DTR_STR_BIT
#define	UDMA_HYPER_OSPI_CFG_DATA_DTR_STR_WIDTH
#define	UDMA_HYPER_OSPI_CFG_DATA_DTR_STR_MASK
#define	UDMA_HYPER_OSPI_CFG_DATA_DTR_STR_RESET
#define	UDMA_HYPER_OSPI_CFG_DATA_DTR_MSB_BIT
#define	UDMA_HYPER_OSPI_CFG_DATA_DTR_MSB_WIDTH
#define	UDMA_HYPER_OSPI_CFG_DATA_DTR_MSB_MASK
#define	UDMA_HYPER_OSPI_CFG_DATA_DTR_MSB_RESET
#define	UDMA_HYPER_OSPI_CSN_INDEX_BIT
#define	UDMA_HYPER_OSPI_CSN_INDEX_WIDTH
#define	UDMA_HYPER_OSPI_CSN_INDEX_MASK
#define	UDMA_HYPER_OSPI_CSN_INDEX_RESET
#define	UDMA_HYPER_OSPI_CSN_AUTO_EN_BIT
#define	UDMA_HYPER_OSPI_CSN_AUTO_EN_WIDTH
#define	UDMA_HYPER_OSPI_CSN_AUTO_EN_MASK
#define	UDMA_HYPER_OSPI_CSN_AUTO_EN_RESET
#define	UDMA_HYPER_OSPI_CSN_RESERVED_BIT
#define	UDMA_HYPER_OSPI_CSN_RESERVED_WIDTH
#define	UDMA_HYPER_OSPI_CSN_RESERVED_MASK
#define	UDMA_HYPER_OSPI_CSN_RESERVED_RESET
#define	UDMA_HYPER_OSPI_CSN_DIRECT_CTRL_BIT
#define	UDMA_HYPER_OSPI_CSN_DIRECT_CTRL_WIDTH
#define	UDMA_HYPER_OSPI_CSN_DIRECT_CTRL_MASK
#define	UDMA_HYPER_OSPI_CSN_DIRECT_CTRL_RESET
#define	UDMA_HYPER_OSPI_CSN_VALUE_BIT
#define	UDMA_HYPER_OSPI_CSN_VALUE_WIDTH
#define	UDMA_HYPER_OSPI_CSN_VALUE_MASK
#define	UDMA_HYPER_OSPI_CSN_VALUE_RESET
#define	UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_BIT
#define	UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_WIDTH
#define	UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_MASK
#define	UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_RESET
#define	UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_DDR_BIT
#define	UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_DDR_WIDTH
#define	UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_DDR_MASK
#define	UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_DDR_RESET
#define	UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_NUM_BIT
#define	UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_NUM_WIDTH
#define	UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_NUM_MASK
#define	UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_NUM_RESET
#define	UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_SIZE_BIT
#define	UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_SIZE_WIDTH
#define	UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_SIZE_MASK
#define	UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_SIZE_RESET
#define	UDMA_HYPER_OSPI_CSN_SDIO_AUTO_STOP_BIT
#define	UDMA_HYPER_OSPI_CSN_SDIO_AUTO_STOP_WIDTH
#define	UDMA_HYPER_OSPI_CSN_SDIO_AUTO_STOP_MASK
#define	UDMA_HYPER_OSPI_CSN_SDIO_AUTO_STOP_RESET
#define	UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_EN_BIT
#define	UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_EN_WIDTH
#define	UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_EN_MASK
#define	UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_EN_RESET
#define	UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_VALUE_BIT
#define	UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_VALUE_WIDTH
#define	UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_VALUE_MASK
#define	UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_VALUE_RESET
#define	UDMA_HYPER_OSPI_RAM_OPT_OPT_READ_EN_CS_BIT
#define	UDMA_HYPER_OSPI_RAM_OPT_OPT_READ_EN_CS_WIDTH
#define	UDMA_HYPER_OSPI_RAM_OPT_OPT_READ_EN_CS_MASK
#define	UDMA_HYPER_OSPI_RAM_OPT_OPT_READ_EN_CS_RESET
#define	UDMA_HYPER_OSPI_RAM_OPT_REAL_ADDR_EN_BIT
#define	UDMA_HYPER_OSPI_RAM_OPT_REAL_ADDR_EN_WIDTH
#define	UDMA_HYPER_OSPI_RAM_OPT_REAL_ADDR_EN_MASK
#define	UDMA_HYPER_OSPI_RAM_OPT_REAL_ADDR_EN_RESET
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_READ_BIT_BIT
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_READ_BIT_WIDTH
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_READ_BIT_MASK
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_READ_BIT_RESET
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CMD_EN_BIT
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CMD_EN_WIDTH
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CMD_EN_MASK
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CMD_EN_RESET
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_ADDR_EVEN_BIT
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_ADDR_EVEN_WIDTH
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_ADDR_EVEN_MASK
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_ADDR_EVEN_RESET
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CROSS_BOUNDARY_EN_BIT
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CROSS_BOUNDARY_EN_WIDTH
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CROSS_BOUNDARY_EN_MASK
#define	UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CROSS_BOUNDARY_EN_RESET
#define	UDMA_HYPER_OSPI_ALTER_XIP_MODE0_BIT
#define	UDMA_HYPER_OSPI_ALTER_XIP_MODE0_WIDTH
#define	UDMA_HYPER_OSPI_ALTER_XIP_MODE0_MASK
#define	UDMA_HYPER_OSPI_ALTER_XIP_MODE0_RESET
#define	UDMA_HYPER_OSPI_ALTER_XIP_MODE1_BIT
#define	UDMA_HYPER_OSPI_ALTER_XIP_MODE1_WIDTH
#define	UDMA_HYPER_OSPI_ALTER_XIP_MODE1_MASK
#define	UDMA_HYPER_OSPI_ALTER_XIP_MODE1_RESET
#define	UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY0_BIT
#define	UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY0_WIDTH
#define	UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY0_MASK
#define	UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY0_RESET
#define	UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY1_BIT
#define	UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY1_WIDTH
#define	UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY1_MASK
#define	UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY1_RESET
#define	UDMA_HYPER_LINE_2D_LINE_BIT
#define	UDMA_HYPER_LINE_2D_LINE_WIDTH
#define	UDMA_HYPER_LINE_2D_LINE_MASK
#define	UDMA_HYPER_LINE_2D_LINE_RESET
#define	UDMA_HYPER_STRIDE_2D_STRIDE_BIT
#define	UDMA_HYPER_STRIDE_2D_STRIDE_WIDTH
#define	UDMA_HYPER_STRIDE_2D_STRIDE_MASK
#define	UDMA_HYPER_STRIDE_2D_STRIDE_RESET
#define	UDMA_HYPER_BURST_ENABLE_CS0_AUTO_BURST_ENABLE_BIT
#define	UDMA_HYPER_BURST_ENABLE_CS0_AUTO_BURST_ENABLE_WIDTH
#define	UDMA_HYPER_BURST_ENABLE_CS0_AUTO_BURST_ENABLE_MASK
#define	UDMA_HYPER_BURST_ENABLE_CS0_AUTO_BURST_ENABLE_RESET
#define	UDMA_HYPER_BURST_ENABLE_CS1_AUTO_BURST_ENABLE_BIT
#define	UDMA_HYPER_BURST_ENABLE_CS1_AUTO_BURST_ENABLE_WIDTH
#define	UDMA_HYPER_BURST_ENABLE_CS1_AUTO_BURST_ENABLE_MASK
#define	UDMA_HYPER_BURST_ENABLE_CS1_AUTO_BURST_ENABLE_RESET
#define	UDMA_HYPER_BURST_ENABLE_CS0_MAXIMUM_CHECK_ENABLE_BIT
#define	UDMA_HYPER_BURST_ENABLE_CS0_MAXIMUM_CHECK_ENABLE_WIDTH
#define	UDMA_HYPER_BURST_ENABLE_CS0_MAXIMUM_CHECK_ENABLE_MASK
#define	UDMA_HYPER_BURST_ENABLE_CS0_MAXIMUM_CHECK_ENABLE_RESET
#define	UDMA_HYPER_BURST_ENABLE_CS1_MAXIMUM_CHECK_ENABLE_BIT
#define	UDMA_HYPER_BURST_ENABLE_CS1_MAXIMUM_CHECK_ENABLE_WIDTH
#define	UDMA_HYPER_BURST_ENABLE_CS1_MAXIMUM_CHECK_ENABLE_MASK
#define	UDMA_HYPER_BURST_ENABLE_CS1_MAXIMUM_CHECK_ENABLE_RESET
#define	UDMA_HYPER_BURST_ENABLE_2D_ENABLE_BIT
#define	UDMA_HYPER_BURST_ENABLE_2D_ENABLE_WIDTH
#define	UDMA_HYPER_BURST_ENABLE_2D_ENABLE_MASK
#define	UDMA_HYPER_BURST_ENABLE_2D_ENABLE_RESET
#define	UDMA_HYPER_BURST_ENABLE_2D_MODE_BIT
#define	UDMA_HYPER_BURST_ENABLE_2D_MODE_WIDTH
#define	UDMA_HYPER_BURST_ENABLE_2D_MODE_MASK
#define	UDMA_HYPER_BURST_ENABLE_2D_MODE_RESET
#define	UDMA_HYPER_IRQ_EN_EN_BIT
#define	UDMA_HYPER_IRQ_EN_EN_WIDTH
#define	UDMA_HYPER_IRQ_EN_EN_MASK
#define	UDMA_HYPER_IRQ_EN_EN_RESET
#define	UDMA_HYPER_IRQ_EN_XIP_EN_BIT
#define	UDMA_HYPER_IRQ_EN_XIP_EN_WIDTH
#define	UDMA_HYPER_IRQ_EN_XIP_EN_MASK
#define	UDMA_HYPER_IRQ_EN_XIP_EN_RESET
#define	UDMA_HYPER_CLK_DIV_DATA_BIT
#define	UDMA_HYPER_CLK_DIV_DATA_WIDTH
#define	UDMA_HYPER_CLK_DIV_DATA_MASK
#define	UDMA_HYPER_CLK_DIV_DATA_RESET
#define	UDMA_HYPER_CLK_DIV_VALID_BIT
#define	UDMA_HYPER_CLK_DIV_VALID_WIDTH
#define	UDMA_HYPER_CLK_DIV_VALID_MASK
#define	UDMA_HYPER_CLK_DIV_VALID_RESET
#define	UDMA_HYPER_STATUS_TX_ERROR_BIT
#define	UDMA_HYPER_STATUS_TX_ERROR_WIDTH
#define	UDMA_HYPER_STATUS_TX_ERROR_MASK
#define	UDMA_HYPER_STATUS_TX_ERROR_RESET
#define	UDMA_HYPER_STATUS_RX_ERROR_BIT
#define	UDMA_HYPER_STATUS_RX_ERROR_WIDTH
#define	UDMA_HYPER_STATUS_RX_ERROR_MASK
#define	UDMA_HYPER_STATUS_RX_ERROR_RESET
#define	UDMA_HYPER_STATUS_RX_TX_END_BIT
#define	UDMA_HYPER_STATUS_RX_TX_END_WIDTH
#define	UDMA_HYPER_STATUS_RX_TX_END_MASK
#define	UDMA_HYPER_STATUS_RX_TX_END_RESET
#define	UDMA_HYPER_STATUS_SDIO_RX_TX_ERROR_BIT
#define	UDMA_HYPER_STATUS_SDIO_RX_TX_ERROR_WIDTH
#define	UDMA_HYPER_STATUS_SDIO_RX_TX_ERROR_MASK
#define	UDMA_HYPER_STATUS_SDIO_RX_TX_ERROR_RESET
#define	UDMA_HYPER_STATUS_SDIO_RX_TX_END_BIT
#define	UDMA_HYPER_STATUS_SDIO_RX_TX_END_WIDTH
#define	UDMA_HYPER_STATUS_SDIO_RX_TX_END_MASK
#define	UDMA_HYPER_STATUS_SDIO_RX_TX_END_RESET
#define	UDMA_HYPER_STATUS_RESERVED_BIT
#define	UDMA_HYPER_STATUS_RESERVED_WIDTH
#define	UDMA_HYPER_STATUS_RESERVED_MASK
#define	UDMA_HYPER_STATUS_RESERVED_RESET
#define	UDMA_HYPER_STATUS_SDIO_ERROR_STATUS_BIT
#define	UDMA_HYPER_STATUS_SDIO_ERROR_STATUS_WIDTH
#define	UDMA_HYPER_STATUS_SDIO_ERROR_STATUS_MASK
#define	UDMA_HYPER_STATUS_SDIO_ERROR_STATUS_RESET
#define	UDMA_HYPER_SDIO_CMD_ARG_ARG_BIT
#define	UDMA_HYPER_SDIO_CMD_ARG_ARG_WIDTH
#define	UDMA_HYPER_SDIO_CMD_ARG_ARG_MASK
#define	UDMA_HYPER_SDIO_CMD_ARG_ARG_RESET
#define	UDMA_HYPER_SDIO_RSP0_RSP0_BIT
#define	UDMA_HYPER_SDIO_RSP0_RSP0_WIDTH
#define	UDMA_HYPER_SDIO_RSP0_RSP0_MASK
#define	UDMA_HYPER_SDIO_RSP0_RSP0_RESET
#define	UDMA_HYPER_SDIO_RSP1_RSP1_BIT
#define	UDMA_HYPER_SDIO_RSP1_RSP1_WIDTH
#define	UDMA_HYPER_SDIO_RSP1_RSP1_MASK
#define	UDMA_HYPER_SDIO_RSP1_RSP1_RESET
#define	UDMA_HYPER_SDIO_RSP2_RSP2_BIT
#define	UDMA_HYPER_SDIO_RSP2_RSP2_WIDTH
#define	UDMA_HYPER_SDIO_RSP2_RSP2_MASK
#define	UDMA_HYPER_SDIO_RSP2_RSP2_RESET
#define	UDMA_HYPER_SDIO_RSP3_RSP3_BIT
#define	UDMA_HYPER_SDIO_RSP3_RSP3_WIDTH
#define	UDMA_HYPER_SDIO_RSP3_RSP3_MASK
#define	UDMA_HYPER_SDIO_RSP3_RSP3_RESET

Macro Definition Documentation

#define UDMA_HYPER_BURST_ENABLE_2D_ENABLE_BIT

#define UDMA_HYPER_BURST_ENABLE_2D_ENABLE_MASK

#define UDMA_HYPER_BURST_ENABLE_2D_ENABLE_RESET

#define UDMA_HYPER_BURST_ENABLE_2D_ENABLE_WIDTH

#define UDMA_HYPER_BURST_ENABLE_2D_MODE_BIT

#define UDMA_HYPER_BURST_ENABLE_2D_MODE_MASK

#define UDMA_HYPER_BURST_ENABLE_2D_MODE_RESET

#define UDMA_HYPER_BURST_ENABLE_2D_MODE_WIDTH

#define UDMA_HYPER_BURST_ENABLE_CS0_AUTO_BURST_ENABLE_BIT

#define UDMA_HYPER_BURST_ENABLE_CS0_AUTO_BURST_ENABLE_MASK

Referenced by __pi_octospi_open().

#define UDMA_HYPER_BURST_ENABLE_CS0_AUTO_BURST_ENABLE_RESET

#define UDMA_HYPER_BURST_ENABLE_CS0_AUTO_BURST_ENABLE_WIDTH

#define UDMA_HYPER_BURST_ENABLE_CS0_MAXIMUM_CHECK_ENABLE_BIT

#define UDMA_HYPER_BURST_ENABLE_CS0_MAXIMUM_CHECK_ENABLE_MASK

Referenced by __pi_octospi_open().

#define UDMA_HYPER_BURST_ENABLE_CS0_MAXIMUM_CHECK_ENABLE_RESET

#define UDMA_HYPER_BURST_ENABLE_CS0_MAXIMUM_CHECK_ENABLE_WIDTH

#define UDMA_HYPER_BURST_ENABLE_CS1_AUTO_BURST_ENABLE_BIT

#define UDMA_HYPER_BURST_ENABLE_CS1_AUTO_BURST_ENABLE_MASK

#define UDMA_HYPER_BURST_ENABLE_CS1_AUTO_BURST_ENABLE_RESET

#define UDMA_HYPER_BURST_ENABLE_CS1_AUTO_BURST_ENABLE_WIDTH

#define UDMA_HYPER_BURST_ENABLE_CS1_MAXIMUM_CHECK_ENABLE_BIT

#define UDMA_HYPER_BURST_ENABLE_CS1_MAXIMUM_CHECK_ENABLE_MASK

#define UDMA_HYPER_BURST_ENABLE_CS1_MAXIMUM_CHECK_ENABLE_RESET

#define UDMA_HYPER_BURST_ENABLE_CS1_MAXIMUM_CHECK_ENABLE_WIDTH

#define UDMA_HYPER_CLK_DIV_DATA_BIT

#define UDMA_HYPER_CLK_DIV_DATA_MASK

#define UDMA_HYPER_CLK_DIV_DATA_RESET

#define UDMA_HYPER_CLK_DIV_DATA_WIDTH

#define UDMA_HYPER_CLK_DIV_VALID_BIT

#define UDMA_HYPER_CLK_DIV_VALID_MASK

#define UDMA_HYPER_CLK_DIV_VALID_RESET

#define UDMA_HYPER_CLK_DIV_VALID_WIDTH

#define UDMA_HYPER_DEVICE_DT0_BIT

#define UDMA_HYPER_DEVICE_DT0_MASK

#define UDMA_HYPER_DEVICE_DT0_RESET

#define UDMA_HYPER_DEVICE_DT0_WIDTH

#define UDMA_HYPER_DEVICE_DT1_BIT

#define UDMA_HYPER_DEVICE_DT1_MASK

#define UDMA_HYPER_DEVICE_DT1_RESET

#define UDMA_HYPER_DEVICE_DT1_WIDTH

#define UDMA_HYPER_DEVICE_SDIO_BIT

#define UDMA_HYPER_DEVICE_SDIO_MASK

#define UDMA_HYPER_DEVICE_SDIO_RESET

#define UDMA_HYPER_DEVICE_SDIO_WIDTH

#define UDMA_HYPER_DEVICE_TYPE_BIT

#define UDMA_HYPER_DEVICE_TYPE_MASK

#define UDMA_HYPER_DEVICE_TYPE_RESET

#define UDMA_HYPER_DEVICE_TYPE_WIDTH

#define UDMA_HYPER_EXT_ADDR_REG_ACCESS_BIT

#define UDMA_HYPER_EXT_ADDR_REG_ACCESS_MASK

#define UDMA_HYPER_EXT_ADDR_REG_ACCESS_RESET

#define UDMA_HYPER_EXT_ADDR_REG_ACCESS_WIDTH

#define UDMA_HYPER_EXT_ADDR_SADDR_BIT

#define UDMA_HYPER_EXT_ADDR_SADDR_MASK

#define UDMA_HYPER_EXT_ADDR_SADDR_RESET

#define UDMA_HYPER_EXT_ADDR_SADDR_WIDTH

#define UDMA_HYPER_IRQ_EN_EN_BIT

#define UDMA_HYPER_IRQ_EN_EN_MASK

#define UDMA_HYPER_IRQ_EN_EN_RESET

#define UDMA_HYPER_IRQ_EN_EN_WIDTH

#define UDMA_HYPER_IRQ_EN_XIP_EN_BIT

#define UDMA_HYPER_IRQ_EN_XIP_EN_MASK

#define UDMA_HYPER_IRQ_EN_XIP_EN_RESET

#define UDMA_HYPER_IRQ_EN_XIP_EN_WIDTH

#define UDMA_HYPER_LINE_2D_LINE_BIT

#define UDMA_HYPER_LINE_2D_LINE_MASK

#define UDMA_HYPER_LINE_2D_LINE_RESET

#define UDMA_HYPER_LINE_2D_LINE_WIDTH

#define UDMA_HYPER_MBA0_MBA0_BIT

#define UDMA_HYPER_MBA0_MBA0_MASK

#define UDMA_HYPER_MBA0_MBA0_RESET

#define UDMA_HYPER_MBA0_MBA0_WIDTH

#define UDMA_HYPER_MBA0_RESERVED_BIT

#define UDMA_HYPER_MBA0_RESERVED_MASK

#define UDMA_HYPER_MBA0_RESERVED_RESET

#define UDMA_HYPER_MBA0_RESERVED_WIDTH

#define UDMA_HYPER_MBA1_MBA1_BIT

#define UDMA_HYPER_MBA1_MBA1_MASK

#define UDMA_HYPER_MBA1_MBA1_RESET

#define UDMA_HYPER_MBA1_MBA1_WIDTH

#define UDMA_HYPER_MBA1_RESERVED_BIT

#define UDMA_HYPER_MBA1_RESERVED_MASK

#define UDMA_HYPER_MBA1_RESERVED_RESET

#define UDMA_HYPER_MBA1_RESERVED_WIDTH

#define UDMA_HYPER_OSPI_ALTER_MODE0_BIT

#define UDMA_HYPER_OSPI_ALTER_MODE0_MASK

Referenced by hal_udma_hyperbus_ospi_alter_set(), and hal_udma_hyperbus_ospi_alter_xip_set().

#define UDMA_HYPER_OSPI_ALTER_MODE0_RESET

#define UDMA_HYPER_OSPI_ALTER_MODE0_WIDTH

Referenced by hal_udma_hyperbus_ospi_alter_set(), and hal_udma_hyperbus_ospi_alter_xip_set().

#define UDMA_HYPER_OSPI_ALTER_MODE1_BIT

#define UDMA_HYPER_OSPI_ALTER_MODE1_MASK

#define UDMA_HYPER_OSPI_ALTER_MODE1_RESET

#define UDMA_HYPER_OSPI_ALTER_MODE1_WIDTH

#define UDMA_HYPER_OSPI_ALTER_XIP_MODE0_BIT

#define UDMA_HYPER_OSPI_ALTER_XIP_MODE0_MASK

#define UDMA_HYPER_OSPI_ALTER_XIP_MODE0_RESET

#define UDMA_HYPER_OSPI_ALTER_XIP_MODE0_WIDTH

#define UDMA_HYPER_OSPI_ALTER_XIP_MODE1_BIT

#define UDMA_HYPER_OSPI_ALTER_XIP_MODE1_MASK

#define UDMA_HYPER_OSPI_ALTER_XIP_MODE1_RESET

#define UDMA_HYPER_OSPI_ALTER_XIP_MODE1_WIDTH

#define UDMA_HYPER_OSPI_CFG_ADDR_DTR_STR_BIT

#define UDMA_HYPER_OSPI_CFG_ADDR_DTR_STR_MASK

#define UDMA_HYPER_OSPI_CFG_ADDR_DTR_STR_RESET

#define UDMA_HYPER_OSPI_CFG_ADDR_DTR_STR_WIDTH

#define UDMA_HYPER_OSPI_CFG_ADDR_SIZE_BIT

#define UDMA_HYPER_OSPI_CFG_ADDR_SIZE_MASK

#define UDMA_HYPER_OSPI_CFG_ADDR_SIZE_RESET

#define UDMA_HYPER_OSPI_CFG_ADDR_SIZE_WIDTH

#define UDMA_HYPER_OSPI_CFG_CMD_DTR_STR_BIT

#define UDMA_HYPER_OSPI_CFG_CMD_DTR_STR_MASK

#define UDMA_HYPER_OSPI_CFG_CMD_DTR_STR_RESET

#define UDMA_HYPER_OSPI_CFG_CMD_DTR_STR_WIDTH

#define UDMA_HYPER_OSPI_CFG_CMD_SIZE_BIT

#define UDMA_HYPER_OSPI_CFG_CMD_SIZE_MASK

#define UDMA_HYPER_OSPI_CFG_CMD_SIZE_RESET

#define UDMA_HYPER_OSPI_CFG_CMD_SIZE_WIDTH

#define UDMA_HYPER_OSPI_CFG_DATA_DTR_MSB_BIT

#define UDMA_HYPER_OSPI_CFG_DATA_DTR_MSB_MASK

#define UDMA_HYPER_OSPI_CFG_DATA_DTR_MSB_RESET

#define UDMA_HYPER_OSPI_CFG_DATA_DTR_MSB_WIDTH

#define UDMA_HYPER_OSPI_CFG_DATA_DTR_STR_BIT

#define UDMA_HYPER_OSPI_CFG_DATA_DTR_STR_MASK

#define UDMA_HYPER_OSPI_CFG_DATA_DTR_STR_RESET

#define UDMA_HYPER_OSPI_CFG_DATA_DTR_STR_WIDTH

#define UDMA_HYPER_OSPI_CFG_LINE_BIT

#define UDMA_HYPER_OSPI_CFG_LINE_MASK

#define UDMA_HYPER_OSPI_CFG_LINE_RESET

#define UDMA_HYPER_OSPI_CFG_LINE_WIDTH

#define UDMA_HYPER_OSPI_CFG_XIP_ADDR_DTR_STR_BIT

#define UDMA_HYPER_OSPI_CFG_XIP_ADDR_DTR_STR_MASK

#define UDMA_HYPER_OSPI_CFG_XIP_ADDR_DTR_STR_RESET

#define UDMA_HYPER_OSPI_CFG_XIP_ADDR_DTR_STR_WIDTH

#define UDMA_HYPER_OSPI_CFG_XIP_ADDR_SIZE_BIT

#define UDMA_HYPER_OSPI_CFG_XIP_ADDR_SIZE_MASK

#define UDMA_HYPER_OSPI_CFG_XIP_ADDR_SIZE_RESET

#define UDMA_HYPER_OSPI_CFG_XIP_ADDR_SIZE_WIDTH

#define UDMA_HYPER_OSPI_CFG_XIP_CMD_DTR_STR_BIT

#define UDMA_HYPER_OSPI_CFG_XIP_CMD_DTR_STR_MASK

#define UDMA_HYPER_OSPI_CFG_XIP_CMD_DTR_STR_RESET

#define UDMA_HYPER_OSPI_CFG_XIP_CMD_DTR_STR_WIDTH

#define UDMA_HYPER_OSPI_CFG_XIP_CMD_SIZE_BIT

#define UDMA_HYPER_OSPI_CFG_XIP_CMD_SIZE_MASK

#define UDMA_HYPER_OSPI_CFG_XIP_CMD_SIZE_RESET

#define UDMA_HYPER_OSPI_CFG_XIP_CMD_SIZE_WIDTH

#define UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_MSB_BIT

#define UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_MSB_MASK

#define UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_MSB_RESET

#define UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_MSB_WIDTH

#define UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_STR_BIT

#define UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_STR_MASK

#define UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_STR_RESET

#define UDMA_HYPER_OSPI_CFG_XIP_DATA_DTR_STR_WIDTH

#define UDMA_HYPER_OSPI_CFG_XIP_LINE_BIT

#define UDMA_HYPER_OSPI_CFG_XIP_LINE_MASK

#define UDMA_HYPER_OSPI_CFG_XIP_LINE_RESET

#define UDMA_HYPER_OSPI_CFG_XIP_LINE_WIDTH

#define UDMA_HYPER_OSPI_CMD_CMD_BIT

#define UDMA_HYPER_OSPI_CMD_CMD_MASK

Referenced by __pi_octospi_ospi_config_set(), hal_udma_hyperbus_ospi_cmd_set(), and hal_udma_hyperbus_ospi_cmd_xip_set().

#define UDMA_HYPER_OSPI_CMD_CMD_RESET

#define UDMA_HYPER_OSPI_CMD_CMD_WIDTH

Referenced by hal_udma_hyperbus_ospi_cmd_set(), and hal_udma_hyperbus_ospi_cmd_xip_set().

#define UDMA_HYPER_OSPI_CMD_SDIO_CMD_OP_BIT

#define UDMA_HYPER_OSPI_CMD_SDIO_CMD_OP_MASK

#define UDMA_HYPER_OSPI_CMD_SDIO_CMD_OP_RESET

#define UDMA_HYPER_OSPI_CMD_SDIO_CMD_OP_WIDTH

#define UDMA_HYPER_OSPI_CMD_SDIO_CMD_RSP_TYPE_BIT

#define UDMA_HYPER_OSPI_CMD_SDIO_CMD_RSP_TYPE_MASK

#define UDMA_HYPER_OSPI_CMD_SDIO_CMD_RSP_TYPE_RESET

#define UDMA_HYPER_OSPI_CMD_SDIO_CMD_RSP_TYPE_WIDTH

#define UDMA_HYPER_OSPI_CMD_XIP_CMD_BIT

#define UDMA_HYPER_OSPI_CMD_XIP_CMD_MASK

#define UDMA_HYPER_OSPI_CMD_XIP_CMD_RESET

#define UDMA_HYPER_OSPI_CMD_XIP_CMD_WIDTH

#define UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_OP_BIT

#define UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_OP_MASK

#define UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_OP_RESET

#define UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_OP_WIDTH

#define UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_RSP_TYPE_BIT

#define UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_RSP_TYPE_MASK

#define UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_RSP_TYPE_RESET

#define UDMA_HYPER_OSPI_CMD_XIP_SDIO_CMD_RSP_TYPE_WIDTH

#define UDMA_HYPER_OSPI_CSN_AUTO_EN_BIT

#define UDMA_HYPER_OSPI_CSN_AUTO_EN_MASK

#define UDMA_HYPER_OSPI_CSN_AUTO_EN_RESET

#define UDMA_HYPER_OSPI_CSN_AUTO_EN_WIDTH

#define UDMA_HYPER_OSPI_CSN_DIRECT_CTRL_BIT

#define UDMA_HYPER_OSPI_CSN_DIRECT_CTRL_MASK

#define UDMA_HYPER_OSPI_CSN_DIRECT_CTRL_RESET

#define UDMA_HYPER_OSPI_CSN_DIRECT_CTRL_WIDTH

#define UDMA_HYPER_OSPI_CSN_INDEX_BIT

#define UDMA_HYPER_OSPI_CSN_INDEX_MASK

#define UDMA_HYPER_OSPI_CSN_INDEX_RESET

#define UDMA_HYPER_OSPI_CSN_INDEX_WIDTH

#define UDMA_HYPER_OSPI_CSN_RESERVED_BIT

#define UDMA_HYPER_OSPI_CSN_RESERVED_MASK

#define UDMA_HYPER_OSPI_CSN_RESERVED_RESET

#define UDMA_HYPER_OSPI_CSN_RESERVED_WIDTH

#define UDMA_HYPER_OSPI_CSN_SDIO_AUTO_STOP_BIT

#define UDMA_HYPER_OSPI_CSN_SDIO_AUTO_STOP_MASK

#define UDMA_HYPER_OSPI_CSN_SDIO_AUTO_STOP_RESET

#define UDMA_HYPER_OSPI_CSN_SDIO_AUTO_STOP_WIDTH

#define UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_NUM_BIT

#define UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_NUM_MASK

#define UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_NUM_RESET

#define UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_NUM_WIDTH

#define UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_SIZE_BIT

#define UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_SIZE_MASK

#define UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_SIZE_RESET

#define UDMA_HYPER_OSPI_CSN_SDIO_BLOCK_SIZE_WIDTH

#define UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_BIT

#define UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_DDR_BIT

#define UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_DDR_MASK

#define UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_DDR_RESET

#define UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_DDR_WIDTH

#define UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_MASK

#define UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_RESET

#define UDMA_HYPER_OSPI_CSN_SDIO_DATA_QUAD_WIDTH

#define UDMA_HYPER_OSPI_CSN_VALUE_BIT

#define UDMA_HYPER_OSPI_CSN_VALUE_MASK

#define UDMA_HYPER_OSPI_CSN_VALUE_RESET

#define UDMA_HYPER_OSPI_CSN_VALUE_WIDTH

#define UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_EN_BIT

#define UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_EN_MASK

#define UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_EN_RESET

#define UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_EN_WIDTH

#define UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_VALUE_BIT

#define UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_VALUE_MASK

#define UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_VALUE_RESET

#define UDMA_HYPER_OSPI_JEDEC_RESET_USER_CTRL_SDO0_VALUE_WIDTH

#define UDMA_HYPER_OSPI_RAM_OPT_OPT_READ_EN_CS_BIT

#define UDMA_HYPER_OSPI_RAM_OPT_OPT_READ_EN_CS_MASK

#define UDMA_HYPER_OSPI_RAM_OPT_OPT_READ_EN_CS_RESET

#define UDMA_HYPER_OSPI_RAM_OPT_OPT_READ_EN_CS_WIDTH

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_ADDR_EVEN_BIT

Referenced by __pi_octospi_ospi_config_set().

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_ADDR_EVEN_MASK

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_ADDR_EVEN_RESET

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_ADDR_EVEN_WIDTH

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CMD_EN_BIT

Referenced by __pi_octospi_ospi_config_set().

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CMD_EN_MASK

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CMD_EN_RESET

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CMD_EN_WIDTH

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CROSS_BOUNDARY_EN_BIT

Referenced by __pi_octospi_device_settings_set().

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CROSS_BOUNDARY_EN_MASK

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CROSS_BOUNDARY_EN_RESET

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_CROSS_BOUNDARY_EN_WIDTH

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_READ_BIT_BIT

Referenced by __pi_octospi_ospi_config_set().

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_READ_BIT_MASK

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_READ_BIT_RESET

#define UDMA_HYPER_OSPI_RAM_OPT_PSRAM_READ_BIT_WIDTH

#define UDMA_HYPER_OSPI_RAM_OPT_REAL_ADDR_EN_BIT

Referenced by __pi_octospi_device_settings_set().

#define UDMA_HYPER_OSPI_RAM_OPT_REAL_ADDR_EN_MASK

#define UDMA_HYPER_OSPI_RAM_OPT_REAL_ADDR_EN_RESET

#define UDMA_HYPER_OSPI_RAM_OPT_REAL_ADDR_EN_WIDTH

#define UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY0_BIT

#define UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY0_MASK

#define UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY0_RESET

#define UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY0_WIDTH

#define UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY1_BIT

#define UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY1_MASK

#define UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY1_RESET

#define UDMA_HYPER_OSPI_REG_XIP_XIP_LATENCY1_WIDTH

#define UDMA_HYPER_RX_DEST_DEST_BIT

#define UDMA_HYPER_RX_DEST_DEST_MASK

#define UDMA_HYPER_RX_DEST_DEST_RESET

#define UDMA_HYPER_RX_DEST_DEST_STREAM_BIT

#define UDMA_HYPER_RX_DEST_DEST_STREAM_MASK

#define UDMA_HYPER_RX_DEST_DEST_STREAM_RESET

#define UDMA_HYPER_RX_DEST_DEST_STREAM_WIDTH

#define UDMA_HYPER_RX_DEST_DEST_WIDTH

#define UDMA_HYPER_SDIO_CMD_ARG_ARG_BIT

#define UDMA_HYPER_SDIO_CMD_ARG_ARG_MASK

#define UDMA_HYPER_SDIO_CMD_ARG_ARG_RESET

#define UDMA_HYPER_SDIO_CMD_ARG_ARG_WIDTH

#define UDMA_HYPER_SDIO_RSP0_RSP0_BIT

#define UDMA_HYPER_SDIO_RSP0_RSP0_MASK

#define UDMA_HYPER_SDIO_RSP0_RSP0_RESET

#define UDMA_HYPER_SDIO_RSP0_RSP0_WIDTH

#define UDMA_HYPER_SDIO_RSP1_RSP1_BIT

#define UDMA_HYPER_SDIO_RSP1_RSP1_MASK

#define UDMA_HYPER_SDIO_RSP1_RSP1_RESET

#define UDMA_HYPER_SDIO_RSP1_RSP1_WIDTH

#define UDMA_HYPER_SDIO_RSP2_RSP2_BIT

#define UDMA_HYPER_SDIO_RSP2_RSP2_MASK

#define UDMA_HYPER_SDIO_RSP2_RSP2_RESET

#define UDMA_HYPER_SDIO_RSP2_RSP2_WIDTH

#define UDMA_HYPER_SDIO_RSP3_RSP3_BIT

#define UDMA_HYPER_SDIO_RSP3_RSP3_MASK

#define UDMA_HYPER_SDIO_RSP3_RSP3_RESET

#define UDMA_HYPER_SDIO_RSP3_RSP3_WIDTH

#define UDMA_HYPER_STATUS_RESERVED_BIT

#define UDMA_HYPER_STATUS_RESERVED_MASK

#define UDMA_HYPER_STATUS_RESERVED_RESET

#define UDMA_HYPER_STATUS_RESERVED_WIDTH

#define UDMA_HYPER_STATUS_RX_ERROR_BIT

#define UDMA_HYPER_STATUS_RX_ERROR_MASK

#define UDMA_HYPER_STATUS_RX_ERROR_RESET

#define UDMA_HYPER_STATUS_RX_ERROR_WIDTH

#define UDMA_HYPER_STATUS_RX_TX_END_BIT

#define UDMA_HYPER_STATUS_RX_TX_END_MASK

#define UDMA_HYPER_STATUS_RX_TX_END_RESET

#define UDMA_HYPER_STATUS_RX_TX_END_WIDTH

#define UDMA_HYPER_STATUS_SDIO_ERROR_STATUS_BIT

#define UDMA_HYPER_STATUS_SDIO_ERROR_STATUS_MASK

#define UDMA_HYPER_STATUS_SDIO_ERROR_STATUS_RESET

#define UDMA_HYPER_STATUS_SDIO_ERROR_STATUS_WIDTH

#define UDMA_HYPER_STATUS_SDIO_RX_TX_END_BIT

#define UDMA_HYPER_STATUS_SDIO_RX_TX_END_MASK

#define UDMA_HYPER_STATUS_SDIO_RX_TX_END_RESET

#define UDMA_HYPER_STATUS_SDIO_RX_TX_END_WIDTH

#define UDMA_HYPER_STATUS_SDIO_RX_TX_ERROR_BIT

#define UDMA_HYPER_STATUS_SDIO_RX_TX_ERROR_MASK

#define UDMA_HYPER_STATUS_SDIO_RX_TX_ERROR_RESET

#define UDMA_HYPER_STATUS_SDIO_RX_TX_ERROR_WIDTH

#define UDMA_HYPER_STATUS_TX_ERROR_BIT

#define UDMA_HYPER_STATUS_TX_ERROR_MASK

#define UDMA_HYPER_STATUS_TX_ERROR_RESET

#define UDMA_HYPER_STATUS_TX_ERROR_WIDTH

#define UDMA_HYPER_STRIDE_2D_STRIDE_BIT

#define UDMA_HYPER_STRIDE_2D_STRIDE_MASK

#define UDMA_HYPER_STRIDE_2D_STRIDE_RESET

#define UDMA_HYPER_STRIDE_2D_STRIDE_WIDTH

#define UDMA_HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_BIT

#define UDMA_HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_MASK

#define UDMA_HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_RESET

#define UDMA_HYPER_TIMING_CFG_ADDITIONAL_LATENCY_AUTOCHECK_EN_WIDTH

#define UDMA_HYPER_TIMING_CFG_CS_MAX_BIT

#define UDMA_HYPER_TIMING_CFG_CS_MAX_MASK

#define UDMA_HYPER_TIMING_CFG_CS_MAX_RESET

#define UDMA_HYPER_TIMING_CFG_CS_MAX_WIDTH

#define UDMA_HYPER_TIMING_CFG_LATENCY0_BIT

#define UDMA_HYPER_TIMING_CFG_LATENCY0_MASK

Referenced by __pi_octospi_ospi_config_set().

#define UDMA_HYPER_TIMING_CFG_LATENCY0_RESET

#define UDMA_HYPER_TIMING_CFG_LATENCY0_WIDTH

#define UDMA_HYPER_TIMING_CFG_LATENCY1_BIT

#define UDMA_HYPER_TIMING_CFG_LATENCY1_MASK

#define UDMA_HYPER_TIMING_CFG_LATENCY1_RESET

#define UDMA_HYPER_TIMING_CFG_LATENCY1_WIDTH

#define UDMA_HYPER_TIMING_CFG_RW_RECOVERY_BIT

#define UDMA_HYPER_TIMING_CFG_RW_RECOVERY_MASK

#define UDMA_HYPER_TIMING_CFG_RW_RECOVERY_RESET

#define UDMA_HYPER_TIMING_CFG_RW_RECOVERY_WIDTH

#define UDMA_HYPER_TIMING_CFG_RWDS_DELAY_BIT

#define UDMA_HYPER_TIMING_CFG_RWDS_DELAY_MASK

#define UDMA_HYPER_TIMING_CFG_RWDS_DELAY_RESET

#define UDMA_HYPER_TIMING_CFG_RWDS_DELAY_WIDTH

#define UDMA_HYPER_TRANS_ADDR_ADDR_BIT

#define UDMA_HYPER_TRANS_ADDR_ADDR_MASK

#define UDMA_HYPER_TRANS_ADDR_ADDR_RESET

#define UDMA_HYPER_TRANS_ADDR_ADDR_WIDTH

#define UDMA_HYPER_TRANS_CFG_RXTX_BIT

#define UDMA_HYPER_TRANS_CFG_RXTX_MASK

#define UDMA_HYPER_TRANS_CFG_RXTX_RESET

#define UDMA_HYPER_TRANS_CFG_RXTX_WIDTH

#define UDMA_HYPER_TRANS_CFG_VALID_BIT

#define UDMA_HYPER_TRANS_CFG_VALID_MASK

#define UDMA_HYPER_TRANS_CFG_VALID_RESET

#define UDMA_HYPER_TRANS_CFG_VALID_WIDTH

#define UDMA_HYPER_TRANS_MODE_AUTO_ENA_BIT

#define UDMA_HYPER_TRANS_MODE_AUTO_ENA_MASK

#define UDMA_HYPER_TRANS_MODE_AUTO_ENA_RESET

#define UDMA_HYPER_TRANS_MODE_AUTO_ENA_WIDTH

#define UDMA_HYPER_TRANS_MODE_STREAM_EN_BIT

#define UDMA_HYPER_TRANS_MODE_STREAM_EN_MASK

#define UDMA_HYPER_TRANS_MODE_STREAM_EN_RESET

#define UDMA_HYPER_TRANS_MODE_STREAM_EN_WIDTH

#define UDMA_HYPER_TRANS_MODE_STREAM_XIP_EN_BIT

#define UDMA_HYPER_TRANS_MODE_STREAM_XIP_EN_MASK

#define UDMA_HYPER_TRANS_MODE_STREAM_XIP_EN_RESET

#define UDMA_HYPER_TRANS_MODE_STREAM_XIP_EN_WIDTH

#define UDMA_HYPER_TRANS_MODE_XIP_EN_BIT

#define UDMA_HYPER_TRANS_MODE_XIP_EN_MASK

#define UDMA_HYPER_TRANS_MODE_XIP_EN_RESET

#define UDMA_HYPER_TRANS_MODE_XIP_EN_WIDTH

#define UDMA_HYPER_TRANS_MODE_XIP_HALTED_BIT

#define UDMA_HYPER_TRANS_MODE_XIP_HALTED_MASK

#define UDMA_HYPER_TRANS_MODE_XIP_HALTED_RESET

#define UDMA_HYPER_TRANS_MODE_XIP_HALTED_WIDTH

#define UDMA_HYPER_TRANS_SIZE_SIZE_BIT

#define UDMA_HYPER_TRANS_SIZE_SIZE_MASK

#define UDMA_HYPER_TRANS_SIZE_SIZE_RESET

#define UDMA_HYPER_TRANS_SIZE_SIZE_WIDTH

#define UDMA_HYPER_TX_DEST_DEST_BIT

#define UDMA_HYPER_TX_DEST_DEST_MASK

#define UDMA_HYPER_TX_DEST_DEST_RESET

#define UDMA_HYPER_TX_DEST_DEST_STREAM_BIT

#define UDMA_HYPER_TX_DEST_DEST_STREAM_MASK

#define UDMA_HYPER_TX_DEST_DEST_STREAM_RESET

#define UDMA_HYPER_TX_DEST_DEST_STREAM_WIDTH

#define UDMA_HYPER_TX_DEST_DEST_WIDTH