udma_core_periph.h File Reference

Data Structures
struct	udma_core_t
union	udma_core_rx_saddr_t
union	udma_core_rx_size_t
union	udma_core_rx_cfg_t
union	udma_core_rx_initcfg_t
union	udma_core_tx_saddr_t
union	udma_core_tx_size_t
union	udma_core_tx_cfg_t
union	udma_core_tx_initcfg_t

Macros
RX_SADDR
#define	UDMA_CORE_RX_SADDR_RX_SADDR_MASK
#define	UDMA_CORE_RX_SADDR_RX_SADDR_SHIFT
#define	UDMA_CORE_RX_SADDR_RX_SADDR(val)
#define	UDMA_CORE_RX_SADDR_RESERVED_0_MASK
#define	UDMA_CORE_RX_SADDR_RESERVED_0_SHIFT
#define	UDMA_CORE_RX_SADDR_RESERVED_0(val)
RX_SIZE
#define	UDMA_CORE_RX_SIZE_RX_SIZE_MASK
#define	UDMA_CORE_RX_SIZE_RX_SIZE_SHIFT
#define	UDMA_CORE_RX_SIZE_RX_SIZE(val)
#define	UDMA_CORE_RX_SIZE_RESERVED_0_MASK
#define	UDMA_CORE_RX_SIZE_RESERVED_0_SHIFT
#define	UDMA_CORE_RX_SIZE_RESERVED_0(val)
RX_CFG
#define	UDMA_CORE_RX_CFG_CONTINOUS_MASK
#define	UDMA_CORE_RX_CFG_CONTINOUS_SHIFT
#define	UDMA_CORE_RX_CFG_CONTINOUS(val)
#define	UDMA_CORE_RX_CFG_DATASIZE_MASK
#define	UDMA_CORE_RX_CFG_DATASIZE_SHIFT
#define	UDMA_CORE_RX_CFG_DATASIZE(val)
#define	UDMA_CORE_RX_CFG_RESERVED_0_MASK
#define	UDMA_CORE_RX_CFG_RESERVED_0_SHIFT
#define	UDMA_CORE_RX_CFG_RESERVED_0(val)
#define	UDMA_CORE_RX_CFG_EN_MASK
#define	UDMA_CORE_RX_CFG_EN_SHIFT
#define	UDMA_CORE_RX_CFG_EN(val)
#define	UDMA_CORE_RX_CFG_PENDING_MASK
#define	UDMA_CORE_RX_CFG_PENDING_SHIFT
#define	UDMA_CORE_RX_CFG_PENDING(val)
#define	UDMA_CORE_RX_CFG_CLR_MASK
#define	UDMA_CORE_RX_CFG_CLR_SHIFT
#define	UDMA_CORE_RX_CFG_CLR(val)
#define	UDMA_CORE_RX_CFG_RESERVED_1_MASK
#define	UDMA_CORE_RX_CFG_RESERVED_1_SHIFT
#define	UDMA_CORE_RX_CFG_RESERVED_1(val)
RX_INITCFG
#define	UDMA_CORE_RX_INITCFG_RESERVED_0_MASK
#define	UDMA_CORE_RX_INITCFG_RESERVED_0_SHIFT
#define	UDMA_CORE_RX_INITCFG_RESERVED_0(val)
TX_SADDR
#define	UDMA_CORE_TX_SADDR_TX_SADDR_MASK
#define	UDMA_CORE_TX_SADDR_TX_SADDR_SHIFT
#define	UDMA_CORE_TX_SADDR_TX_SADDR(val)
#define	UDMA_CORE_TX_SADDR_RESERVED_0_MASK
#define	UDMA_CORE_TX_SADDR_RESERVED_0_SHIFT
#define	UDMA_CORE_TX_SADDR_RESERVED_0(val)
TX_SIZE
#define	UDMA_CORE_TX_SIZE_TX_SIZE_MASK
#define	UDMA_CORE_TX_SIZE_TX_SIZE_SHIFT
#define	UDMA_CORE_TX_SIZE_TX_SIZE(val)
#define	UDMA_CORE_TX_SIZE_RESERVED_0_MASK
#define	UDMA_CORE_TX_SIZE_RESERVED_0_SHIFT
#define	UDMA_CORE_TX_SIZE_RESERVED_0(val)
TX_CFG
#define	UDMA_CORE_TX_CFG_CONTINOUS_MASK
#define	UDMA_CORE_TX_CFG_CONTINOUS_SHIFT
#define	UDMA_CORE_TX_CFG_CONTINOUS(val)
#define	UDMA_CORE_TX_CFG_DATASIZE_MASK
#define	UDMA_CORE_TX_CFG_DATASIZE_SHIFT
#define	UDMA_CORE_TX_CFG_DATASIZE(val)
#define	UDMA_CORE_TX_CFG_RESERVED_0_MASK
#define	UDMA_CORE_TX_CFG_RESERVED_0_SHIFT
#define	UDMA_CORE_TX_CFG_RESERVED_0(val)
#define	UDMA_CORE_TX_CFG_EN_MASK
#define	UDMA_CORE_TX_CFG_EN_SHIFT
#define	UDMA_CORE_TX_CFG_EN(val)
#define	UDMA_CORE_TX_CFG_PENDING_MASK
#define	UDMA_CORE_TX_CFG_PENDING_SHIFT
#define	UDMA_CORE_TX_CFG_PENDING(val)
#define	UDMA_CORE_TX_CFG_CLR_MASK
#define	UDMA_CORE_TX_CFG_CLR_SHIFT
#define	UDMA_CORE_TX_CFG_CLR(val)
#define	UDMA_CORE_TX_CFG_RESERVED_1_MASK
#define	UDMA_CORE_TX_CFG_RESERVED_1_SHIFT
#define	UDMA_CORE_TX_CFG_RESERVED_1(val)
TX_INITCFG
#define	UDMA_CORE_TX_INITCFG_RESERVED_0_MASK
#define	UDMA_CORE_TX_INITCFG_RESERVED_0_SHIFT
#define	UDMA_CORE_TX_INITCFG_RESERVED_0(val)
#define	UDMA_CORE_CFG_DATASIZE_8
#define	UDMA_CORE_CFG_DATASIZE_16
#define	UDMA_CORE_CFG_DATASIZE_32

Macro Definition Documentation

#define UDMA_CORE_CFG_DATASIZE_16

#define UDMA_CORE_CFG_DATASIZE_32

#define UDMA_CORE_CFG_DATASIZE_8

#define UDMA_CORE_RX_CFG_CLR

(

val

)

Referenced by udma_channel_clear().

#define UDMA_CORE_RX_CFG_CLR_MASK

#define UDMA_CORE_RX_CFG_CLR_SHIFT

#define UDMA_CORE_RX_CFG_CONTINOUS

(

val

)

#define UDMA_CORE_RX_CFG_CONTINOUS_MASK

#define UDMA_CORE_RX_CFG_CONTINOUS_SHIFT

#define UDMA_CORE_RX_CFG_DATASIZE

(

val

)

Referenced by __pi_cpi_copy(), and __pi_i2s_open().

#define UDMA_CORE_RX_CFG_DATASIZE_MASK

#define UDMA_CORE_RX_CFG_DATASIZE_SHIFT

#define UDMA_CORE_RX_CFG_EN

(

val

)

Referenced by __pi_cpi_copy(), __pi_i2c_copy_exec_read(), __pi_i2c_detect(), __pi_i2s_open(), __pi_spi_receive_async(), __pi_spi_receive_async_with_ucode(), __pi_spi_xfer_async(), __spi_cpy_read_aligned(), __spi_cpy_read_misaligned(), __spi_cpy_send_misaligned(), hal_dmacpy_enqueue(), hal_i2s_enqueue(), and hal_uart_enqueue().

#define UDMA_CORE_RX_CFG_EN_MASK

#define UDMA_CORE_RX_CFG_EN_SHIFT

#define UDMA_CORE_RX_CFG_PENDING

(

val

)

#define UDMA_CORE_RX_CFG_PENDING_MASK

Referenced by udma_channel_busy_get().

#define UDMA_CORE_RX_CFG_PENDING_SHIFT

Referenced by udma_channel_busy_get().

#define UDMA_CORE_RX_CFG_RESERVED_0

(

val

)

#define UDMA_CORE_RX_CFG_RESERVED_0_MASK

#define UDMA_CORE_RX_CFG_RESERVED_0_SHIFT

#define UDMA_CORE_RX_CFG_RESERVED_1

(

val

)

#define UDMA_CORE_RX_CFG_RESERVED_1_MASK

#define UDMA_CORE_RX_CFG_RESERVED_1_SHIFT

#define UDMA_CORE_RX_INITCFG_RESERVED_0

(

val

)

#define UDMA_CORE_RX_INITCFG_RESERVED_0_MASK

#define UDMA_CORE_RX_INITCFG_RESERVED_0_SHIFT

#define UDMA_CORE_RX_SADDR_RESERVED_0

(

val

)

#define UDMA_CORE_RX_SADDR_RESERVED_0_MASK

#define UDMA_CORE_RX_SADDR_RESERVED_0_SHIFT

#define UDMA_CORE_RX_SADDR_RX_SADDR

(

val

)

#define UDMA_CORE_RX_SADDR_RX_SADDR_MASK

#define UDMA_CORE_RX_SADDR_RX_SADDR_SHIFT

#define UDMA_CORE_RX_SIZE_RESERVED_0

(

val

)

#define UDMA_CORE_RX_SIZE_RESERVED_0_MASK

#define UDMA_CORE_RX_SIZE_RESERVED_0_SHIFT

#define UDMA_CORE_RX_SIZE_RX_SIZE

(

val

)

#define UDMA_CORE_RX_SIZE_RX_SIZE_MASK

#define UDMA_CORE_RX_SIZE_RX_SIZE_SHIFT

#define UDMA_CORE_TX_CFG_CLR

(

val

)

Referenced by udma_channel_clear().

#define UDMA_CORE_TX_CFG_CLR_MASK

#define UDMA_CORE_TX_CFG_CLR_SHIFT

#define UDMA_CORE_TX_CFG_CONTINOUS

(

val

)

#define UDMA_CORE_TX_CFG_CONTINOUS_MASK

#define UDMA_CORE_TX_CFG_CONTINOUS_SHIFT

#define UDMA_CORE_TX_CFG_DATASIZE

(

val

)

#define UDMA_CORE_TX_CFG_DATASIZE_MASK

#define UDMA_CORE_TX_CFG_DATASIZE_SHIFT

#define UDMA_CORE_TX_CFG_EN

(

val

)

Referenced by __pi_i2c_copy_exec_read(), __pi_i2c_copy_exec_write(), __pi_i2c_detect(), __pi_i2c_send_stop_cmd(), __pi_spi_receive_async(), __pi_spi_receive_async_with_ucode(), __pi_spi_send_async(), __pi_spi_send_async_with_ucode(), __pi_spi_xfer_async(), __spi_cpy_read_aligned(), __spi_cpy_read_misaligned(), __spi_cpy_send_aligned(), and __spi_cpy_send_misaligned().

#define UDMA_CORE_TX_CFG_EN_MASK

#define UDMA_CORE_TX_CFG_EN_SHIFT

#define UDMA_CORE_TX_CFG_PENDING

(

val

)

#define UDMA_CORE_TX_CFG_PENDING_MASK

Referenced by udma_channel_busy_get().

#define UDMA_CORE_TX_CFG_PENDING_SHIFT

Referenced by udma_channel_busy_get().

#define UDMA_CORE_TX_CFG_RESERVED_0

(

val

)

#define UDMA_CORE_TX_CFG_RESERVED_0_MASK

#define UDMA_CORE_TX_CFG_RESERVED_0_SHIFT

#define UDMA_CORE_TX_CFG_RESERVED_1

(

val

)

#define UDMA_CORE_TX_CFG_RESERVED_1_MASK

#define UDMA_CORE_TX_CFG_RESERVED_1_SHIFT

#define UDMA_CORE_TX_INITCFG_RESERVED_0

(

val

)

#define UDMA_CORE_TX_INITCFG_RESERVED_0_MASK

#define UDMA_CORE_TX_INITCFG_RESERVED_0_SHIFT

#define UDMA_CORE_TX_SADDR_RESERVED_0

(

val

)

#define UDMA_CORE_TX_SADDR_RESERVED_0_MASK

#define UDMA_CORE_TX_SADDR_RESERVED_0_SHIFT

#define UDMA_CORE_TX_SADDR_TX_SADDR

(

val

)

#define UDMA_CORE_TX_SADDR_TX_SADDR_MASK

#define UDMA_CORE_TX_SADDR_TX_SADDR_SHIFT

#define UDMA_CORE_TX_SIZE_RESERVED_0

(

val

)

#define UDMA_CORE_TX_SIZE_RESERVED_0_MASK

#define UDMA_CORE_TX_SIZE_RESERVED_0_SHIFT

#define UDMA_CORE_TX_SIZE_TX_SIZE

(

val

)

#define UDMA_CORE_TX_SIZE_TX_SIZE_MASK

#define UDMA_CORE_TX_SIZE_TX_SIZE_SHIFT