udma_asrc_regfields.h File Reference

Macros
#define	UDMA_ASRC_CTRL_CFG_0_CLK_EN_BIT
#define	UDMA_ASRC_CTRL_CFG_0_CLK_EN_WIDTH
#define	UDMA_ASRC_CTRL_CFG_0_CLK_EN_MASK
#define	UDMA_ASRC_CTRL_CFG_0_CLK_EN_RESET
#define	UDMA_ASRC_CTRL_CFG_0_RSTN_BIT
#define	UDMA_ASRC_CTRL_CFG_0_RSTN_WIDTH
#define	UDMA_ASRC_CTRL_CFG_0_RSTN_MASK
#define	UDMA_ASRC_CTRL_CFG_0_RSTN_RESET
#define	UDMA_ASRC_CTRL_CFG_0_FS_IN_BIT
#define	UDMA_ASRC_CTRL_CFG_0_FS_IN_WIDTH
#define	UDMA_ASRC_CTRL_CFG_0_FS_IN_MASK
#define	UDMA_ASRC_CTRL_CFG_0_FS_IN_RESET
#define	UDMA_ASRC_CTRL_CFG_0_FS_OUT_BIT
#define	UDMA_ASRC_CTRL_CFG_0_FS_OUT_WIDTH
#define	UDMA_ASRC_CTRL_CFG_0_FS_OUT_MASK
#define	UDMA_ASRC_CTRL_CFG_0_FS_OUT_RESET
#define	UDMA_ASRC_CTRL_CFG_0_LOCK_WND_BIT
#define	UDMA_ASRC_CTRL_CFG_0_LOCK_WND_WIDTH
#define	UDMA_ASRC_CTRL_CFG_0_LOCK_WND_MASK
#define	UDMA_ASRC_CTRL_CFG_0_LOCK_WND_RESET
#define	UDMA_ASRC_CTRL_CFG_1_CLK_EN_BIT
#define	UDMA_ASRC_CTRL_CFG_1_CLK_EN_WIDTH
#define	UDMA_ASRC_CTRL_CFG_1_CLK_EN_MASK
#define	UDMA_ASRC_CTRL_CFG_1_CLK_EN_RESET
#define	UDMA_ASRC_CTRL_CFG_1_RSTN_BIT
#define	UDMA_ASRC_CTRL_CFG_1_RSTN_WIDTH
#define	UDMA_ASRC_CTRL_CFG_1_RSTN_MASK
#define	UDMA_ASRC_CTRL_CFG_1_RSTN_RESET
#define	UDMA_ASRC_CTRL_CFG_1_FS_IN_BIT
#define	UDMA_ASRC_CTRL_CFG_1_FS_IN_WIDTH
#define	UDMA_ASRC_CTRL_CFG_1_FS_IN_MASK
#define	UDMA_ASRC_CTRL_CFG_1_FS_IN_RESET
#define	UDMA_ASRC_CTRL_CFG_1_FS_OUT_BIT
#define	UDMA_ASRC_CTRL_CFG_1_FS_OUT_WIDTH
#define	UDMA_ASRC_CTRL_CFG_1_FS_OUT_MASK
#define	UDMA_ASRC_CTRL_CFG_1_FS_OUT_RESET
#define	UDMA_ASRC_CTRL_CFG_1_LOCK_WND_BIT
#define	UDMA_ASRC_CTRL_CFG_1_LOCK_WND_WIDTH
#define	UDMA_ASRC_CTRL_CFG_1_LOCK_WND_MASK
#define	UDMA_ASRC_CTRL_CFG_1_LOCK_WND_RESET
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH0_BIT
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH0_WIDTH
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH0_MASK
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH0_RESET
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH1_BIT
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH1_WIDTH
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH1_MASK
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH1_RESET
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH2_BIT
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH2_WIDTH
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH2_MASK
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH2_RESET
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH3_BIT
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH3_WIDTH
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH3_MASK
#define	UDMA_ASRC_LANE_IDIN_0_ID_CH3_RESET
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH0_BIT
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH0_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH0_MASK
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH0_RESET
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH1_BIT
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH1_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH1_MASK
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH1_RESET
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH2_BIT
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH2_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH2_MASK
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH2_RESET
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH3_BIT
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH3_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH3_MASK
#define	UDMA_ASRC_LANE_IDOUT_0_ID_CH3_RESET
#define	UDMA_ASRC_LANE_CFG_0_CLK_EN_BIT
#define	UDMA_ASRC_LANE_CFG_0_CLK_EN_WIDTH
#define	UDMA_ASRC_LANE_CFG_0_CLK_EN_MASK
#define	UDMA_ASRC_LANE_CFG_0_CLK_EN_RESET
#define	UDMA_ASRC_LANE_CFG_0_RSTN_BIT
#define	UDMA_ASRC_LANE_CFG_0_RSTN_WIDTH
#define	UDMA_ASRC_LANE_CFG_0_RSTN_MASK
#define	UDMA_ASRC_LANE_CFG_0_RSTN_RESET
#define	UDMA_ASRC_LANE_CFG_0_CTRL_MUX_BIT
#define	UDMA_ASRC_LANE_CFG_0_CTRL_MUX_WIDTH
#define	UDMA_ASRC_LANE_CFG_0_CTRL_MUX_MASK
#define	UDMA_ASRC_LANE_CFG_0_CTRL_MUX_RESET
#define	UDMA_ASRC_LANE_CFG_0_USE_STREAM_IN_BIT
#define	UDMA_ASRC_LANE_CFG_0_USE_STREAM_IN_WIDTH
#define	UDMA_ASRC_LANE_CFG_0_USE_STREAM_IN_MASK
#define	UDMA_ASRC_LANE_CFG_0_USE_STREAM_IN_RESET
#define	UDMA_ASRC_LANE_CFG_0_USE_STREAM_OUT_BIT
#define	UDMA_ASRC_LANE_CFG_0_USE_STREAM_OUT_WIDTH
#define	UDMA_ASRC_LANE_CFG_0_USE_STREAM_OUT_MASK
#define	UDMA_ASRC_LANE_CFG_0_USE_STREAM_OUT_RESET
#define	UDMA_ASRC_LANE_CFG_0_CH_EN_BIT
#define	UDMA_ASRC_LANE_CFG_0_CH_EN_WIDTH
#define	UDMA_ASRC_LANE_CFG_0_CH_EN_MASK
#define	UDMA_ASRC_LANE_CFG_0_CH_EN_RESET
#define	UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_IN_BIT
#define	UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_IN_WIDTH
#define	UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_IN_MASK
#define	UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_IN_RESET
#define	UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_OUT_BIT
#define	UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_OUT_WIDTH
#define	UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_OUT_MASK
#define	UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_OUT_RESET
#define	UDMA_ASRC_LANE_CFG_0_DROP_ON_WAIT_BIT
#define	UDMA_ASRC_LANE_CFG_0_DROP_ON_WAIT_WIDTH
#define	UDMA_ASRC_LANE_CFG_0_DROP_ON_WAIT_MASK
#define	UDMA_ASRC_LANE_CFG_0_DROP_ON_WAIT_RESET
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH0_BIT
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH0_WIDTH
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH0_MASK
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH0_RESET
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH1_BIT
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH1_WIDTH
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH1_MASK
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH1_RESET
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH2_BIT
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH2_WIDTH
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH2_MASK
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH2_RESET
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH3_BIT
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH3_WIDTH
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH3_MASK
#define	UDMA_ASRC_LANE_IDIN_1_ID_CH3_RESET
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH0_BIT
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH0_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH0_MASK
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH0_RESET
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH1_BIT
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH1_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH1_MASK
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH1_RESET
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH2_BIT
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH2_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH2_MASK
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH2_RESET
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH3_BIT
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH3_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH3_MASK
#define	UDMA_ASRC_LANE_IDOUT_1_ID_CH3_RESET
#define	UDMA_ASRC_LANE_CFG_1_CLK_EN_BIT
#define	UDMA_ASRC_LANE_CFG_1_CLK_EN_WIDTH
#define	UDMA_ASRC_LANE_CFG_1_CLK_EN_MASK
#define	UDMA_ASRC_LANE_CFG_1_CLK_EN_RESET
#define	UDMA_ASRC_LANE_CFG_1_RSTN_BIT
#define	UDMA_ASRC_LANE_CFG_1_RSTN_WIDTH
#define	UDMA_ASRC_LANE_CFG_1_RSTN_MASK
#define	UDMA_ASRC_LANE_CFG_1_RSTN_RESET
#define	UDMA_ASRC_LANE_CFG_1_CTRL_MUX_BIT
#define	UDMA_ASRC_LANE_CFG_1_CTRL_MUX_WIDTH
#define	UDMA_ASRC_LANE_CFG_1_CTRL_MUX_MASK
#define	UDMA_ASRC_LANE_CFG_1_CTRL_MUX_RESET
#define	UDMA_ASRC_LANE_CFG_1_USE_STREAM_IN_BIT
#define	UDMA_ASRC_LANE_CFG_1_USE_STREAM_IN_WIDTH
#define	UDMA_ASRC_LANE_CFG_1_USE_STREAM_IN_MASK
#define	UDMA_ASRC_LANE_CFG_1_USE_STREAM_IN_RESET
#define	UDMA_ASRC_LANE_CFG_1_USE_STREAM_OUT_BIT
#define	UDMA_ASRC_LANE_CFG_1_USE_STREAM_OUT_WIDTH
#define	UDMA_ASRC_LANE_CFG_1_USE_STREAM_OUT_MASK
#define	UDMA_ASRC_LANE_CFG_1_USE_STREAM_OUT_RESET
#define	UDMA_ASRC_LANE_CFG_1_CH_EN_BIT
#define	UDMA_ASRC_LANE_CFG_1_CH_EN_WIDTH
#define	UDMA_ASRC_LANE_CFG_1_CH_EN_MASK
#define	UDMA_ASRC_LANE_CFG_1_CH_EN_RESET
#define	UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_IN_BIT
#define	UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_IN_WIDTH
#define	UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_IN_MASK
#define	UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_IN_RESET
#define	UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_OUT_BIT
#define	UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_OUT_WIDTH
#define	UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_OUT_MASK
#define	UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_OUT_RESET
#define	UDMA_ASRC_LANE_CFG_1_DROP_ON_WAIT_BIT
#define	UDMA_ASRC_LANE_CFG_1_DROP_ON_WAIT_WIDTH
#define	UDMA_ASRC_LANE_CFG_1_DROP_ON_WAIT_MASK
#define	UDMA_ASRC_LANE_CFG_1_DROP_ON_WAIT_RESET
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH0_BIT
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH0_WIDTH
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH0_MASK
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH0_RESET
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH1_BIT
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH1_WIDTH
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH1_MASK
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH1_RESET
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH2_BIT
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH2_WIDTH
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH2_MASK
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH2_RESET
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH3_BIT
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH3_WIDTH
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH3_MASK
#define	UDMA_ASRC_LANE_IDIN_2_ID_CH3_RESET
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH0_BIT
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH0_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH0_MASK
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH0_RESET
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH1_BIT
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH1_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH1_MASK
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH1_RESET
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH2_BIT
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH2_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH2_MASK
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH2_RESET
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH3_BIT
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH3_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH3_MASK
#define	UDMA_ASRC_LANE_IDOUT_2_ID_CH3_RESET
#define	UDMA_ASRC_LANE_CFG_2_CLK_EN_BIT
#define	UDMA_ASRC_LANE_CFG_2_CLK_EN_WIDTH
#define	UDMA_ASRC_LANE_CFG_2_CLK_EN_MASK
#define	UDMA_ASRC_LANE_CFG_2_CLK_EN_RESET
#define	UDMA_ASRC_LANE_CFG_2_RSTN_BIT
#define	UDMA_ASRC_LANE_CFG_2_RSTN_WIDTH
#define	UDMA_ASRC_LANE_CFG_2_RSTN_MASK
#define	UDMA_ASRC_LANE_CFG_2_RSTN_RESET
#define	UDMA_ASRC_LANE_CFG_2_CTRL_MUX_BIT
#define	UDMA_ASRC_LANE_CFG_2_CTRL_MUX_WIDTH
#define	UDMA_ASRC_LANE_CFG_2_CTRL_MUX_MASK
#define	UDMA_ASRC_LANE_CFG_2_CTRL_MUX_RESET
#define	UDMA_ASRC_LANE_CFG_2_USE_STREAM_IN_BIT
#define	UDMA_ASRC_LANE_CFG_2_USE_STREAM_IN_WIDTH
#define	UDMA_ASRC_LANE_CFG_2_USE_STREAM_IN_MASK
#define	UDMA_ASRC_LANE_CFG_2_USE_STREAM_IN_RESET
#define	UDMA_ASRC_LANE_CFG_2_USE_STREAM_OUT_BIT
#define	UDMA_ASRC_LANE_CFG_2_USE_STREAM_OUT_WIDTH
#define	UDMA_ASRC_LANE_CFG_2_USE_STREAM_OUT_MASK
#define	UDMA_ASRC_LANE_CFG_2_USE_STREAM_OUT_RESET
#define	UDMA_ASRC_LANE_CFG_2_CH_EN_BIT
#define	UDMA_ASRC_LANE_CFG_2_CH_EN_WIDTH
#define	UDMA_ASRC_LANE_CFG_2_CH_EN_MASK
#define	UDMA_ASRC_LANE_CFG_2_CH_EN_RESET
#define	UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_IN_BIT
#define	UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_IN_WIDTH
#define	UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_IN_MASK
#define	UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_IN_RESET
#define	UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_OUT_BIT
#define	UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_OUT_WIDTH
#define	UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_OUT_MASK
#define	UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_OUT_RESET
#define	UDMA_ASRC_LANE_CFG_2_DROP_ON_WAIT_BIT
#define	UDMA_ASRC_LANE_CFG_2_DROP_ON_WAIT_WIDTH
#define	UDMA_ASRC_LANE_CFG_2_DROP_ON_WAIT_MASK
#define	UDMA_ASRC_LANE_CFG_2_DROP_ON_WAIT_RESET
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH0_BIT
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH0_WIDTH
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH0_MASK
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH0_RESET
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH1_BIT
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH1_WIDTH
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH1_MASK
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH1_RESET
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH2_BIT
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH2_WIDTH
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH2_MASK
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH2_RESET
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH3_BIT
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH3_WIDTH
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH3_MASK
#define	UDMA_ASRC_LANE_IDIN_3_ID_CH3_RESET
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH0_BIT
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH0_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH0_MASK
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH0_RESET
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH1_BIT
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH1_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH1_MASK
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH1_RESET
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH2_BIT
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH2_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH2_MASK
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH2_RESET
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH3_BIT
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH3_WIDTH
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH3_MASK
#define	UDMA_ASRC_LANE_IDOUT_3_ID_CH3_RESET
#define	UDMA_ASRC_LANE_CFG_3_CLK_EN_BIT
#define	UDMA_ASRC_LANE_CFG_3_CLK_EN_WIDTH
#define	UDMA_ASRC_LANE_CFG_3_CLK_EN_MASK
#define	UDMA_ASRC_LANE_CFG_3_CLK_EN_RESET
#define	UDMA_ASRC_LANE_CFG_3_RSTN_BIT
#define	UDMA_ASRC_LANE_CFG_3_RSTN_WIDTH
#define	UDMA_ASRC_LANE_CFG_3_RSTN_MASK
#define	UDMA_ASRC_LANE_CFG_3_RSTN_RESET
#define	UDMA_ASRC_LANE_CFG_3_CTRL_MUX_BIT
#define	UDMA_ASRC_LANE_CFG_3_CTRL_MUX_WIDTH
#define	UDMA_ASRC_LANE_CFG_3_CTRL_MUX_MASK
#define	UDMA_ASRC_LANE_CFG_3_CTRL_MUX_RESET
#define	UDMA_ASRC_LANE_CFG_3_USE_STREAM_IN_BIT
#define	UDMA_ASRC_LANE_CFG_3_USE_STREAM_IN_WIDTH
#define	UDMA_ASRC_LANE_CFG_3_USE_STREAM_IN_MASK
#define	UDMA_ASRC_LANE_CFG_3_USE_STREAM_IN_RESET
#define	UDMA_ASRC_LANE_CFG_3_USE_STREAM_OUT_BIT
#define	UDMA_ASRC_LANE_CFG_3_USE_STREAM_OUT_WIDTH
#define	UDMA_ASRC_LANE_CFG_3_USE_STREAM_OUT_MASK
#define	UDMA_ASRC_LANE_CFG_3_USE_STREAM_OUT_RESET
#define	UDMA_ASRC_LANE_CFG_3_CH_EN_BIT
#define	UDMA_ASRC_LANE_CFG_3_CH_EN_WIDTH
#define	UDMA_ASRC_LANE_CFG_3_CH_EN_MASK
#define	UDMA_ASRC_LANE_CFG_3_CH_EN_RESET
#define	UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_IN_BIT
#define	UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_IN_WIDTH
#define	UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_IN_MASK
#define	UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_IN_RESET
#define	UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_OUT_BIT
#define	UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_OUT_WIDTH
#define	UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_OUT_MASK
#define	UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_OUT_RESET
#define	UDMA_ASRC_LANE_CFG_3_DROP_ON_WAIT_BIT
#define	UDMA_ASRC_LANE_CFG_3_DROP_ON_WAIT_WIDTH
#define	UDMA_ASRC_LANE_CFG_3_DROP_ON_WAIT_MASK
#define	UDMA_ASRC_LANE_CFG_3_DROP_ON_WAIT_RESET
#define	UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH0_BIT
#define	UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH0_WIDTH
#define	UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH0_MASK
#define	UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH0_RESET
#define	UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH1_BIT
#define	UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH1_WIDTH
#define	UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH1_MASK
#define	UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH1_RESET
#define	UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH0_BIT
#define	UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH0_WIDTH
#define	UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH0_MASK
#define	UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH0_RESET
#define	UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH1_BIT
#define	UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH1_WIDTH
#define	UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH1_MASK
#define	UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH1_RESET
#define	UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_EN_BIT
#define	UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_EN_WIDTH
#define	UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_EN_MASK
#define	UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_EN_RESET
#define	UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_BIT
#define	UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_WIDTH
#define	UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_MASK
#define	UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_RESET
#define	UDMA_ASRC_MEM2MEM_CFG_CLK_EN_BIT
#define	UDMA_ASRC_MEM2MEM_CFG_CLK_EN_WIDTH
#define	UDMA_ASRC_MEM2MEM_CFG_CLK_EN_MASK
#define	UDMA_ASRC_MEM2MEM_CFG_CLK_EN_RESET
#define	UDMA_ASRC_MEM2MEM_CFG_RSTN_BIT
#define	UDMA_ASRC_MEM2MEM_CFG_RSTN_WIDTH
#define	UDMA_ASRC_MEM2MEM_CFG_RSTN_MASK
#define	UDMA_ASRC_MEM2MEM_CFG_RSTN_RESET
#define	UDMA_ASRC_MEM2MEM_CFG_CH_EN_BIT
#define	UDMA_ASRC_MEM2MEM_CFG_CH_EN_WIDTH
#define	UDMA_ASRC_MEM2MEM_CFG_CH_EN_MASK
#define	UDMA_ASRC_MEM2MEM_CFG_CH_EN_RESET
#define	UDMA_ASRC_MEM2MEM_CFG_FS_IN_BIT
#define	UDMA_ASRC_MEM2MEM_CFG_FS_IN_WIDTH
#define	UDMA_ASRC_MEM2MEM_CFG_FS_IN_MASK
#define	UDMA_ASRC_MEM2MEM_CFG_FS_IN_RESET
#define	UDMA_ASRC_MEM2MEM_CFG_FS_OUT_BIT
#define	UDMA_ASRC_MEM2MEM_CFG_FS_OUT_WIDTH
#define	UDMA_ASRC_MEM2MEM_CFG_FS_OUT_MASK
#define	UDMA_ASRC_MEM2MEM_CFG_FS_OUT_RESET
#define	UDMA_ASRC_MEM2MEM_CFG_STORE_BIT
#define	UDMA_ASRC_MEM2MEM_CFG_STORE_WIDTH
#define	UDMA_ASRC_MEM2MEM_CFG_STORE_MASK
#define	UDMA_ASRC_MEM2MEM_CFG_STORE_RESET
#define	UDMA_ASRC_MEM2MEM_CFG_RESTORE_BIT
#define	UDMA_ASRC_MEM2MEM_CFG_RESTORE_WIDTH
#define	UDMA_ASRC_MEM2MEM_CFG_RESTORE_MASK
#define	UDMA_ASRC_MEM2MEM_CFG_RESTORE_RESET
#define	UDMA_ASRC_MEM2MEM_CFG_CTX_ID_BIT
#define	UDMA_ASRC_MEM2MEM_CFG_CTX_ID_WIDTH
#define	UDMA_ASRC_MEM2MEM_CFG_CTX_ID_MASK
#define	UDMA_ASRC_MEM2MEM_CFG_CTX_ID_RESET
#define	UDMA_ASRC_STATUS_LOCK_BIT
#define	UDMA_ASRC_STATUS_LOCK_WIDTH
#define	UDMA_ASRC_STATUS_LOCK_MASK
#define	UDMA_ASRC_STATUS_LOCK_RESET

Macro Definition Documentation

#define UDMA_ASRC_CTRL_CFG_0_CLK_EN_BIT

#define UDMA_ASRC_CTRL_CFG_0_CLK_EN_MASK

Referenced by hal_udma_asrc_ctrl_cfg_disable().

#define UDMA_ASRC_CTRL_CFG_0_CLK_EN_RESET

#define UDMA_ASRC_CTRL_CFG_0_CLK_EN_WIDTH

#define UDMA_ASRC_CTRL_CFG_0_FS_IN_BIT

#define UDMA_ASRC_CTRL_CFG_0_FS_IN_MASK

#define UDMA_ASRC_CTRL_CFG_0_FS_IN_RESET

#define UDMA_ASRC_CTRL_CFG_0_FS_IN_WIDTH

#define UDMA_ASRC_CTRL_CFG_0_FS_OUT_BIT

#define UDMA_ASRC_CTRL_CFG_0_FS_OUT_MASK

#define UDMA_ASRC_CTRL_CFG_0_FS_OUT_RESET

#define UDMA_ASRC_CTRL_CFG_0_FS_OUT_WIDTH

#define UDMA_ASRC_CTRL_CFG_0_LOCK_WND_BIT

#define UDMA_ASRC_CTRL_CFG_0_LOCK_WND_MASK

#define UDMA_ASRC_CTRL_CFG_0_LOCK_WND_RESET

Referenced by hal_udma_asrc_ctrl_cfg_set().

#define UDMA_ASRC_CTRL_CFG_0_LOCK_WND_WIDTH

#define UDMA_ASRC_CTRL_CFG_0_RSTN_BIT

#define UDMA_ASRC_CTRL_CFG_0_RSTN_MASK

Referenced by hal_udma_asrc_ctrl_cfg_disable().

#define UDMA_ASRC_CTRL_CFG_0_RSTN_RESET

#define UDMA_ASRC_CTRL_CFG_0_RSTN_WIDTH

#define UDMA_ASRC_CTRL_CFG_1_CLK_EN_BIT

#define UDMA_ASRC_CTRL_CFG_1_CLK_EN_MASK

#define UDMA_ASRC_CTRL_CFG_1_CLK_EN_RESET

#define UDMA_ASRC_CTRL_CFG_1_CLK_EN_WIDTH

#define UDMA_ASRC_CTRL_CFG_1_FS_IN_BIT

#define UDMA_ASRC_CTRL_CFG_1_FS_IN_MASK

#define UDMA_ASRC_CTRL_CFG_1_FS_IN_RESET

#define UDMA_ASRC_CTRL_CFG_1_FS_IN_WIDTH

#define UDMA_ASRC_CTRL_CFG_1_FS_OUT_BIT

#define UDMA_ASRC_CTRL_CFG_1_FS_OUT_MASK

#define UDMA_ASRC_CTRL_CFG_1_FS_OUT_RESET

#define UDMA_ASRC_CTRL_CFG_1_FS_OUT_WIDTH

#define UDMA_ASRC_CTRL_CFG_1_LOCK_WND_BIT

#define UDMA_ASRC_CTRL_CFG_1_LOCK_WND_MASK

#define UDMA_ASRC_CTRL_CFG_1_LOCK_WND_RESET

#define UDMA_ASRC_CTRL_CFG_1_LOCK_WND_WIDTH

#define UDMA_ASRC_CTRL_CFG_1_RSTN_BIT

#define UDMA_ASRC_CTRL_CFG_1_RSTN_MASK

#define UDMA_ASRC_CTRL_CFG_1_RSTN_RESET

#define UDMA_ASRC_CTRL_CFG_1_RSTN_WIDTH

#define UDMA_ASRC_LANE_CFG_0_CH_EN_BIT

#define UDMA_ASRC_LANE_CFG_0_CH_EN_MASK

#define UDMA_ASRC_LANE_CFG_0_CH_EN_RESET

#define UDMA_ASRC_LANE_CFG_0_CH_EN_WIDTH

#define UDMA_ASRC_LANE_CFG_0_CLK_EN_BIT

#define UDMA_ASRC_LANE_CFG_0_CLK_EN_MASK

Referenced by hal_udma_asrc_lane_cfg_disable().

#define UDMA_ASRC_LANE_CFG_0_CLK_EN_RESET

#define UDMA_ASRC_LANE_CFG_0_CLK_EN_WIDTH

#define UDMA_ASRC_LANE_CFG_0_CTRL_MUX_BIT

#define UDMA_ASRC_LANE_CFG_0_CTRL_MUX_MASK

#define UDMA_ASRC_LANE_CFG_0_CTRL_MUX_RESET

#define UDMA_ASRC_LANE_CFG_0_CTRL_MUX_WIDTH

#define UDMA_ASRC_LANE_CFG_0_DROP_ON_WAIT_BIT

#define UDMA_ASRC_LANE_CFG_0_DROP_ON_WAIT_MASK

#define UDMA_ASRC_LANE_CFG_0_DROP_ON_WAIT_RESET

Referenced by hal_udma_asrc_lane_cfg_set().

#define UDMA_ASRC_LANE_CFG_0_DROP_ON_WAIT_WIDTH

#define UDMA_ASRC_LANE_CFG_0_RSTN_BIT

#define UDMA_ASRC_LANE_CFG_0_RSTN_MASK

Referenced by hal_udma_asrc_lane_cfg_disable().

#define UDMA_ASRC_LANE_CFG_0_RSTN_RESET

#define UDMA_ASRC_LANE_CFG_0_RSTN_WIDTH

#define UDMA_ASRC_LANE_CFG_0_USE_STREAM_IN_BIT

#define UDMA_ASRC_LANE_CFG_0_USE_STREAM_IN_MASK

#define UDMA_ASRC_LANE_CFG_0_USE_STREAM_IN_RESET

#define UDMA_ASRC_LANE_CFG_0_USE_STREAM_IN_WIDTH

#define UDMA_ASRC_LANE_CFG_0_USE_STREAM_OUT_BIT

#define UDMA_ASRC_LANE_CFG_0_USE_STREAM_OUT_MASK

#define UDMA_ASRC_LANE_CFG_0_USE_STREAM_OUT_RESET

#define UDMA_ASRC_LANE_CFG_0_USE_STREAM_OUT_WIDTH

#define UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_IN_BIT

#define UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_IN_MASK

#define UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_IN_RESET

Referenced by hal_udma_asrc_lane_cfg_set().

#define UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_IN_WIDTH

#define UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_OUT_BIT

#define UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_OUT_MASK

#define UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_OUT_RESET

Referenced by hal_udma_asrc_lane_cfg_set().

#define UDMA_ASRC_LANE_CFG_0_WAIT_LOCK_OUT_WIDTH

#define UDMA_ASRC_LANE_CFG_1_CH_EN_BIT

#define UDMA_ASRC_LANE_CFG_1_CH_EN_MASK

#define UDMA_ASRC_LANE_CFG_1_CH_EN_RESET

#define UDMA_ASRC_LANE_CFG_1_CH_EN_WIDTH

#define UDMA_ASRC_LANE_CFG_1_CLK_EN_BIT

#define UDMA_ASRC_LANE_CFG_1_CLK_EN_MASK

#define UDMA_ASRC_LANE_CFG_1_CLK_EN_RESET

#define UDMA_ASRC_LANE_CFG_1_CLK_EN_WIDTH

#define UDMA_ASRC_LANE_CFG_1_CTRL_MUX_BIT

#define UDMA_ASRC_LANE_CFG_1_CTRL_MUX_MASK

#define UDMA_ASRC_LANE_CFG_1_CTRL_MUX_RESET

#define UDMA_ASRC_LANE_CFG_1_CTRL_MUX_WIDTH

#define UDMA_ASRC_LANE_CFG_1_DROP_ON_WAIT_BIT

#define UDMA_ASRC_LANE_CFG_1_DROP_ON_WAIT_MASK

#define UDMA_ASRC_LANE_CFG_1_DROP_ON_WAIT_RESET

#define UDMA_ASRC_LANE_CFG_1_DROP_ON_WAIT_WIDTH

#define UDMA_ASRC_LANE_CFG_1_RSTN_BIT

#define UDMA_ASRC_LANE_CFG_1_RSTN_MASK

#define UDMA_ASRC_LANE_CFG_1_RSTN_RESET

#define UDMA_ASRC_LANE_CFG_1_RSTN_WIDTH

#define UDMA_ASRC_LANE_CFG_1_USE_STREAM_IN_BIT

#define UDMA_ASRC_LANE_CFG_1_USE_STREAM_IN_MASK

#define UDMA_ASRC_LANE_CFG_1_USE_STREAM_IN_RESET

#define UDMA_ASRC_LANE_CFG_1_USE_STREAM_IN_WIDTH

#define UDMA_ASRC_LANE_CFG_1_USE_STREAM_OUT_BIT

#define UDMA_ASRC_LANE_CFG_1_USE_STREAM_OUT_MASK

#define UDMA_ASRC_LANE_CFG_1_USE_STREAM_OUT_RESET

#define UDMA_ASRC_LANE_CFG_1_USE_STREAM_OUT_WIDTH

#define UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_IN_BIT

#define UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_IN_MASK

#define UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_IN_RESET

#define UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_IN_WIDTH

#define UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_OUT_BIT

#define UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_OUT_MASK

#define UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_OUT_RESET

#define UDMA_ASRC_LANE_CFG_1_WAIT_LOCK_OUT_WIDTH

#define UDMA_ASRC_LANE_CFG_2_CH_EN_BIT

#define UDMA_ASRC_LANE_CFG_2_CH_EN_MASK

#define UDMA_ASRC_LANE_CFG_2_CH_EN_RESET

#define UDMA_ASRC_LANE_CFG_2_CH_EN_WIDTH

#define UDMA_ASRC_LANE_CFG_2_CLK_EN_BIT

#define UDMA_ASRC_LANE_CFG_2_CLK_EN_MASK

#define UDMA_ASRC_LANE_CFG_2_CLK_EN_RESET

#define UDMA_ASRC_LANE_CFG_2_CLK_EN_WIDTH

#define UDMA_ASRC_LANE_CFG_2_CTRL_MUX_BIT

#define UDMA_ASRC_LANE_CFG_2_CTRL_MUX_MASK

#define UDMA_ASRC_LANE_CFG_2_CTRL_MUX_RESET

#define UDMA_ASRC_LANE_CFG_2_CTRL_MUX_WIDTH

#define UDMA_ASRC_LANE_CFG_2_DROP_ON_WAIT_BIT

#define UDMA_ASRC_LANE_CFG_2_DROP_ON_WAIT_MASK

#define UDMA_ASRC_LANE_CFG_2_DROP_ON_WAIT_RESET

#define UDMA_ASRC_LANE_CFG_2_DROP_ON_WAIT_WIDTH

#define UDMA_ASRC_LANE_CFG_2_RSTN_BIT

#define UDMA_ASRC_LANE_CFG_2_RSTN_MASK

#define UDMA_ASRC_LANE_CFG_2_RSTN_RESET

#define UDMA_ASRC_LANE_CFG_2_RSTN_WIDTH

#define UDMA_ASRC_LANE_CFG_2_USE_STREAM_IN_BIT

#define UDMA_ASRC_LANE_CFG_2_USE_STREAM_IN_MASK

#define UDMA_ASRC_LANE_CFG_2_USE_STREAM_IN_RESET

#define UDMA_ASRC_LANE_CFG_2_USE_STREAM_IN_WIDTH

#define UDMA_ASRC_LANE_CFG_2_USE_STREAM_OUT_BIT

#define UDMA_ASRC_LANE_CFG_2_USE_STREAM_OUT_MASK

#define UDMA_ASRC_LANE_CFG_2_USE_STREAM_OUT_RESET

#define UDMA_ASRC_LANE_CFG_2_USE_STREAM_OUT_WIDTH

#define UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_IN_BIT

#define UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_IN_MASK

#define UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_IN_RESET

#define UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_IN_WIDTH

#define UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_OUT_BIT

#define UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_OUT_MASK

#define UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_OUT_RESET

#define UDMA_ASRC_LANE_CFG_2_WAIT_LOCK_OUT_WIDTH

#define UDMA_ASRC_LANE_CFG_3_CH_EN_BIT

#define UDMA_ASRC_LANE_CFG_3_CH_EN_MASK

#define UDMA_ASRC_LANE_CFG_3_CH_EN_RESET

#define UDMA_ASRC_LANE_CFG_3_CH_EN_WIDTH

#define UDMA_ASRC_LANE_CFG_3_CLK_EN_BIT

#define UDMA_ASRC_LANE_CFG_3_CLK_EN_MASK

#define UDMA_ASRC_LANE_CFG_3_CLK_EN_RESET

#define UDMA_ASRC_LANE_CFG_3_CLK_EN_WIDTH

#define UDMA_ASRC_LANE_CFG_3_CTRL_MUX_BIT

#define UDMA_ASRC_LANE_CFG_3_CTRL_MUX_MASK

#define UDMA_ASRC_LANE_CFG_3_CTRL_MUX_RESET

#define UDMA_ASRC_LANE_CFG_3_CTRL_MUX_WIDTH

#define UDMA_ASRC_LANE_CFG_3_DROP_ON_WAIT_BIT

#define UDMA_ASRC_LANE_CFG_3_DROP_ON_WAIT_MASK

#define UDMA_ASRC_LANE_CFG_3_DROP_ON_WAIT_RESET

#define UDMA_ASRC_LANE_CFG_3_DROP_ON_WAIT_WIDTH

#define UDMA_ASRC_LANE_CFG_3_RSTN_BIT

#define UDMA_ASRC_LANE_CFG_3_RSTN_MASK

#define UDMA_ASRC_LANE_CFG_3_RSTN_RESET

#define UDMA_ASRC_LANE_CFG_3_RSTN_WIDTH

#define UDMA_ASRC_LANE_CFG_3_USE_STREAM_IN_BIT

#define UDMA_ASRC_LANE_CFG_3_USE_STREAM_IN_MASK

#define UDMA_ASRC_LANE_CFG_3_USE_STREAM_IN_RESET

#define UDMA_ASRC_LANE_CFG_3_USE_STREAM_IN_WIDTH

#define UDMA_ASRC_LANE_CFG_3_USE_STREAM_OUT_BIT

#define UDMA_ASRC_LANE_CFG_3_USE_STREAM_OUT_MASK

#define UDMA_ASRC_LANE_CFG_3_USE_STREAM_OUT_RESET

#define UDMA_ASRC_LANE_CFG_3_USE_STREAM_OUT_WIDTH

#define UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_IN_BIT

#define UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_IN_MASK

#define UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_IN_RESET

#define UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_IN_WIDTH

#define UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_OUT_BIT

#define UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_OUT_MASK

#define UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_OUT_RESET

#define UDMA_ASRC_LANE_CFG_3_WAIT_LOCK_OUT_WIDTH

#define UDMA_ASRC_LANE_IDIN_0_ID_CH0_BIT

#define UDMA_ASRC_LANE_IDIN_0_ID_CH0_MASK

#define UDMA_ASRC_LANE_IDIN_0_ID_CH0_RESET

#define UDMA_ASRC_LANE_IDIN_0_ID_CH0_WIDTH

#define UDMA_ASRC_LANE_IDIN_0_ID_CH1_BIT

#define UDMA_ASRC_LANE_IDIN_0_ID_CH1_MASK

#define UDMA_ASRC_LANE_IDIN_0_ID_CH1_RESET

#define UDMA_ASRC_LANE_IDIN_0_ID_CH1_WIDTH

#define UDMA_ASRC_LANE_IDIN_0_ID_CH2_BIT

#define UDMA_ASRC_LANE_IDIN_0_ID_CH2_MASK

#define UDMA_ASRC_LANE_IDIN_0_ID_CH2_RESET

#define UDMA_ASRC_LANE_IDIN_0_ID_CH2_WIDTH

#define UDMA_ASRC_LANE_IDIN_0_ID_CH3_BIT

#define UDMA_ASRC_LANE_IDIN_0_ID_CH3_MASK

#define UDMA_ASRC_LANE_IDIN_0_ID_CH3_RESET

#define UDMA_ASRC_LANE_IDIN_0_ID_CH3_WIDTH

#define UDMA_ASRC_LANE_IDIN_1_ID_CH0_BIT

#define UDMA_ASRC_LANE_IDIN_1_ID_CH0_MASK

#define UDMA_ASRC_LANE_IDIN_1_ID_CH0_RESET

#define UDMA_ASRC_LANE_IDIN_1_ID_CH0_WIDTH

#define UDMA_ASRC_LANE_IDIN_1_ID_CH1_BIT

#define UDMA_ASRC_LANE_IDIN_1_ID_CH1_MASK

#define UDMA_ASRC_LANE_IDIN_1_ID_CH1_RESET

#define UDMA_ASRC_LANE_IDIN_1_ID_CH1_WIDTH

#define UDMA_ASRC_LANE_IDIN_1_ID_CH2_BIT

#define UDMA_ASRC_LANE_IDIN_1_ID_CH2_MASK

#define UDMA_ASRC_LANE_IDIN_1_ID_CH2_RESET

#define UDMA_ASRC_LANE_IDIN_1_ID_CH2_WIDTH

#define UDMA_ASRC_LANE_IDIN_1_ID_CH3_BIT

#define UDMA_ASRC_LANE_IDIN_1_ID_CH3_MASK

#define UDMA_ASRC_LANE_IDIN_1_ID_CH3_RESET

#define UDMA_ASRC_LANE_IDIN_1_ID_CH3_WIDTH

#define UDMA_ASRC_LANE_IDIN_2_ID_CH0_BIT

#define UDMA_ASRC_LANE_IDIN_2_ID_CH0_MASK

#define UDMA_ASRC_LANE_IDIN_2_ID_CH0_RESET

#define UDMA_ASRC_LANE_IDIN_2_ID_CH0_WIDTH

#define UDMA_ASRC_LANE_IDIN_2_ID_CH1_BIT

#define UDMA_ASRC_LANE_IDIN_2_ID_CH1_MASK

#define UDMA_ASRC_LANE_IDIN_2_ID_CH1_RESET

#define UDMA_ASRC_LANE_IDIN_2_ID_CH1_WIDTH

#define UDMA_ASRC_LANE_IDIN_2_ID_CH2_BIT

#define UDMA_ASRC_LANE_IDIN_2_ID_CH2_MASK

#define UDMA_ASRC_LANE_IDIN_2_ID_CH2_RESET

#define UDMA_ASRC_LANE_IDIN_2_ID_CH2_WIDTH

#define UDMA_ASRC_LANE_IDIN_2_ID_CH3_BIT

#define UDMA_ASRC_LANE_IDIN_2_ID_CH3_MASK

#define UDMA_ASRC_LANE_IDIN_2_ID_CH3_RESET

#define UDMA_ASRC_LANE_IDIN_2_ID_CH3_WIDTH

#define UDMA_ASRC_LANE_IDIN_3_ID_CH0_BIT

#define UDMA_ASRC_LANE_IDIN_3_ID_CH0_MASK

#define UDMA_ASRC_LANE_IDIN_3_ID_CH0_RESET

#define UDMA_ASRC_LANE_IDIN_3_ID_CH0_WIDTH

#define UDMA_ASRC_LANE_IDIN_3_ID_CH1_BIT

#define UDMA_ASRC_LANE_IDIN_3_ID_CH1_MASK

#define UDMA_ASRC_LANE_IDIN_3_ID_CH1_RESET

#define UDMA_ASRC_LANE_IDIN_3_ID_CH1_WIDTH

#define UDMA_ASRC_LANE_IDIN_3_ID_CH2_BIT

#define UDMA_ASRC_LANE_IDIN_3_ID_CH2_MASK

#define UDMA_ASRC_LANE_IDIN_3_ID_CH2_RESET

#define UDMA_ASRC_LANE_IDIN_3_ID_CH2_WIDTH

#define UDMA_ASRC_LANE_IDIN_3_ID_CH3_BIT

#define UDMA_ASRC_LANE_IDIN_3_ID_CH3_MASK

#define UDMA_ASRC_LANE_IDIN_3_ID_CH3_RESET

#define UDMA_ASRC_LANE_IDIN_3_ID_CH3_WIDTH

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH0_BIT

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH0_MASK

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH0_RESET

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH0_WIDTH

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH1_BIT

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH1_MASK

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH1_RESET

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH1_WIDTH

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH2_BIT

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH2_MASK

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH2_RESET

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH2_WIDTH

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH3_BIT

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH3_MASK

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH3_RESET

#define UDMA_ASRC_LANE_IDOUT_0_ID_CH3_WIDTH

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH0_BIT

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH0_MASK

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH0_RESET

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH0_WIDTH

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH1_BIT

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH1_MASK

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH1_RESET

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH1_WIDTH

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH2_BIT

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH2_MASK

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH2_RESET

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH2_WIDTH

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH3_BIT

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH3_MASK

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH3_RESET

#define UDMA_ASRC_LANE_IDOUT_1_ID_CH3_WIDTH

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH0_BIT

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH0_MASK

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH0_RESET

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH0_WIDTH

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH1_BIT

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH1_MASK

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH1_RESET

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH1_WIDTH

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH2_BIT

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH2_MASK

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH2_RESET

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH2_WIDTH

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH3_BIT

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH3_MASK

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH3_RESET

#define UDMA_ASRC_LANE_IDOUT_2_ID_CH3_WIDTH

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH0_BIT

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH0_MASK

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH0_RESET

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH0_WIDTH

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH1_BIT

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH1_MASK

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH1_RESET

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH1_WIDTH

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH2_BIT

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH2_MASK

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH2_RESET

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH2_WIDTH

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH3_BIT

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH3_MASK

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH3_RESET

#define UDMA_ASRC_LANE_IDOUT_3_ID_CH3_WIDTH

#define UDMA_ASRC_MEM2MEM_CFG_CH_EN_BIT

#define UDMA_ASRC_MEM2MEM_CFG_CH_EN_MASK

#define UDMA_ASRC_MEM2MEM_CFG_CH_EN_RESET

#define UDMA_ASRC_MEM2MEM_CFG_CH_EN_WIDTH

#define UDMA_ASRC_MEM2MEM_CFG_CLK_EN_BIT

#define UDMA_ASRC_MEM2MEM_CFG_CLK_EN_MASK

#define UDMA_ASRC_MEM2MEM_CFG_CLK_EN_RESET

#define UDMA_ASRC_MEM2MEM_CFG_CLK_EN_WIDTH

#define UDMA_ASRC_MEM2MEM_CFG_CTX_ID_BIT

#define UDMA_ASRC_MEM2MEM_CFG_CTX_ID_MASK

#define UDMA_ASRC_MEM2MEM_CFG_CTX_ID_RESET

#define UDMA_ASRC_MEM2MEM_CFG_CTX_ID_WIDTH

#define UDMA_ASRC_MEM2MEM_CFG_FS_IN_BIT

#define UDMA_ASRC_MEM2MEM_CFG_FS_IN_MASK

#define UDMA_ASRC_MEM2MEM_CFG_FS_IN_RESET

#define UDMA_ASRC_MEM2MEM_CFG_FS_IN_WIDTH

#define UDMA_ASRC_MEM2MEM_CFG_FS_OUT_BIT

#define UDMA_ASRC_MEM2MEM_CFG_FS_OUT_MASK

#define UDMA_ASRC_MEM2MEM_CFG_FS_OUT_RESET

#define UDMA_ASRC_MEM2MEM_CFG_FS_OUT_WIDTH

#define UDMA_ASRC_MEM2MEM_CFG_RESTORE_BIT

#define UDMA_ASRC_MEM2MEM_CFG_RESTORE_MASK

#define UDMA_ASRC_MEM2MEM_CFG_RESTORE_RESET

#define UDMA_ASRC_MEM2MEM_CFG_RESTORE_WIDTH

#define UDMA_ASRC_MEM2MEM_CFG_RSTN_BIT

#define UDMA_ASRC_MEM2MEM_CFG_RSTN_MASK

#define UDMA_ASRC_MEM2MEM_CFG_RSTN_RESET

#define UDMA_ASRC_MEM2MEM_CFG_RSTN_WIDTH

#define UDMA_ASRC_MEM2MEM_CFG_STORE_BIT

#define UDMA_ASRC_MEM2MEM_CFG_STORE_MASK

#define UDMA_ASRC_MEM2MEM_CFG_STORE_RESET

#define UDMA_ASRC_MEM2MEM_CFG_STORE_WIDTH

#define UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH0_BIT

#define UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH0_MASK

#define UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH0_RESET

#define UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH0_WIDTH

#define UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH1_BIT

#define UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH1_MASK

#define UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH1_RESET

#define UDMA_ASRC_MEM2MEM_ID_M2M_IN_CH1_WIDTH

#define UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH0_BIT

#define UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH0_MASK

#define UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH0_RESET

#define UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH0_WIDTH

#define UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH1_BIT

#define UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH1_MASK

#define UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH1_RESET

#define UDMA_ASRC_MEM2MEM_ID_M2M_OUT_CH1_WIDTH

#define UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_BIT

#define UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_EN_BIT

#define UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_EN_MASK

#define UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_EN_RESET

#define UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_EN_WIDTH

#define UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_MASK

#define UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_RESET

#define UDMA_ASRC_MEM2MEM_RATIO_M2M_RATIO_WIDTH

#define UDMA_ASRC_STATUS_LOCK_BIT

#define UDMA_ASRC_STATUS_LOCK_MASK

#define UDMA_ASRC_STATUS_LOCK_RESET

#define UDMA_ASRC_STATUS_LOCK_WIDTH