soc_eu_regfields.h File Reference

Macros
#define	SOC_EU_SW_EVENT_EVENT_BIT
#define	SOC_EU_SW_EVENT_EVENT_WIDTH
#define	SOC_EU_SW_EVENT_EVENT_MASK
#define	SOC_EU_SW_EVENT_EVENT_RESET
#define	SOC_EU_FC_MASK_MSB_FC_MASK_MSB_BIT
#define	SOC_EU_FC_MASK_MSB_FC_MASK_MSB_WIDTH
#define	SOC_EU_FC_MASK_MSB_FC_MASK_MSB_MASK
#define	SOC_EU_FC_MASK_MSB_FC_MASK_MSB_RESET
#define	SOC_EU_FC_MASK_LSB_FC_MASK_LSB_BIT
#define	SOC_EU_FC_MASK_LSB_FC_MASK_LSB_WIDTH
#define	SOC_EU_FC_MASK_LSB_FC_MASK_LSB_MASK
#define	SOC_EU_FC_MASK_LSB_FC_MASK_LSB_RESET
#define	SOC_EU_CL_MASK_MSB_CL_MASK_MSB_BIT
#define	SOC_EU_CL_MASK_MSB_CL_MASK_MSB_WIDTH
#define	SOC_EU_CL_MASK_MSB_CL_MASK_MSB_MASK
#define	SOC_EU_CL_MASK_MSB_CL_MASK_MSB_RESET
#define	SOC_EU_CL_MASK_LSB_CL_MASK_LSB_BIT
#define	SOC_EU_CL_MASK_LSB_CL_MASK_LSB_WIDTH
#define	SOC_EU_CL_MASK_LSB_CL_MASK_LSB_MASK
#define	SOC_EU_CL_MASK_LSB_CL_MASK_LSB_RESET
#define	SOC_EU_PR_MASK_MSB_PR_MASK_MSB_BIT
#define	SOC_EU_PR_MASK_MSB_PR_MASK_MSB_WIDTH
#define	SOC_EU_PR_MASK_MSB_PR_MASK_MSB_MASK
#define	SOC_EU_PR_MASK_MSB_PR_MASK_MSB_RESET
#define	SOC_EU_PR_MASK_LSB_PR_MASK_LSB_BIT
#define	SOC_EU_PR_MASK_LSB_PR_MASK_LSB_WIDTH
#define	SOC_EU_PR_MASK_LSB_PR_MASK_LSB_MASK
#define	SOC_EU_PR_MASK_LSB_PR_MASK_LSB_RESET
#define	SOC_EU_ERR_MSB_ERR_MSB_BIT
#define	SOC_EU_ERR_MSB_ERR_MSB_WIDTH
#define	SOC_EU_ERR_MSB_ERR_MSB_MASK
#define	SOC_EU_ERR_MSB_ERR_MSB_RESET
#define	SOC_EU_ERR_LSB_ERR_LSB_BIT
#define	SOC_EU_ERR_LSB_ERR_LSB_WIDTH
#define	SOC_EU_ERR_LSB_ERR_LSB_MASK
#define	SOC_EU_ERR_LSB_ERR_LSB_RESET
#define	SOC_EU_TIMER1_SEL_HI_EVT_BIT
#define	SOC_EU_TIMER1_SEL_HI_EVT_WIDTH
#define	SOC_EU_TIMER1_SEL_HI_EVT_MASK
#define	SOC_EU_TIMER1_SEL_HI_EVT_RESET
#define	SOC_EU_TIMER1_SEL_HI_ENA_BIT
#define	SOC_EU_TIMER1_SEL_HI_ENA_WIDTH
#define	SOC_EU_TIMER1_SEL_HI_ENA_MASK
#define	SOC_EU_TIMER1_SEL_HI_ENA_RESET
#define	SOC_EU_TIMER1_SEL_LO_EVT_BIT
#define	SOC_EU_TIMER1_SEL_LO_EVT_WIDTH
#define	SOC_EU_TIMER1_SEL_LO_EVT_MASK
#define	SOC_EU_TIMER1_SEL_LO_EVT_RESET
#define	SOC_EU_TIMER1_SEL_LO_ENA_BIT
#define	SOC_EU_TIMER1_SEL_LO_ENA_WIDTH
#define	SOC_EU_TIMER1_SEL_LO_ENA_MASK
#define	SOC_EU_TIMER1_SEL_LO_ENA_RESET
#define	SOC_EU_TIMER2_SEL_HI_EVT_BIT
#define	SOC_EU_TIMER2_SEL_HI_EVT_WIDTH
#define	SOC_EU_TIMER2_SEL_HI_EVT_MASK
#define	SOC_EU_TIMER2_SEL_HI_EVT_RESET
#define	SOC_EU_TIMER2_SEL_HI_ENA_BIT
#define	SOC_EU_TIMER2_SEL_HI_ENA_WIDTH
#define	SOC_EU_TIMER2_SEL_HI_ENA_MASK
#define	SOC_EU_TIMER2_SEL_HI_ENA_RESET
#define	SOC_EU_TIMER2_SEL_LO_EVT_BIT
#define	SOC_EU_TIMER2_SEL_LO_EVT_WIDTH
#define	SOC_EU_TIMER2_SEL_LO_EVT_MASK
#define	SOC_EU_TIMER2_SEL_LO_EVT_RESET
#define	SOC_EU_TIMER2_SEL_LO_ENA_BIT
#define	SOC_EU_TIMER2_SEL_LO_ENA_WIDTH
#define	SOC_EU_TIMER2_SEL_LO_ENA_MASK
#define	SOC_EU_TIMER2_SEL_LO_ENA_RESET

Macro Definition Documentation

#define SOC_EU_CL_MASK_LSB_CL_MASK_LSB_BIT

#define SOC_EU_CL_MASK_LSB_CL_MASK_LSB_MASK

#define SOC_EU_CL_MASK_LSB_CL_MASK_LSB_RESET

#define SOC_EU_CL_MASK_LSB_CL_MASK_LSB_WIDTH

#define SOC_EU_CL_MASK_MSB_CL_MASK_MSB_BIT

#define SOC_EU_CL_MASK_MSB_CL_MASK_MSB_MASK

#define SOC_EU_CL_MASK_MSB_CL_MASK_MSB_RESET

#define SOC_EU_CL_MASK_MSB_CL_MASK_MSB_WIDTH

#define SOC_EU_ERR_LSB_ERR_LSB_BIT

#define SOC_EU_ERR_LSB_ERR_LSB_MASK

#define SOC_EU_ERR_LSB_ERR_LSB_RESET

#define SOC_EU_ERR_LSB_ERR_LSB_WIDTH

#define SOC_EU_ERR_MSB_ERR_MSB_BIT

#define SOC_EU_ERR_MSB_ERR_MSB_MASK

#define SOC_EU_ERR_MSB_ERR_MSB_RESET

#define SOC_EU_ERR_MSB_ERR_MSB_WIDTH

#define SOC_EU_FC_MASK_LSB_FC_MASK_LSB_BIT

#define SOC_EU_FC_MASK_LSB_FC_MASK_LSB_MASK

#define SOC_EU_FC_MASK_LSB_FC_MASK_LSB_RESET

#define SOC_EU_FC_MASK_LSB_FC_MASK_LSB_WIDTH

#define SOC_EU_FC_MASK_MSB_FC_MASK_MSB_BIT

#define SOC_EU_FC_MASK_MSB_FC_MASK_MSB_MASK

#define SOC_EU_FC_MASK_MSB_FC_MASK_MSB_RESET

#define SOC_EU_FC_MASK_MSB_FC_MASK_MSB_WIDTH

#define SOC_EU_PR_MASK_LSB_PR_MASK_LSB_BIT

#define SOC_EU_PR_MASK_LSB_PR_MASK_LSB_MASK

#define SOC_EU_PR_MASK_LSB_PR_MASK_LSB_RESET

#define SOC_EU_PR_MASK_LSB_PR_MASK_LSB_WIDTH

#define SOC_EU_PR_MASK_MSB_PR_MASK_MSB_BIT

#define SOC_EU_PR_MASK_MSB_PR_MASK_MSB_MASK

#define SOC_EU_PR_MASK_MSB_PR_MASK_MSB_RESET

#define SOC_EU_PR_MASK_MSB_PR_MASK_MSB_WIDTH

#define SOC_EU_SW_EVENT_EVENT_BIT

#define SOC_EU_SW_EVENT_EVENT_MASK

#define SOC_EU_SW_EVENT_EVENT_RESET

#define SOC_EU_SW_EVENT_EVENT_WIDTH

#define SOC_EU_TIMER1_SEL_HI_ENA_BIT

#define SOC_EU_TIMER1_SEL_HI_ENA_MASK

#define SOC_EU_TIMER1_SEL_HI_ENA_RESET

#define SOC_EU_TIMER1_SEL_HI_ENA_WIDTH

#define SOC_EU_TIMER1_SEL_HI_EVT_BIT

#define SOC_EU_TIMER1_SEL_HI_EVT_MASK

#define SOC_EU_TIMER1_SEL_HI_EVT_RESET

#define SOC_EU_TIMER1_SEL_HI_EVT_WIDTH

#define SOC_EU_TIMER1_SEL_LO_ENA_BIT

#define SOC_EU_TIMER1_SEL_LO_ENA_MASK

#define SOC_EU_TIMER1_SEL_LO_ENA_RESET

#define SOC_EU_TIMER1_SEL_LO_ENA_WIDTH

#define SOC_EU_TIMER1_SEL_LO_EVT_BIT

#define SOC_EU_TIMER1_SEL_LO_EVT_MASK

#define SOC_EU_TIMER1_SEL_LO_EVT_RESET

#define SOC_EU_TIMER1_SEL_LO_EVT_WIDTH

#define SOC_EU_TIMER2_SEL_HI_ENA_BIT

#define SOC_EU_TIMER2_SEL_HI_ENA_MASK

#define SOC_EU_TIMER2_SEL_HI_ENA_RESET

#define SOC_EU_TIMER2_SEL_HI_ENA_WIDTH

#define SOC_EU_TIMER2_SEL_HI_EVT_BIT

#define SOC_EU_TIMER2_SEL_HI_EVT_MASK

#define SOC_EU_TIMER2_SEL_HI_EVT_RESET

#define SOC_EU_TIMER2_SEL_HI_EVT_WIDTH

#define SOC_EU_TIMER2_SEL_LO_ENA_BIT

#define SOC_EU_TIMER2_SEL_LO_ENA_MASK

#define SOC_EU_TIMER2_SEL_LO_ENA_RESET

#define SOC_EU_TIMER2_SEL_LO_ENA_WIDTH

#define SOC_EU_TIMER2_SEL_LO_EVT_BIT

#define SOC_EU_TIMER2_SEL_LO_EVT_MASK

#define SOC_EU_TIMER2_SEL_LO_EVT_RESET

#define SOC_EU_TIMER2_SEL_LO_EVT_WIDTH