secured_riscv_debug_regfields.h File Reference

Macros
#define	SECURED_RISCV_DEBUG_CTRL_SSTE_BIT
#define	SECURED_RISCV_DEBUG_CTRL_SSTE_WIDTH
#define	SECURED_RISCV_DEBUG_CTRL_SSTE_MASK
#define	SECURED_RISCV_DEBUG_CTRL_SSTE_RESET
#define	SECURED_RISCV_DEBUG_CTRL_HALT_BIT
#define	SECURED_RISCV_DEBUG_CTRL_HALT_WIDTH
#define	SECURED_RISCV_DEBUG_CTRL_HALT_MASK
#define	SECURED_RISCV_DEBUG_CTRL_HALT_RESET
#define	SECURED_RISCV_DEBUG_HIT_SSTH_BIT
#define	SECURED_RISCV_DEBUG_HIT_SSTH_WIDTH
#define	SECURED_RISCV_DEBUG_HIT_SSTH_MASK
#define	SECURED_RISCV_DEBUG_HIT_SSTH_RESET
#define	SECURED_RISCV_DEBUG_HIT_SLEEP_BIT
#define	SECURED_RISCV_DEBUG_HIT_SLEEP_WIDTH
#define	SECURED_RISCV_DEBUG_HIT_SLEEP_MASK
#define	SECURED_RISCV_DEBUG_HIT_SLEEP_RESET
#define	SECURED_RISCV_DEBUG_IE_EILL_BIT
#define	SECURED_RISCV_DEBUG_IE_EILL_WIDTH
#define	SECURED_RISCV_DEBUG_IE_EILL_MASK
#define	SECURED_RISCV_DEBUG_IE_EILL_RESET
#define	SECURED_RISCV_DEBUG_IE_EBRK_BIT
#define	SECURED_RISCV_DEBUG_IE_EBRK_WIDTH
#define	SECURED_RISCV_DEBUG_IE_EBRK_MASK
#define	SECURED_RISCV_DEBUG_IE_EBRK_RESET
#define	SECURED_RISCV_DEBUG_IE_ELSU_BIT
#define	SECURED_RISCV_DEBUG_IE_ELSU_WIDTH
#define	SECURED_RISCV_DEBUG_IE_ELSU_MASK
#define	SECURED_RISCV_DEBUG_IE_ELSU_RESET
#define	SECURED_RISCV_DEBUG_IE_ELSU_DUP_BIT
#define	SECURED_RISCV_DEBUG_IE_ELSU_DUP_WIDTH
#define	SECURED_RISCV_DEBUG_IE_ELSU_DUP_MASK
#define	SECURED_RISCV_DEBUG_IE_ELSU_DUP_RESET
#define	SECURED_RISCV_DEBUG_IE_ECALL_BIT
#define	SECURED_RISCV_DEBUG_IE_ECALL_WIDTH
#define	SECURED_RISCV_DEBUG_IE_ECALL_MASK
#define	SECURED_RISCV_DEBUG_IE_ECALL_RESET
#define	SECURED_RISCV_DEBUG_CAUSE_CAUSE_BIT
#define	SECURED_RISCV_DEBUG_CAUSE_CAUSE_WIDTH
#define	SECURED_RISCV_DEBUG_CAUSE_CAUSE_MASK
#define	SECURED_RISCV_DEBUG_CAUSE_CAUSE_RESET
#define	SECURED_RISCV_DEBUG_CAUSE_IRQ_BIT
#define	SECURED_RISCV_DEBUG_CAUSE_IRQ_WIDTH
#define	SECURED_RISCV_DEBUG_CAUSE_IRQ_MASK
#define	SECURED_RISCV_DEBUG_CAUSE_IRQ_RESET
#define	SECURED_RISCV_DEBUG_NPC_NPC_BIT
#define	SECURED_RISCV_DEBUG_NPC_NPC_WIDTH
#define	SECURED_RISCV_DEBUG_NPC_NPC_MASK
#define	SECURED_RISCV_DEBUG_NPC_NPC_RESET
#define	SECURED_RISCV_DEBUG_PPC_PPC_BIT
#define	SECURED_RISCV_DEBUG_PPC_PPC_WIDTH
#define	SECURED_RISCV_DEBUG_PPC_PPC_MASK
#define	SECURED_RISCV_DEBUG_PPC_PPC_RESET
#define	SECURED_RISCV_DEBUG_GPR0_GPR0_BIT
#define	SECURED_RISCV_DEBUG_GPR0_GPR0_WIDTH
#define	SECURED_RISCV_DEBUG_GPR0_GPR0_MASK
#define	SECURED_RISCV_DEBUG_GPR0_GPR0_RESET
#define	SECURED_RISCV_DEBUG_GPR1_GPR1_BIT
#define	SECURED_RISCV_DEBUG_GPR1_GPR1_WIDTH
#define	SECURED_RISCV_DEBUG_GPR1_GPR1_MASK
#define	SECURED_RISCV_DEBUG_GPR1_GPR1_RESET
#define	SECURED_RISCV_DEBUG_GPR2_GPR2_BIT
#define	SECURED_RISCV_DEBUG_GPR2_GPR2_WIDTH
#define	SECURED_RISCV_DEBUG_GPR2_GPR2_MASK
#define	SECURED_RISCV_DEBUG_GPR2_GPR2_RESET
#define	SECURED_RISCV_DEBUG_GPR3_GPR3_BIT
#define	SECURED_RISCV_DEBUG_GPR3_GPR3_WIDTH
#define	SECURED_RISCV_DEBUG_GPR3_GPR3_MASK
#define	SECURED_RISCV_DEBUG_GPR3_GPR3_RESET
#define	SECURED_RISCV_DEBUG_GPR4_GPR4_BIT
#define	SECURED_RISCV_DEBUG_GPR4_GPR4_WIDTH
#define	SECURED_RISCV_DEBUG_GPR4_GPR4_MASK
#define	SECURED_RISCV_DEBUG_GPR4_GPR4_RESET
#define	SECURED_RISCV_DEBUG_GPR5_GPR5_BIT
#define	SECURED_RISCV_DEBUG_GPR5_GPR5_WIDTH
#define	SECURED_RISCV_DEBUG_GPR5_GPR5_MASK
#define	SECURED_RISCV_DEBUG_GPR5_GPR5_RESET
#define	SECURED_RISCV_DEBUG_GPR6_GPR6_BIT
#define	SECURED_RISCV_DEBUG_GPR6_GPR6_WIDTH
#define	SECURED_RISCV_DEBUG_GPR6_GPR6_MASK
#define	SECURED_RISCV_DEBUG_GPR6_GPR6_RESET
#define	SECURED_RISCV_DEBUG_GPR7_GPR7_BIT
#define	SECURED_RISCV_DEBUG_GPR7_GPR7_WIDTH
#define	SECURED_RISCV_DEBUG_GPR7_GPR7_MASK
#define	SECURED_RISCV_DEBUG_GPR7_GPR7_RESET
#define	SECURED_RISCV_DEBUG_GPR8_GPR8_BIT
#define	SECURED_RISCV_DEBUG_GPR8_GPR8_WIDTH
#define	SECURED_RISCV_DEBUG_GPR8_GPR8_MASK
#define	SECURED_RISCV_DEBUG_GPR8_GPR8_RESET
#define	SECURED_RISCV_DEBUG_GPR9_GPR9_BIT
#define	SECURED_RISCV_DEBUG_GPR9_GPR9_WIDTH
#define	SECURED_RISCV_DEBUG_GPR9_GPR9_MASK
#define	SECURED_RISCV_DEBUG_GPR9_GPR9_RESET
#define	SECURED_RISCV_DEBUG_GPR10_GPR10_BIT
#define	SECURED_RISCV_DEBUG_GPR10_GPR10_WIDTH
#define	SECURED_RISCV_DEBUG_GPR10_GPR10_MASK
#define	SECURED_RISCV_DEBUG_GPR10_GPR10_RESET
#define	SECURED_RISCV_DEBUG_GPR11_GPR11_BIT
#define	SECURED_RISCV_DEBUG_GPR11_GPR11_WIDTH
#define	SECURED_RISCV_DEBUG_GPR11_GPR11_MASK
#define	SECURED_RISCV_DEBUG_GPR11_GPR11_RESET
#define	SECURED_RISCV_DEBUG_GPR12_GPR12_BIT
#define	SECURED_RISCV_DEBUG_GPR12_GPR12_WIDTH
#define	SECURED_RISCV_DEBUG_GPR12_GPR12_MASK
#define	SECURED_RISCV_DEBUG_GPR12_GPR12_RESET
#define	SECURED_RISCV_DEBUG_GPR13_GPR13_BIT
#define	SECURED_RISCV_DEBUG_GPR13_GPR13_WIDTH
#define	SECURED_RISCV_DEBUG_GPR13_GPR13_MASK
#define	SECURED_RISCV_DEBUG_GPR13_GPR13_RESET
#define	SECURED_RISCV_DEBUG_GPR14_GPR14_BIT
#define	SECURED_RISCV_DEBUG_GPR14_GPR14_WIDTH
#define	SECURED_RISCV_DEBUG_GPR14_GPR14_MASK
#define	SECURED_RISCV_DEBUG_GPR14_GPR14_RESET
#define	SECURED_RISCV_DEBUG_GPR15_GPR15_BIT
#define	SECURED_RISCV_DEBUG_GPR15_GPR15_WIDTH
#define	SECURED_RISCV_DEBUG_GPR15_GPR15_MASK
#define	SECURED_RISCV_DEBUG_GPR15_GPR15_RESET
#define	SECURED_RISCV_DEBUG_GPR16_GPR16_BIT
#define	SECURED_RISCV_DEBUG_GPR16_GPR16_WIDTH
#define	SECURED_RISCV_DEBUG_GPR16_GPR16_MASK
#define	SECURED_RISCV_DEBUG_GPR16_GPR16_RESET
#define	SECURED_RISCV_DEBUG_GPR17_GPR17_BIT
#define	SECURED_RISCV_DEBUG_GPR17_GPR17_WIDTH
#define	SECURED_RISCV_DEBUG_GPR17_GPR17_MASK
#define	SECURED_RISCV_DEBUG_GPR17_GPR17_RESET
#define	SECURED_RISCV_DEBUG_GPR18_GPR18_BIT
#define	SECURED_RISCV_DEBUG_GPR18_GPR18_WIDTH
#define	SECURED_RISCV_DEBUG_GPR18_GPR18_MASK
#define	SECURED_RISCV_DEBUG_GPR18_GPR18_RESET
#define	SECURED_RISCV_DEBUG_GPR19_GPR19_BIT
#define	SECURED_RISCV_DEBUG_GPR19_GPR19_WIDTH
#define	SECURED_RISCV_DEBUG_GPR19_GPR19_MASK
#define	SECURED_RISCV_DEBUG_GPR19_GPR19_RESET
#define	SECURED_RISCV_DEBUG_GPR20_GPR20_BIT
#define	SECURED_RISCV_DEBUG_GPR20_GPR20_WIDTH
#define	SECURED_RISCV_DEBUG_GPR20_GPR20_MASK
#define	SECURED_RISCV_DEBUG_GPR20_GPR20_RESET
#define	SECURED_RISCV_DEBUG_GPR21_GPR21_BIT
#define	SECURED_RISCV_DEBUG_GPR21_GPR21_WIDTH
#define	SECURED_RISCV_DEBUG_GPR21_GPR21_MASK
#define	SECURED_RISCV_DEBUG_GPR21_GPR21_RESET
#define	SECURED_RISCV_DEBUG_GPR22_GPR22_BIT
#define	SECURED_RISCV_DEBUG_GPR22_GPR22_WIDTH
#define	SECURED_RISCV_DEBUG_GPR22_GPR22_MASK
#define	SECURED_RISCV_DEBUG_GPR22_GPR22_RESET
#define	SECURED_RISCV_DEBUG_GPR23_GPR23_BIT
#define	SECURED_RISCV_DEBUG_GPR23_GPR23_WIDTH
#define	SECURED_RISCV_DEBUG_GPR23_GPR23_MASK
#define	SECURED_RISCV_DEBUG_GPR23_GPR23_RESET
#define	SECURED_RISCV_DEBUG_GPR24_GPR24_BIT
#define	SECURED_RISCV_DEBUG_GPR24_GPR24_WIDTH
#define	SECURED_RISCV_DEBUG_GPR24_GPR24_MASK
#define	SECURED_RISCV_DEBUG_GPR24_GPR24_RESET
#define	SECURED_RISCV_DEBUG_GPR25_GPR25_BIT
#define	SECURED_RISCV_DEBUG_GPR25_GPR25_WIDTH
#define	SECURED_RISCV_DEBUG_GPR25_GPR25_MASK
#define	SECURED_RISCV_DEBUG_GPR25_GPR25_RESET
#define	SECURED_RISCV_DEBUG_GPR26_GPR26_BIT
#define	SECURED_RISCV_DEBUG_GPR26_GPR26_WIDTH
#define	SECURED_RISCV_DEBUG_GPR26_GPR26_MASK
#define	SECURED_RISCV_DEBUG_GPR26_GPR26_RESET
#define	SECURED_RISCV_DEBUG_GPR27_GPR27_BIT
#define	SECURED_RISCV_DEBUG_GPR27_GPR27_WIDTH
#define	SECURED_RISCV_DEBUG_GPR27_GPR27_MASK
#define	SECURED_RISCV_DEBUG_GPR27_GPR27_RESET
#define	SECURED_RISCV_DEBUG_GPR28_GPR28_BIT
#define	SECURED_RISCV_DEBUG_GPR28_GPR28_WIDTH
#define	SECURED_RISCV_DEBUG_GPR28_GPR28_MASK
#define	SECURED_RISCV_DEBUG_GPR28_GPR28_RESET
#define	SECURED_RISCV_DEBUG_GPR29_GPR29_BIT
#define	SECURED_RISCV_DEBUG_GPR29_GPR29_WIDTH
#define	SECURED_RISCV_DEBUG_GPR29_GPR29_MASK
#define	SECURED_RISCV_DEBUG_GPR29_GPR29_RESET
#define	SECURED_RISCV_DEBUG_GPR30_GPR30_BIT
#define	SECURED_RISCV_DEBUG_GPR30_GPR30_WIDTH
#define	SECURED_RISCV_DEBUG_GPR30_GPR30_MASK
#define	SECURED_RISCV_DEBUG_GPR30_GPR30_RESET
#define	SECURED_RISCV_DEBUG_GPR31_GPR31_BIT
#define	SECURED_RISCV_DEBUG_GPR31_GPR31_WIDTH
#define	SECURED_RISCV_DEBUG_GPR31_GPR31_MASK
#define	SECURED_RISCV_DEBUG_GPR31_GPR31_RESET
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_UIE_BIT
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_UIE_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_UIE_MASK
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_UIE_RESET
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MIE_BIT
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MIE_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MIE_MASK
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MIE_RESET
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_UPIE_BIT
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_UPIE_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_UPIE_MASK
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_UPIE_RESET
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MPIE_BIT
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MPIE_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MPIE_MASK
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MPIE_RESET
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MPP_BIT
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MPP_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MPP_MASK
#define	SECURED_RISCV_DEBUG_CSR_MSTATUS_MPP_RESET
#define	SECURED_RISCV_DEBUG_CSR_MTVEC_MTVEC_BIT
#define	SECURED_RISCV_DEBUG_CSR_MTVEC_MTVEC_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MTVEC_MTVEC_MASK
#define	SECURED_RISCV_DEBUG_CSR_MTVEC_MTVEC_RESET
#define	SECURED_RISCV_DEBUG_CSR_MEPC_MEPC_BIT
#define	SECURED_RISCV_DEBUG_CSR_MEPC_MEPC_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MEPC_MEPC_MASK
#define	SECURED_RISCV_DEBUG_CSR_MEPC_MEPC_RESET
#define	SECURED_RISCV_DEBUG_CSR_MCAUSE_CAUSE_BIT
#define	SECURED_RISCV_DEBUG_CSR_MCAUSE_CAUSE_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MCAUSE_CAUSE_MASK
#define	SECURED_RISCV_DEBUG_CSR_MCAUSE_CAUSE_RESET
#define	SECURED_RISCV_DEBUG_CSR_MCAUSE_IRQ_BIT
#define	SECURED_RISCV_DEBUG_CSR_MCAUSE_IRQ_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MCAUSE_IRQ_MASK
#define	SECURED_RISCV_DEBUG_CSR_MCAUSE_IRQ_RESET
#define	SECURED_RISCV_DEBUG_CSR_PCCR_PCCR_BIT
#define	SECURED_RISCV_DEBUG_CSR_PCCR_PCCR_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_PCCR_PCCR_MASK
#define	SECURED_RISCV_DEBUG_CSR_PCCR_PCCR_RESET
#define	SECURED_RISCV_DEBUG_CSR_PCER_PCER_BIT
#define	SECURED_RISCV_DEBUG_CSR_PCER_PCER_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_PCER_PCER_MASK
#define	SECURED_RISCV_DEBUG_CSR_PCER_PCER_RESET
#define	SECURED_RISCV_DEBUG_CSR_PCMR_SAT_BIT
#define	SECURED_RISCV_DEBUG_CSR_PCMR_SAT_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_PCMR_SAT_MASK
#define	SECURED_RISCV_DEBUG_CSR_PCMR_SAT_RESET
#define	SECURED_RISCV_DEBUG_CSR_PCMR_GE_BIT
#define	SECURED_RISCV_DEBUG_CSR_PCMR_GE_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_PCMR_GE_MASK
#define	SECURED_RISCV_DEBUG_CSR_PCMR_GE_RESET
#define	SECURED_RISCV_DEBUG_CSR_HWLP0S_START_BIT
#define	SECURED_RISCV_DEBUG_CSR_HWLP0S_START_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_HWLP0S_START_MASK
#define	SECURED_RISCV_DEBUG_CSR_HWLP0S_START_RESET
#define	SECURED_RISCV_DEBUG_CSR_HWLP0E_END_BIT
#define	SECURED_RISCV_DEBUG_CSR_HWLP0E_END_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_HWLP0E_END_MASK
#define	SECURED_RISCV_DEBUG_CSR_HWLP0E_END_RESET
#define	SECURED_RISCV_DEBUG_CSR_HWLP0C_CNT_BIT
#define	SECURED_RISCV_DEBUG_CSR_HWLP0C_CNT_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_HWLP0C_CNT_MASK
#define	SECURED_RISCV_DEBUG_CSR_HWLP0C_CNT_RESET
#define	SECURED_RISCV_DEBUG_CSR_HWLP1S_START_BIT
#define	SECURED_RISCV_DEBUG_CSR_HWLP1S_START_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_HWLP1S_START_MASK
#define	SECURED_RISCV_DEBUG_CSR_HWLP1S_START_RESET
#define	SECURED_RISCV_DEBUG_CSR_HWLP1E_END_BIT
#define	SECURED_RISCV_DEBUG_CSR_HWLP1E_END_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_HWLP1E_END_MASK
#define	SECURED_RISCV_DEBUG_CSR_HWLP1E_END_RESET
#define	SECURED_RISCV_DEBUG_CSR_HWLP1C_CNT_BIT
#define	SECURED_RISCV_DEBUG_CSR_HWLP1C_CNT_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_HWLP1C_CNT_MASK
#define	SECURED_RISCV_DEBUG_CSR_HWLP1C_CNT_RESET
#define	SECURED_RISCV_DEBUG_CSR_PRIVLV_PLEV_BIT
#define	SECURED_RISCV_DEBUG_CSR_PRIVLV_PLEV_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_PRIVLV_PLEV_MASK
#define	SECURED_RISCV_DEBUG_CSR_PRIVLV_PLEV_RESET
#define	SECURED_RISCV_DEBUG_CSR_UHARTID_CORE_ID_BIT
#define	SECURED_RISCV_DEBUG_CSR_UHARTID_CORE_ID_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_UHARTID_CORE_ID_MASK
#define	SECURED_RISCV_DEBUG_CSR_UHARTID_CORE_ID_RESET
#define	SECURED_RISCV_DEBUG_CSR_UHARTID_CLUSTER_ID_BIT
#define	SECURED_RISCV_DEBUG_CSR_UHARTID_CLUSTER_ID_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_UHARTID_CLUSTER_ID_MASK
#define	SECURED_RISCV_DEBUG_CSR_UHARTID_CLUSTER_ID_RESET
#define	SECURED_RISCV_DEBUG_CSR_MHARTID_CORE_ID_BIT
#define	SECURED_RISCV_DEBUG_CSR_MHARTID_CORE_ID_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MHARTID_CORE_ID_MASK
#define	SECURED_RISCV_DEBUG_CSR_MHARTID_CORE_ID_RESET
#define	SECURED_RISCV_DEBUG_CSR_MHARTID_CLUSTER_ID_BIT
#define	SECURED_RISCV_DEBUG_CSR_MHARTID_CLUSTER_ID_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_MHARTID_CLUSTER_ID_MASK
#define	SECURED_RISCV_DEBUG_CSR_MHARTID_CLUSTER_ID_RESET
#define	SECURED_RISCV_DEBUG_CSR_USTATUS_UIE_BIT
#define	SECURED_RISCV_DEBUG_CSR_USTATUS_UIE_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_USTATUS_UIE_MASK
#define	SECURED_RISCV_DEBUG_CSR_USTATUS_UIE_RESET
#define	SECURED_RISCV_DEBUG_CSR_USTATUS_UPIE_BIT
#define	SECURED_RISCV_DEBUG_CSR_USTATUS_UPIE_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_USTATUS_UPIE_MASK
#define	SECURED_RISCV_DEBUG_CSR_USTATUS_UPIE_RESET
#define	SECURED_RISCV_DEBUG_CSR_UTVEC_UTVEC_BIT
#define	SECURED_RISCV_DEBUG_CSR_UTVEC_UTVEC_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_UTVEC_UTVEC_MASK
#define	SECURED_RISCV_DEBUG_CSR_UTVEC_UTVEC_RESET
#define	SECURED_RISCV_DEBUG_CSR_UEPC_UEPC_BIT
#define	SECURED_RISCV_DEBUG_CSR_UEPC_UEPC_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_UEPC_UEPC_MASK
#define	SECURED_RISCV_DEBUG_CSR_UEPC_UEPC_RESET
#define	SECURED_RISCV_DEBUG_CSR_UCAUSE_CAUSE_BIT
#define	SECURED_RISCV_DEBUG_CSR_UCAUSE_CAUSE_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_UCAUSE_CAUSE_MASK
#define	SECURED_RISCV_DEBUG_CSR_UCAUSE_CAUSE_RESET
#define	SECURED_RISCV_DEBUG_CSR_UCAUSE_IRQ_BIT
#define	SECURED_RISCV_DEBUG_CSR_UCAUSE_IRQ_WIDTH
#define	SECURED_RISCV_DEBUG_CSR_UCAUSE_IRQ_MASK
#define	SECURED_RISCV_DEBUG_CSR_UCAUSE_IRQ_RESET

Macro Definition Documentation

#define SECURED_RISCV_DEBUG_CAUSE_CAUSE_BIT

#define SECURED_RISCV_DEBUG_CAUSE_CAUSE_MASK

#define SECURED_RISCV_DEBUG_CAUSE_CAUSE_RESET

#define SECURED_RISCV_DEBUG_CAUSE_CAUSE_WIDTH

#define SECURED_RISCV_DEBUG_CAUSE_IRQ_BIT

#define SECURED_RISCV_DEBUG_CAUSE_IRQ_MASK

#define SECURED_RISCV_DEBUG_CAUSE_IRQ_RESET

#define SECURED_RISCV_DEBUG_CAUSE_IRQ_WIDTH

#define SECURED_RISCV_DEBUG_CSR_HWLP0C_CNT_BIT

#define SECURED_RISCV_DEBUG_CSR_HWLP0C_CNT_MASK

#define SECURED_RISCV_DEBUG_CSR_HWLP0C_CNT_RESET

#define SECURED_RISCV_DEBUG_CSR_HWLP0C_CNT_WIDTH

#define SECURED_RISCV_DEBUG_CSR_HWLP0E_END_BIT

#define SECURED_RISCV_DEBUG_CSR_HWLP0E_END_MASK

#define SECURED_RISCV_DEBUG_CSR_HWLP0E_END_RESET

#define SECURED_RISCV_DEBUG_CSR_HWLP0E_END_WIDTH

#define SECURED_RISCV_DEBUG_CSR_HWLP0S_START_BIT

#define SECURED_RISCV_DEBUG_CSR_HWLP0S_START_MASK

#define SECURED_RISCV_DEBUG_CSR_HWLP0S_START_RESET

#define SECURED_RISCV_DEBUG_CSR_HWLP0S_START_WIDTH

#define SECURED_RISCV_DEBUG_CSR_HWLP1C_CNT_BIT

#define SECURED_RISCV_DEBUG_CSR_HWLP1C_CNT_MASK

#define SECURED_RISCV_DEBUG_CSR_HWLP1C_CNT_RESET

#define SECURED_RISCV_DEBUG_CSR_HWLP1C_CNT_WIDTH

#define SECURED_RISCV_DEBUG_CSR_HWLP1E_END_BIT

#define SECURED_RISCV_DEBUG_CSR_HWLP1E_END_MASK

#define SECURED_RISCV_DEBUG_CSR_HWLP1E_END_RESET

#define SECURED_RISCV_DEBUG_CSR_HWLP1E_END_WIDTH

#define SECURED_RISCV_DEBUG_CSR_HWLP1S_START_BIT

#define SECURED_RISCV_DEBUG_CSR_HWLP1S_START_MASK

#define SECURED_RISCV_DEBUG_CSR_HWLP1S_START_RESET

#define SECURED_RISCV_DEBUG_CSR_HWLP1S_START_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MCAUSE_CAUSE_BIT

#define SECURED_RISCV_DEBUG_CSR_MCAUSE_CAUSE_MASK

#define SECURED_RISCV_DEBUG_CSR_MCAUSE_CAUSE_RESET

#define SECURED_RISCV_DEBUG_CSR_MCAUSE_CAUSE_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MCAUSE_IRQ_BIT

#define SECURED_RISCV_DEBUG_CSR_MCAUSE_IRQ_MASK

#define SECURED_RISCV_DEBUG_CSR_MCAUSE_IRQ_RESET

#define SECURED_RISCV_DEBUG_CSR_MCAUSE_IRQ_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MEPC_MEPC_BIT

#define SECURED_RISCV_DEBUG_CSR_MEPC_MEPC_MASK

#define SECURED_RISCV_DEBUG_CSR_MEPC_MEPC_RESET

#define SECURED_RISCV_DEBUG_CSR_MEPC_MEPC_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MHARTID_CLUSTER_ID_BIT

#define SECURED_RISCV_DEBUG_CSR_MHARTID_CLUSTER_ID_MASK

#define SECURED_RISCV_DEBUG_CSR_MHARTID_CLUSTER_ID_RESET

#define SECURED_RISCV_DEBUG_CSR_MHARTID_CLUSTER_ID_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MHARTID_CORE_ID_BIT

#define SECURED_RISCV_DEBUG_CSR_MHARTID_CORE_ID_MASK

#define SECURED_RISCV_DEBUG_CSR_MHARTID_CORE_ID_RESET

#define SECURED_RISCV_DEBUG_CSR_MHARTID_CORE_ID_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MIE_BIT

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MIE_MASK

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MIE_RESET

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MIE_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MPIE_BIT

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MPIE_MASK

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MPIE_RESET

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MPIE_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MPP_BIT

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MPP_MASK

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MPP_RESET

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_MPP_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_UIE_BIT

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_UIE_MASK

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_UIE_RESET

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_UIE_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_UPIE_BIT

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_UPIE_MASK

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_UPIE_RESET

#define SECURED_RISCV_DEBUG_CSR_MSTATUS_UPIE_WIDTH

#define SECURED_RISCV_DEBUG_CSR_MTVEC_MTVEC_BIT

#define SECURED_RISCV_DEBUG_CSR_MTVEC_MTVEC_MASK

#define SECURED_RISCV_DEBUG_CSR_MTVEC_MTVEC_RESET

#define SECURED_RISCV_DEBUG_CSR_MTVEC_MTVEC_WIDTH

#define SECURED_RISCV_DEBUG_CSR_PCCR_PCCR_BIT

#define SECURED_RISCV_DEBUG_CSR_PCCR_PCCR_MASK

#define SECURED_RISCV_DEBUG_CSR_PCCR_PCCR_RESET

#define SECURED_RISCV_DEBUG_CSR_PCCR_PCCR_WIDTH

#define SECURED_RISCV_DEBUG_CSR_PCER_PCER_BIT

#define SECURED_RISCV_DEBUG_CSR_PCER_PCER_MASK

#define SECURED_RISCV_DEBUG_CSR_PCER_PCER_RESET

#define SECURED_RISCV_DEBUG_CSR_PCER_PCER_WIDTH

#define SECURED_RISCV_DEBUG_CSR_PCMR_GE_BIT

#define SECURED_RISCV_DEBUG_CSR_PCMR_GE_MASK

#define SECURED_RISCV_DEBUG_CSR_PCMR_GE_RESET

#define SECURED_RISCV_DEBUG_CSR_PCMR_GE_WIDTH

#define SECURED_RISCV_DEBUG_CSR_PCMR_SAT_BIT

#define SECURED_RISCV_DEBUG_CSR_PCMR_SAT_MASK

#define SECURED_RISCV_DEBUG_CSR_PCMR_SAT_RESET

#define SECURED_RISCV_DEBUG_CSR_PCMR_SAT_WIDTH

#define SECURED_RISCV_DEBUG_CSR_PRIVLV_PLEV_BIT

#define SECURED_RISCV_DEBUG_CSR_PRIVLV_PLEV_MASK

#define SECURED_RISCV_DEBUG_CSR_PRIVLV_PLEV_RESET

#define SECURED_RISCV_DEBUG_CSR_PRIVLV_PLEV_WIDTH

#define SECURED_RISCV_DEBUG_CSR_UCAUSE_CAUSE_BIT

#define SECURED_RISCV_DEBUG_CSR_UCAUSE_CAUSE_MASK

#define SECURED_RISCV_DEBUG_CSR_UCAUSE_CAUSE_RESET

#define SECURED_RISCV_DEBUG_CSR_UCAUSE_CAUSE_WIDTH

#define SECURED_RISCV_DEBUG_CSR_UCAUSE_IRQ_BIT

#define SECURED_RISCV_DEBUG_CSR_UCAUSE_IRQ_MASK

#define SECURED_RISCV_DEBUG_CSR_UCAUSE_IRQ_RESET

#define SECURED_RISCV_DEBUG_CSR_UCAUSE_IRQ_WIDTH

#define SECURED_RISCV_DEBUG_CSR_UEPC_UEPC_BIT

#define SECURED_RISCV_DEBUG_CSR_UEPC_UEPC_MASK

#define SECURED_RISCV_DEBUG_CSR_UEPC_UEPC_RESET

#define SECURED_RISCV_DEBUG_CSR_UEPC_UEPC_WIDTH

#define SECURED_RISCV_DEBUG_CSR_UHARTID_CLUSTER_ID_BIT

#define SECURED_RISCV_DEBUG_CSR_UHARTID_CLUSTER_ID_MASK

#define SECURED_RISCV_DEBUG_CSR_UHARTID_CLUSTER_ID_RESET

#define SECURED_RISCV_DEBUG_CSR_UHARTID_CLUSTER_ID_WIDTH

#define SECURED_RISCV_DEBUG_CSR_UHARTID_CORE_ID_BIT

#define SECURED_RISCV_DEBUG_CSR_UHARTID_CORE_ID_MASK

#define SECURED_RISCV_DEBUG_CSR_UHARTID_CORE_ID_RESET

#define SECURED_RISCV_DEBUG_CSR_UHARTID_CORE_ID_WIDTH

#define SECURED_RISCV_DEBUG_CSR_USTATUS_UIE_BIT

#define SECURED_RISCV_DEBUG_CSR_USTATUS_UIE_MASK

#define SECURED_RISCV_DEBUG_CSR_USTATUS_UIE_RESET

#define SECURED_RISCV_DEBUG_CSR_USTATUS_UIE_WIDTH

#define SECURED_RISCV_DEBUG_CSR_USTATUS_UPIE_BIT

#define SECURED_RISCV_DEBUG_CSR_USTATUS_UPIE_MASK

#define SECURED_RISCV_DEBUG_CSR_USTATUS_UPIE_RESET

#define SECURED_RISCV_DEBUG_CSR_USTATUS_UPIE_WIDTH

#define SECURED_RISCV_DEBUG_CSR_UTVEC_UTVEC_BIT

#define SECURED_RISCV_DEBUG_CSR_UTVEC_UTVEC_MASK

#define SECURED_RISCV_DEBUG_CSR_UTVEC_UTVEC_RESET

#define SECURED_RISCV_DEBUG_CSR_UTVEC_UTVEC_WIDTH

#define SECURED_RISCV_DEBUG_CTRL_HALT_BIT

#define SECURED_RISCV_DEBUG_CTRL_HALT_MASK

#define SECURED_RISCV_DEBUG_CTRL_HALT_RESET

#define SECURED_RISCV_DEBUG_CTRL_HALT_WIDTH

#define SECURED_RISCV_DEBUG_CTRL_SSTE_BIT

#define SECURED_RISCV_DEBUG_CTRL_SSTE_MASK

#define SECURED_RISCV_DEBUG_CTRL_SSTE_RESET

#define SECURED_RISCV_DEBUG_CTRL_SSTE_WIDTH

#define SECURED_RISCV_DEBUG_GPR0_GPR0_BIT

#define SECURED_RISCV_DEBUG_GPR0_GPR0_MASK

#define SECURED_RISCV_DEBUG_GPR0_GPR0_RESET

#define SECURED_RISCV_DEBUG_GPR0_GPR0_WIDTH

#define SECURED_RISCV_DEBUG_GPR10_GPR10_BIT

#define SECURED_RISCV_DEBUG_GPR10_GPR10_MASK

#define SECURED_RISCV_DEBUG_GPR10_GPR10_RESET

#define SECURED_RISCV_DEBUG_GPR10_GPR10_WIDTH

#define SECURED_RISCV_DEBUG_GPR11_GPR11_BIT

#define SECURED_RISCV_DEBUG_GPR11_GPR11_MASK

#define SECURED_RISCV_DEBUG_GPR11_GPR11_RESET

#define SECURED_RISCV_DEBUG_GPR11_GPR11_WIDTH

#define SECURED_RISCV_DEBUG_GPR12_GPR12_BIT

#define SECURED_RISCV_DEBUG_GPR12_GPR12_MASK

#define SECURED_RISCV_DEBUG_GPR12_GPR12_RESET

#define SECURED_RISCV_DEBUG_GPR12_GPR12_WIDTH

#define SECURED_RISCV_DEBUG_GPR13_GPR13_BIT

#define SECURED_RISCV_DEBUG_GPR13_GPR13_MASK

#define SECURED_RISCV_DEBUG_GPR13_GPR13_RESET

#define SECURED_RISCV_DEBUG_GPR13_GPR13_WIDTH

#define SECURED_RISCV_DEBUG_GPR14_GPR14_BIT

#define SECURED_RISCV_DEBUG_GPR14_GPR14_MASK

#define SECURED_RISCV_DEBUG_GPR14_GPR14_RESET

#define SECURED_RISCV_DEBUG_GPR14_GPR14_WIDTH

#define SECURED_RISCV_DEBUG_GPR15_GPR15_BIT

#define SECURED_RISCV_DEBUG_GPR15_GPR15_MASK

#define SECURED_RISCV_DEBUG_GPR15_GPR15_RESET

#define SECURED_RISCV_DEBUG_GPR15_GPR15_WIDTH

#define SECURED_RISCV_DEBUG_GPR16_GPR16_BIT

#define SECURED_RISCV_DEBUG_GPR16_GPR16_MASK

#define SECURED_RISCV_DEBUG_GPR16_GPR16_RESET

#define SECURED_RISCV_DEBUG_GPR16_GPR16_WIDTH

#define SECURED_RISCV_DEBUG_GPR17_GPR17_BIT

#define SECURED_RISCV_DEBUG_GPR17_GPR17_MASK

#define SECURED_RISCV_DEBUG_GPR17_GPR17_RESET

#define SECURED_RISCV_DEBUG_GPR17_GPR17_WIDTH

#define SECURED_RISCV_DEBUG_GPR18_GPR18_BIT

#define SECURED_RISCV_DEBUG_GPR18_GPR18_MASK

#define SECURED_RISCV_DEBUG_GPR18_GPR18_RESET

#define SECURED_RISCV_DEBUG_GPR18_GPR18_WIDTH

#define SECURED_RISCV_DEBUG_GPR19_GPR19_BIT

#define SECURED_RISCV_DEBUG_GPR19_GPR19_MASK

#define SECURED_RISCV_DEBUG_GPR19_GPR19_RESET

#define SECURED_RISCV_DEBUG_GPR19_GPR19_WIDTH

#define SECURED_RISCV_DEBUG_GPR1_GPR1_BIT

#define SECURED_RISCV_DEBUG_GPR1_GPR1_MASK

#define SECURED_RISCV_DEBUG_GPR1_GPR1_RESET

#define SECURED_RISCV_DEBUG_GPR1_GPR1_WIDTH

#define SECURED_RISCV_DEBUG_GPR20_GPR20_BIT

#define SECURED_RISCV_DEBUG_GPR20_GPR20_MASK

#define SECURED_RISCV_DEBUG_GPR20_GPR20_RESET

#define SECURED_RISCV_DEBUG_GPR20_GPR20_WIDTH

#define SECURED_RISCV_DEBUG_GPR21_GPR21_BIT

#define SECURED_RISCV_DEBUG_GPR21_GPR21_MASK

#define SECURED_RISCV_DEBUG_GPR21_GPR21_RESET

#define SECURED_RISCV_DEBUG_GPR21_GPR21_WIDTH

#define SECURED_RISCV_DEBUG_GPR22_GPR22_BIT

#define SECURED_RISCV_DEBUG_GPR22_GPR22_MASK

#define SECURED_RISCV_DEBUG_GPR22_GPR22_RESET

#define SECURED_RISCV_DEBUG_GPR22_GPR22_WIDTH

#define SECURED_RISCV_DEBUG_GPR23_GPR23_BIT

#define SECURED_RISCV_DEBUG_GPR23_GPR23_MASK

#define SECURED_RISCV_DEBUG_GPR23_GPR23_RESET

#define SECURED_RISCV_DEBUG_GPR23_GPR23_WIDTH

#define SECURED_RISCV_DEBUG_GPR24_GPR24_BIT

#define SECURED_RISCV_DEBUG_GPR24_GPR24_MASK

#define SECURED_RISCV_DEBUG_GPR24_GPR24_RESET

#define SECURED_RISCV_DEBUG_GPR24_GPR24_WIDTH

#define SECURED_RISCV_DEBUG_GPR25_GPR25_BIT

#define SECURED_RISCV_DEBUG_GPR25_GPR25_MASK

#define SECURED_RISCV_DEBUG_GPR25_GPR25_RESET

#define SECURED_RISCV_DEBUG_GPR25_GPR25_WIDTH

#define SECURED_RISCV_DEBUG_GPR26_GPR26_BIT

#define SECURED_RISCV_DEBUG_GPR26_GPR26_MASK

#define SECURED_RISCV_DEBUG_GPR26_GPR26_RESET

#define SECURED_RISCV_DEBUG_GPR26_GPR26_WIDTH

#define SECURED_RISCV_DEBUG_GPR27_GPR27_BIT

#define SECURED_RISCV_DEBUG_GPR27_GPR27_MASK

#define SECURED_RISCV_DEBUG_GPR27_GPR27_RESET

#define SECURED_RISCV_DEBUG_GPR27_GPR27_WIDTH

#define SECURED_RISCV_DEBUG_GPR28_GPR28_BIT

#define SECURED_RISCV_DEBUG_GPR28_GPR28_MASK

#define SECURED_RISCV_DEBUG_GPR28_GPR28_RESET

#define SECURED_RISCV_DEBUG_GPR28_GPR28_WIDTH

#define SECURED_RISCV_DEBUG_GPR29_GPR29_BIT

#define SECURED_RISCV_DEBUG_GPR29_GPR29_MASK

#define SECURED_RISCV_DEBUG_GPR29_GPR29_RESET

#define SECURED_RISCV_DEBUG_GPR29_GPR29_WIDTH

#define SECURED_RISCV_DEBUG_GPR2_GPR2_BIT

#define SECURED_RISCV_DEBUG_GPR2_GPR2_MASK

#define SECURED_RISCV_DEBUG_GPR2_GPR2_RESET

#define SECURED_RISCV_DEBUG_GPR2_GPR2_WIDTH

#define SECURED_RISCV_DEBUG_GPR30_GPR30_BIT

#define SECURED_RISCV_DEBUG_GPR30_GPR30_MASK

#define SECURED_RISCV_DEBUG_GPR30_GPR30_RESET

#define SECURED_RISCV_DEBUG_GPR30_GPR30_WIDTH

#define SECURED_RISCV_DEBUG_GPR31_GPR31_BIT

#define SECURED_RISCV_DEBUG_GPR31_GPR31_MASK

#define SECURED_RISCV_DEBUG_GPR31_GPR31_RESET

#define SECURED_RISCV_DEBUG_GPR31_GPR31_WIDTH

#define SECURED_RISCV_DEBUG_GPR3_GPR3_BIT

#define SECURED_RISCV_DEBUG_GPR3_GPR3_MASK

#define SECURED_RISCV_DEBUG_GPR3_GPR3_RESET

#define SECURED_RISCV_DEBUG_GPR3_GPR3_WIDTH

#define SECURED_RISCV_DEBUG_GPR4_GPR4_BIT

#define SECURED_RISCV_DEBUG_GPR4_GPR4_MASK

#define SECURED_RISCV_DEBUG_GPR4_GPR4_RESET

#define SECURED_RISCV_DEBUG_GPR4_GPR4_WIDTH

#define SECURED_RISCV_DEBUG_GPR5_GPR5_BIT

#define SECURED_RISCV_DEBUG_GPR5_GPR5_MASK

#define SECURED_RISCV_DEBUG_GPR5_GPR5_RESET

#define SECURED_RISCV_DEBUG_GPR5_GPR5_WIDTH

#define SECURED_RISCV_DEBUG_GPR6_GPR6_BIT

#define SECURED_RISCV_DEBUG_GPR6_GPR6_MASK

#define SECURED_RISCV_DEBUG_GPR6_GPR6_RESET

#define SECURED_RISCV_DEBUG_GPR6_GPR6_WIDTH

#define SECURED_RISCV_DEBUG_GPR7_GPR7_BIT

#define SECURED_RISCV_DEBUG_GPR7_GPR7_MASK

#define SECURED_RISCV_DEBUG_GPR7_GPR7_RESET

#define SECURED_RISCV_DEBUG_GPR7_GPR7_WIDTH

#define SECURED_RISCV_DEBUG_GPR8_GPR8_BIT

#define SECURED_RISCV_DEBUG_GPR8_GPR8_MASK

#define SECURED_RISCV_DEBUG_GPR8_GPR8_RESET

#define SECURED_RISCV_DEBUG_GPR8_GPR8_WIDTH

#define SECURED_RISCV_DEBUG_GPR9_GPR9_BIT

#define SECURED_RISCV_DEBUG_GPR9_GPR9_MASK

#define SECURED_RISCV_DEBUG_GPR9_GPR9_RESET

#define SECURED_RISCV_DEBUG_GPR9_GPR9_WIDTH

#define SECURED_RISCV_DEBUG_HIT_SLEEP_BIT

#define SECURED_RISCV_DEBUG_HIT_SLEEP_MASK

#define SECURED_RISCV_DEBUG_HIT_SLEEP_RESET

#define SECURED_RISCV_DEBUG_HIT_SLEEP_WIDTH

#define SECURED_RISCV_DEBUG_HIT_SSTH_BIT

#define SECURED_RISCV_DEBUG_HIT_SSTH_MASK

#define SECURED_RISCV_DEBUG_HIT_SSTH_RESET

#define SECURED_RISCV_DEBUG_HIT_SSTH_WIDTH

#define SECURED_RISCV_DEBUG_IE_EBRK_BIT

#define SECURED_RISCV_DEBUG_IE_EBRK_MASK

#define SECURED_RISCV_DEBUG_IE_EBRK_RESET

#define SECURED_RISCV_DEBUG_IE_EBRK_WIDTH

#define SECURED_RISCV_DEBUG_IE_ECALL_BIT

#define SECURED_RISCV_DEBUG_IE_ECALL_MASK

#define SECURED_RISCV_DEBUG_IE_ECALL_RESET

#define SECURED_RISCV_DEBUG_IE_ECALL_WIDTH

#define SECURED_RISCV_DEBUG_IE_EILL_BIT

#define SECURED_RISCV_DEBUG_IE_EILL_MASK

#define SECURED_RISCV_DEBUG_IE_EILL_RESET

#define SECURED_RISCV_DEBUG_IE_EILL_WIDTH

#define SECURED_RISCV_DEBUG_IE_ELSU_BIT

#define SECURED_RISCV_DEBUG_IE_ELSU_DUP_BIT

#define SECURED_RISCV_DEBUG_IE_ELSU_DUP_MASK

#define SECURED_RISCV_DEBUG_IE_ELSU_DUP_RESET

#define SECURED_RISCV_DEBUG_IE_ELSU_DUP_WIDTH

#define SECURED_RISCV_DEBUG_IE_ELSU_MASK

#define SECURED_RISCV_DEBUG_IE_ELSU_RESET

#define SECURED_RISCV_DEBUG_IE_ELSU_WIDTH

#define SECURED_RISCV_DEBUG_NPC_NPC_BIT

#define SECURED_RISCV_DEBUG_NPC_NPC_MASK

#define SECURED_RISCV_DEBUG_NPC_NPC_RESET

#define SECURED_RISCV_DEBUG_NPC_NPC_WIDTH

#define SECURED_RISCV_DEBUG_PPC_PPC_BIT

#define SECURED_RISCV_DEBUG_PPC_PPC_MASK

#define SECURED_RISCV_DEBUG_PPC_PPC_RESET

#define SECURED_RISCV_DEBUG_PPC_PPC_WIDTH