pwm_regfields.h File Reference

Macros
#define	ADV_TIMER_T0_CMD_START_BIT
#define	ADV_TIMER_T0_CMD_START_WIDTH
#define	ADV_TIMER_T0_CMD_START_MASK
#define	ADV_TIMER_T0_CMD_START_RESET
#define	ADV_TIMER_T0_CMD_STOP_BIT
#define	ADV_TIMER_T0_CMD_STOP_WIDTH
#define	ADV_TIMER_T0_CMD_STOP_MASK
#define	ADV_TIMER_T0_CMD_STOP_RESET
#define	ADV_TIMER_T0_CMD_UPDATE_BIT
#define	ADV_TIMER_T0_CMD_UPDATE_WIDTH
#define	ADV_TIMER_T0_CMD_UPDATE_MASK
#define	ADV_TIMER_T0_CMD_UPDATE_RESET
#define	ADV_TIMER_T0_CMD_RESET_BIT
#define	ADV_TIMER_T0_CMD_RESET_WIDTH
#define	ADV_TIMER_T0_CMD_RESET_MASK
#define	ADV_TIMER_T0_CMD_RESET_RESET
#define	ADV_TIMER_T0_CMD_ARM_BIT
#define	ADV_TIMER_T0_CMD_ARM_WIDTH
#define	ADV_TIMER_T0_CMD_ARM_MASK
#define	ADV_TIMER_T0_CMD_ARM_RESET
#define	ADV_TIMER_T0_CMD_RFU_BIT
#define	ADV_TIMER_T0_CMD_RFU_WIDTH
#define	ADV_TIMER_T0_CMD_RFU_MASK
#define	ADV_TIMER_T0_CMD_RFU_RESET
#define	ADV_TIMER_T0_CONFIG_INSEL_BIT
#define	ADV_TIMER_T0_CONFIG_INSEL_WIDTH
#define	ADV_TIMER_T0_CONFIG_INSEL_MASK
#define	ADV_TIMER_T0_CONFIG_INSEL_RESET
#define	ADV_TIMER_T0_CONFIG_MODE_BIT
#define	ADV_TIMER_T0_CONFIG_MODE_WIDTH
#define	ADV_TIMER_T0_CONFIG_MODE_MASK
#define	ADV_TIMER_T0_CONFIG_MODE_RESET
#define	ADV_TIMER_T0_CONFIG_CLKSEL_BIT
#define	ADV_TIMER_T0_CONFIG_CLKSEL_WIDTH
#define	ADV_TIMER_T0_CONFIG_CLKSEL_MASK
#define	ADV_TIMER_T0_CONFIG_CLKSEL_RESET
#define	ADV_TIMER_T0_CONFIG_UPDOWNSEL_BIT
#define	ADV_TIMER_T0_CONFIG_UPDOWNSEL_WIDTH
#define	ADV_TIMER_T0_CONFIG_UPDOWNSEL_MASK
#define	ADV_TIMER_T0_CONFIG_UPDOWNSEL_RESET
#define	ADV_TIMER_T0_CONFIG_PRESC_BIT
#define	ADV_TIMER_T0_CONFIG_PRESC_WIDTH
#define	ADV_TIMER_T0_CONFIG_PRESC_MASK
#define	ADV_TIMER_T0_CONFIG_PRESC_RESET
#define	ADV_TIMER_T0_THRESHOLD_TH_LO_BIT
#define	ADV_TIMER_T0_THRESHOLD_TH_LO_WIDTH
#define	ADV_TIMER_T0_THRESHOLD_TH_LO_MASK
#define	ADV_TIMER_T0_THRESHOLD_TH_LO_RESET
#define	ADV_TIMER_T0_THRESHOLD_TH_HI_BIT
#define	ADV_TIMER_T0_THRESHOLD_TH_HI_WIDTH
#define	ADV_TIMER_T0_THRESHOLD_TH_HI_MASK
#define	ADV_TIMER_T0_THRESHOLD_TH_HI_RESET
#define	ADV_TIMER_T0_TH_CHANNEL0_TH_BIT
#define	ADV_TIMER_T0_TH_CHANNEL0_TH_WIDTH
#define	ADV_TIMER_T0_TH_CHANNEL0_TH_MASK
#define	ADV_TIMER_T0_TH_CHANNEL0_TH_RESET
#define	ADV_TIMER_T0_TH_CHANNEL0_MODE_BIT
#define	ADV_TIMER_T0_TH_CHANNEL0_MODE_WIDTH
#define	ADV_TIMER_T0_TH_CHANNEL0_MODE_MASK
#define	ADV_TIMER_T0_TH_CHANNEL0_MODE_RESET
#define	ADV_TIMER_T0_TH_CHANNEL1_TH_BIT
#define	ADV_TIMER_T0_TH_CHANNEL1_TH_WIDTH
#define	ADV_TIMER_T0_TH_CHANNEL1_TH_MASK
#define	ADV_TIMER_T0_TH_CHANNEL1_TH_RESET
#define	ADV_TIMER_T0_TH_CHANNEL1_MODE_BIT
#define	ADV_TIMER_T0_TH_CHANNEL1_MODE_WIDTH
#define	ADV_TIMER_T0_TH_CHANNEL1_MODE_MASK
#define	ADV_TIMER_T0_TH_CHANNEL1_MODE_RESET
#define	ADV_TIMER_T0_TH_CHANNEL2_TH_BIT
#define	ADV_TIMER_T0_TH_CHANNEL2_TH_WIDTH
#define	ADV_TIMER_T0_TH_CHANNEL2_TH_MASK
#define	ADV_TIMER_T0_TH_CHANNEL2_TH_RESET
#define	ADV_TIMER_T0_TH_CHANNEL2_MODE_BIT
#define	ADV_TIMER_T0_TH_CHANNEL2_MODE_WIDTH
#define	ADV_TIMER_T0_TH_CHANNEL2_MODE_MASK
#define	ADV_TIMER_T0_TH_CHANNEL2_MODE_RESET
#define	ADV_TIMER_T0_TH_CHANNEL3_TH_BIT
#define	ADV_TIMER_T0_TH_CHANNEL3_TH_WIDTH
#define	ADV_TIMER_T0_TH_CHANNEL3_TH_MASK
#define	ADV_TIMER_T0_TH_CHANNEL3_TH_RESET
#define	ADV_TIMER_T0_TH_CHANNEL3_MODE_BIT
#define	ADV_TIMER_T0_TH_CHANNEL3_MODE_WIDTH
#define	ADV_TIMER_T0_TH_CHANNEL3_MODE_MASK
#define	ADV_TIMER_T0_TH_CHANNEL3_MODE_RESET
#define	ADV_TIMER_T0_COUNTER_COUNTER_BIT
#define	ADV_TIMER_T0_COUNTER_COUNTER_WIDTH
#define	ADV_TIMER_T0_COUNTER_COUNTER_MASK
#define	ADV_TIMER_T0_COUNTER_COUNTER_RESET
#define	ADV_TIMER_T1_CMD_START_BIT
#define	ADV_TIMER_T1_CMD_START_WIDTH
#define	ADV_TIMER_T1_CMD_START_MASK
#define	ADV_TIMER_T1_CMD_START_RESET
#define	ADV_TIMER_T1_CMD_STOP_BIT
#define	ADV_TIMER_T1_CMD_STOP_WIDTH
#define	ADV_TIMER_T1_CMD_STOP_MASK
#define	ADV_TIMER_T1_CMD_STOP_RESET
#define	ADV_TIMER_T1_CMD_UPDATE_BIT
#define	ADV_TIMER_T1_CMD_UPDATE_WIDTH
#define	ADV_TIMER_T1_CMD_UPDATE_MASK
#define	ADV_TIMER_T1_CMD_UPDATE_RESET
#define	ADV_TIMER_T1_CMD_RESET_BIT
#define	ADV_TIMER_T1_CMD_RESET_WIDTH
#define	ADV_TIMER_T1_CMD_RESET_MASK
#define	ADV_TIMER_T1_CMD_RESET_RESET
#define	ADV_TIMER_T1_CMD_ARM_BIT
#define	ADV_TIMER_T1_CMD_ARM_WIDTH
#define	ADV_TIMER_T1_CMD_ARM_MASK
#define	ADV_TIMER_T1_CMD_ARM_RESET
#define	ADV_TIMER_T1_CONFIG_INSEL_BIT
#define	ADV_TIMER_T1_CONFIG_INSEL_WIDTH
#define	ADV_TIMER_T1_CONFIG_INSEL_MASK
#define	ADV_TIMER_T1_CONFIG_INSEL_RESET
#define	ADV_TIMER_T1_CONFIG_MODE_BIT
#define	ADV_TIMER_T1_CONFIG_MODE_WIDTH
#define	ADV_TIMER_T1_CONFIG_MODE_MASK
#define	ADV_TIMER_T1_CONFIG_MODE_RESET
#define	ADV_TIMER_T1_CONFIG_CLKSEL_BIT
#define	ADV_TIMER_T1_CONFIG_CLKSEL_WIDTH
#define	ADV_TIMER_T1_CONFIG_CLKSEL_MASK
#define	ADV_TIMER_T1_CONFIG_CLKSEL_RESET
#define	ADV_TIMER_T1_CONFIG_UPDOWNSEL_BIT
#define	ADV_TIMER_T1_CONFIG_UPDOWNSEL_WIDTH
#define	ADV_TIMER_T1_CONFIG_UPDOWNSEL_MASK
#define	ADV_TIMER_T1_CONFIG_UPDOWNSEL_RESET
#define	ADV_TIMER_T1_CONFIG_PRESC_BIT
#define	ADV_TIMER_T1_CONFIG_PRESC_WIDTH
#define	ADV_TIMER_T1_CONFIG_PRESC_MASK
#define	ADV_TIMER_T1_CONFIG_PRESC_RESET
#define	ADV_TIMER_T1_THRESHOLD_TH_LO_BIT
#define	ADV_TIMER_T1_THRESHOLD_TH_LO_WIDTH
#define	ADV_TIMER_T1_THRESHOLD_TH_LO_MASK
#define	ADV_TIMER_T1_THRESHOLD_TH_LO_RESET
#define	ADV_TIMER_T1_THRESHOLD_TH_HI_BIT
#define	ADV_TIMER_T1_THRESHOLD_TH_HI_WIDTH
#define	ADV_TIMER_T1_THRESHOLD_TH_HI_MASK
#define	ADV_TIMER_T1_THRESHOLD_TH_HI_RESET
#define	ADV_TIMER_T1_TH_CHANNEL0_TH_BIT
#define	ADV_TIMER_T1_TH_CHANNEL0_TH_WIDTH
#define	ADV_TIMER_T1_TH_CHANNEL0_TH_MASK
#define	ADV_TIMER_T1_TH_CHANNEL0_TH_RESET
#define	ADV_TIMER_T1_TH_CHANNEL0_MODE_BIT
#define	ADV_TIMER_T1_TH_CHANNEL0_MODE_WIDTH
#define	ADV_TIMER_T1_TH_CHANNEL0_MODE_MASK
#define	ADV_TIMER_T1_TH_CHANNEL0_MODE_RESET
#define	ADV_TIMER_T1_TH_CHANNEL1_TH_BIT
#define	ADV_TIMER_T1_TH_CHANNEL1_TH_WIDTH
#define	ADV_TIMER_T1_TH_CHANNEL1_TH_MASK
#define	ADV_TIMER_T1_TH_CHANNEL1_TH_RESET
#define	ADV_TIMER_T1_TH_CHANNEL1_MODE_BIT
#define	ADV_TIMER_T1_TH_CHANNEL1_MODE_WIDTH
#define	ADV_TIMER_T1_TH_CHANNEL1_MODE_MASK
#define	ADV_TIMER_T1_TH_CHANNEL1_MODE_RESET
#define	ADV_TIMER_T1_TH_CHANNEL2_TH_BIT
#define	ADV_TIMER_T1_TH_CHANNEL2_TH_WIDTH
#define	ADV_TIMER_T1_TH_CHANNEL2_TH_MASK
#define	ADV_TIMER_T1_TH_CHANNEL2_TH_RESET
#define	ADV_TIMER_T1_TH_CHANNEL2_MODE_BIT
#define	ADV_TIMER_T1_TH_CHANNEL2_MODE_WIDTH
#define	ADV_TIMER_T1_TH_CHANNEL2_MODE_MASK
#define	ADV_TIMER_T1_TH_CHANNEL2_MODE_RESET
#define	ADV_TIMER_T1_TH_CHANNEL3_TH_BIT
#define	ADV_TIMER_T1_TH_CHANNEL3_TH_WIDTH
#define	ADV_TIMER_T1_TH_CHANNEL3_TH_MASK
#define	ADV_TIMER_T1_TH_CHANNEL3_TH_RESET
#define	ADV_TIMER_T1_TH_CHANNEL3_MODE_BIT
#define	ADV_TIMER_T1_TH_CHANNEL3_MODE_WIDTH
#define	ADV_TIMER_T1_TH_CHANNEL3_MODE_MASK
#define	ADV_TIMER_T1_TH_CHANNEL3_MODE_RESET
#define	ADV_TIMER_T1_COUNTER_COUNTER_BIT
#define	ADV_TIMER_T1_COUNTER_COUNTER_WIDTH
#define	ADV_TIMER_T1_COUNTER_COUNTER_MASK
#define	ADV_TIMER_T1_COUNTER_COUNTER_RESET
#define	ADV_TIMER_T2_CMD_START_BIT
#define	ADV_TIMER_T2_CMD_START_WIDTH
#define	ADV_TIMER_T2_CMD_START_MASK
#define	ADV_TIMER_T2_CMD_START_RESET
#define	ADV_TIMER_T2_CMD_STOP_BIT
#define	ADV_TIMER_T2_CMD_STOP_WIDTH
#define	ADV_TIMER_T2_CMD_STOP_MASK
#define	ADV_TIMER_T2_CMD_STOP_RESET
#define	ADV_TIMER_T2_CMD_UPDATE_BIT
#define	ADV_TIMER_T2_CMD_UPDATE_WIDTH
#define	ADV_TIMER_T2_CMD_UPDATE_MASK
#define	ADV_TIMER_T2_CMD_UPDATE_RESET
#define	ADV_TIMER_T2_CMD_RESET_BIT
#define	ADV_TIMER_T2_CMD_RESET_WIDTH
#define	ADV_TIMER_T2_CMD_RESET_MASK
#define	ADV_TIMER_T2_CMD_RESET_RESET
#define	ADV_TIMER_T2_CMD_ARM_BIT
#define	ADV_TIMER_T2_CMD_ARM_WIDTH
#define	ADV_TIMER_T2_CMD_ARM_MASK
#define	ADV_TIMER_T2_CMD_ARM_RESET
#define	ADV_TIMER_T2_CONFIG_INSEL_BIT
#define	ADV_TIMER_T2_CONFIG_INSEL_WIDTH
#define	ADV_TIMER_T2_CONFIG_INSEL_MASK
#define	ADV_TIMER_T2_CONFIG_INSEL_RESET
#define	ADV_TIMER_T2_CONFIG_MODE_BIT
#define	ADV_TIMER_T2_CONFIG_MODE_WIDTH
#define	ADV_TIMER_T2_CONFIG_MODE_MASK
#define	ADV_TIMER_T2_CONFIG_MODE_RESET
#define	ADV_TIMER_T2_CONFIG_CLKSEL_BIT
#define	ADV_TIMER_T2_CONFIG_CLKSEL_WIDTH
#define	ADV_TIMER_T2_CONFIG_CLKSEL_MASK
#define	ADV_TIMER_T2_CONFIG_CLKSEL_RESET
#define	ADV_TIMER_T2_CONFIG_UPDOWNSEL_BIT
#define	ADV_TIMER_T2_CONFIG_UPDOWNSEL_WIDTH
#define	ADV_TIMER_T2_CONFIG_UPDOWNSEL_MASK
#define	ADV_TIMER_T2_CONFIG_UPDOWNSEL_RESET
#define	ADV_TIMER_T2_CONFIG_PRESC_BIT
#define	ADV_TIMER_T2_CONFIG_PRESC_WIDTH
#define	ADV_TIMER_T2_CONFIG_PRESC_MASK
#define	ADV_TIMER_T2_CONFIG_PRESC_RESET
#define	ADV_TIMER_T2_THRESHOLD_TH_LO_BIT
#define	ADV_TIMER_T2_THRESHOLD_TH_LO_WIDTH
#define	ADV_TIMER_T2_THRESHOLD_TH_LO_MASK
#define	ADV_TIMER_T2_THRESHOLD_TH_LO_RESET
#define	ADV_TIMER_T2_THRESHOLD_TH_HI_BIT
#define	ADV_TIMER_T2_THRESHOLD_TH_HI_WIDTH
#define	ADV_TIMER_T2_THRESHOLD_TH_HI_MASK
#define	ADV_TIMER_T2_THRESHOLD_TH_HI_RESET
#define	ADV_TIMER_T2_TH_CHANNEL0_TH_BIT
#define	ADV_TIMER_T2_TH_CHANNEL0_TH_WIDTH
#define	ADV_TIMER_T2_TH_CHANNEL0_TH_MASK
#define	ADV_TIMER_T2_TH_CHANNEL0_TH_RESET
#define	ADV_TIMER_T2_TH_CHANNEL0_MODE_BIT
#define	ADV_TIMER_T2_TH_CHANNEL0_MODE_WIDTH
#define	ADV_TIMER_T2_TH_CHANNEL0_MODE_MASK
#define	ADV_TIMER_T2_TH_CHANNEL0_MODE_RESET
#define	ADV_TIMER_T2_TH_CHANNEL1_TH_BIT
#define	ADV_TIMER_T2_TH_CHANNEL1_TH_WIDTH
#define	ADV_TIMER_T2_TH_CHANNEL1_TH_MASK
#define	ADV_TIMER_T2_TH_CHANNEL1_TH_RESET
#define	ADV_TIMER_T2_TH_CHANNEL1_MODE_BIT
#define	ADV_TIMER_T2_TH_CHANNEL1_MODE_WIDTH
#define	ADV_TIMER_T2_TH_CHANNEL1_MODE_MASK
#define	ADV_TIMER_T2_TH_CHANNEL1_MODE_RESET
#define	ADV_TIMER_T2_TH_CHANNEL2_TH_BIT
#define	ADV_TIMER_T2_TH_CHANNEL2_TH_WIDTH
#define	ADV_TIMER_T2_TH_CHANNEL2_TH_MASK
#define	ADV_TIMER_T2_TH_CHANNEL2_TH_RESET
#define	ADV_TIMER_T2_TH_CHANNEL2_MODE_BIT
#define	ADV_TIMER_T2_TH_CHANNEL2_MODE_WIDTH
#define	ADV_TIMER_T2_TH_CHANNEL2_MODE_MASK
#define	ADV_TIMER_T2_TH_CHANNEL2_MODE_RESET
#define	ADV_TIMER_T2_TH_CHANNEL3_TH_BIT
#define	ADV_TIMER_T2_TH_CHANNEL3_TH_WIDTH
#define	ADV_TIMER_T2_TH_CHANNEL3_TH_MASK
#define	ADV_TIMER_T2_TH_CHANNEL3_TH_RESET
#define	ADV_TIMER_T2_TH_CHANNEL3_MODE_BIT
#define	ADV_TIMER_T2_TH_CHANNEL3_MODE_WIDTH
#define	ADV_TIMER_T2_TH_CHANNEL3_MODE_MASK
#define	ADV_TIMER_T2_TH_CHANNEL3_MODE_RESET
#define	ADV_TIMER_T2_COUNTER_COUNTER_BIT
#define	ADV_TIMER_T2_COUNTER_COUNTER_WIDTH
#define	ADV_TIMER_T2_COUNTER_COUNTER_MASK
#define	ADV_TIMER_T2_COUNTER_COUNTER_RESET
#define	ADV_TIMER_T3_CMD_START_BIT
#define	ADV_TIMER_T3_CMD_START_WIDTH
#define	ADV_TIMER_T3_CMD_START_MASK
#define	ADV_TIMER_T3_CMD_START_RESET
#define	ADV_TIMER_T3_CMD_STOP_BIT
#define	ADV_TIMER_T3_CMD_STOP_WIDTH
#define	ADV_TIMER_T3_CMD_STOP_MASK
#define	ADV_TIMER_T3_CMD_STOP_RESET
#define	ADV_TIMER_T3_CMD_UPDATE_BIT
#define	ADV_TIMER_T3_CMD_UPDATE_WIDTH
#define	ADV_TIMER_T3_CMD_UPDATE_MASK
#define	ADV_TIMER_T3_CMD_UPDATE_RESET
#define	ADV_TIMER_T3_CMD_RESET_BIT
#define	ADV_TIMER_T3_CMD_RESET_WIDTH
#define	ADV_TIMER_T3_CMD_RESET_MASK
#define	ADV_TIMER_T3_CMD_RESET_RESET
#define	ADV_TIMER_T3_CMD_ARM_BIT
#define	ADV_TIMER_T3_CMD_ARM_WIDTH
#define	ADV_TIMER_T3_CMD_ARM_MASK
#define	ADV_TIMER_T3_CMD_ARM_RESET
#define	ADV_TIMER_T3_CONFIG_INSEL_BIT
#define	ADV_TIMER_T3_CONFIG_INSEL_WIDTH
#define	ADV_TIMER_T3_CONFIG_INSEL_MASK
#define	ADV_TIMER_T3_CONFIG_INSEL_RESET
#define	ADV_TIMER_T3_CONFIG_MODE_BIT
#define	ADV_TIMER_T3_CONFIG_MODE_WIDTH
#define	ADV_TIMER_T3_CONFIG_MODE_MASK
#define	ADV_TIMER_T3_CONFIG_MODE_RESET
#define	ADV_TIMER_T3_CONFIG_CLKSEL_BIT
#define	ADV_TIMER_T3_CONFIG_CLKSEL_WIDTH
#define	ADV_TIMER_T3_CONFIG_CLKSEL_MASK
#define	ADV_TIMER_T3_CONFIG_CLKSEL_RESET
#define	ADV_TIMER_T3_CONFIG_UPDOWNSEL_BIT
#define	ADV_TIMER_T3_CONFIG_UPDOWNSEL_WIDTH
#define	ADV_TIMER_T3_CONFIG_UPDOWNSEL_MASK
#define	ADV_TIMER_T3_CONFIG_UPDOWNSEL_RESET
#define	ADV_TIMER_T3_CONFIG_PRESC_BIT
#define	ADV_TIMER_T3_CONFIG_PRESC_WIDTH
#define	ADV_TIMER_T3_CONFIG_PRESC_MASK
#define	ADV_TIMER_T3_CONFIG_PRESC_RESET
#define	ADV_TIMER_T3_THRESHOLD_TH_LO_BIT
#define	ADV_TIMER_T3_THRESHOLD_TH_LO_WIDTH
#define	ADV_TIMER_T3_THRESHOLD_TH_LO_MASK
#define	ADV_TIMER_T3_THRESHOLD_TH_LO_RESET
#define	ADV_TIMER_T3_THRESHOLD_TH_HI_BIT
#define	ADV_TIMER_T3_THRESHOLD_TH_HI_WIDTH
#define	ADV_TIMER_T3_THRESHOLD_TH_HI_MASK
#define	ADV_TIMER_T3_THRESHOLD_TH_HI_RESET
#define	ADV_TIMER_T3_TH_CHANNEL0_TH_BIT
#define	ADV_TIMER_T3_TH_CHANNEL0_TH_WIDTH
#define	ADV_TIMER_T3_TH_CHANNEL0_TH_MASK
#define	ADV_TIMER_T3_TH_CHANNEL0_TH_RESET
#define	ADV_TIMER_T3_TH_CHANNEL0_MODE_BIT
#define	ADV_TIMER_T3_TH_CHANNEL0_MODE_WIDTH
#define	ADV_TIMER_T3_TH_CHANNEL0_MODE_MASK
#define	ADV_TIMER_T3_TH_CHANNEL0_MODE_RESET
#define	ADV_TIMER_T3_TH_CHANNEL1_TH_BIT
#define	ADV_TIMER_T3_TH_CHANNEL1_TH_WIDTH
#define	ADV_TIMER_T3_TH_CHANNEL1_TH_MASK
#define	ADV_TIMER_T3_TH_CHANNEL1_TH_RESET
#define	ADV_TIMER_T3_TH_CHANNEL1_MODE_BIT
#define	ADV_TIMER_T3_TH_CHANNEL1_MODE_WIDTH
#define	ADV_TIMER_T3_TH_CHANNEL1_MODE_MASK
#define	ADV_TIMER_T3_TH_CHANNEL1_MODE_RESET
#define	ADV_TIMER_T3_TH_CHANNEL2_TH_BIT
#define	ADV_TIMER_T3_TH_CHANNEL2_TH_WIDTH
#define	ADV_TIMER_T3_TH_CHANNEL2_TH_MASK
#define	ADV_TIMER_T3_TH_CHANNEL2_TH_RESET
#define	ADV_TIMER_T3_TH_CHANNEL2_MODE_BIT
#define	ADV_TIMER_T3_TH_CHANNEL2_MODE_WIDTH
#define	ADV_TIMER_T3_TH_CHANNEL2_MODE_MASK
#define	ADV_TIMER_T3_TH_CHANNEL2_MODE_RESET
#define	ADV_TIMER_T3_TH_CHANNEL3_TH_BIT
#define	ADV_TIMER_T3_TH_CHANNEL3_TH_WIDTH
#define	ADV_TIMER_T3_TH_CHANNEL3_TH_MASK
#define	ADV_TIMER_T3_TH_CHANNEL3_TH_RESET
#define	ADV_TIMER_T3_TH_CHANNEL3_MODE_BIT
#define	ADV_TIMER_T3_TH_CHANNEL3_MODE_WIDTH
#define	ADV_TIMER_T3_TH_CHANNEL3_MODE_MASK
#define	ADV_TIMER_T3_TH_CHANNEL3_MODE_RESET
#define	ADV_TIMER_T3_COUNTER_COUNTER_BIT
#define	ADV_TIMER_T3_COUNTER_COUNTER_WIDTH
#define	ADV_TIMER_T3_COUNTER_COUNTER_MASK
#define	ADV_TIMER_T3_COUNTER_COUNTER_RESET
#define	ADV_TIMER_EVENT_CFG_SEL0_BIT
#define	ADV_TIMER_EVENT_CFG_SEL0_WIDTH
#define	ADV_TIMER_EVENT_CFG_SEL0_MASK
#define	ADV_TIMER_EVENT_CFG_SEL0_RESET
#define	ADV_TIMER_EVENT_CFG_SEL1_BIT
#define	ADV_TIMER_EVENT_CFG_SEL1_WIDTH
#define	ADV_TIMER_EVENT_CFG_SEL1_MASK
#define	ADV_TIMER_EVENT_CFG_SEL1_RESET
#define	ADV_TIMER_EVENT_CFG_SEL2_BIT
#define	ADV_TIMER_EVENT_CFG_SEL2_WIDTH
#define	ADV_TIMER_EVENT_CFG_SEL2_MASK
#define	ADV_TIMER_EVENT_CFG_SEL2_RESET
#define	ADV_TIMER_EVENT_CFG_SEL3_BIT
#define	ADV_TIMER_EVENT_CFG_SEL3_WIDTH
#define	ADV_TIMER_EVENT_CFG_SEL3_MASK
#define	ADV_TIMER_EVENT_CFG_SEL3_RESET
#define	ADV_TIMER_EVENT_CFG_ENA_BIT
#define	ADV_TIMER_EVENT_CFG_ENA_WIDTH
#define	ADV_TIMER_EVENT_CFG_ENA_MASK
#define	ADV_TIMER_EVENT_CFG_ENA_RESET
#define	ADV_TIMER_CG_ENA_BIT
#define	ADV_TIMER_CG_ENA_WIDTH
#define	ADV_TIMER_CG_ENA_MASK
#define	ADV_TIMER_CG_ENA_RESET
#define	ADV_TIMER_CH_MUX_CH_SEL_0_BIT
#define	ADV_TIMER_CH_MUX_CH_SEL_0_WIDTH
#define	ADV_TIMER_CH_MUX_CH_SEL_0_MASK
#define	ADV_TIMER_CH_MUX_CH_SEL_0_RESET
#define	ADV_TIMER_CH_MUX_CH_SEL_1_BIT
#define	ADV_TIMER_CH_MUX_CH_SEL_1_WIDTH
#define	ADV_TIMER_CH_MUX_CH_SEL_1_MASK
#define	ADV_TIMER_CH_MUX_CH_SEL_1_RESET
#define	ADV_TIMER_CH_MUX_CH_SEL_2_BIT
#define	ADV_TIMER_CH_MUX_CH_SEL_2_WIDTH
#define	ADV_TIMER_CH_MUX_CH_SEL_2_MASK
#define	ADV_TIMER_CH_MUX_CH_SEL_2_RESET
#define	ADV_TIMER_CH_MUX_CH_SEL_3_BIT
#define	ADV_TIMER_CH_MUX_CH_SEL_3_WIDTH
#define	ADV_TIMER_CH_MUX_CH_SEL_3_MASK
#define	ADV_TIMER_CH_MUX_CH_SEL_3_RESET
#define	ADV_TIMER_CH_MUX_CH_SEL_4_BIT
#define	ADV_TIMER_CH_MUX_CH_SEL_4_WIDTH
#define	ADV_TIMER_CH_MUX_CH_SEL_4_MASK
#define	ADV_TIMER_CH_MUX_CH_SEL_4_RESET
#define	ADV_TIMER_CH_MUX_CH_SEL_5_BIT
#define	ADV_TIMER_CH_MUX_CH_SEL_5_WIDTH
#define	ADV_TIMER_CH_MUX_CH_SEL_5_MASK
#define	ADV_TIMER_CH_MUX_CH_SEL_5_RESET
#define	ADV_TIMER_CH_MUX_CH_SEL_6_BIT
#define	ADV_TIMER_CH_MUX_CH_SEL_6_WIDTH
#define	ADV_TIMER_CH_MUX_CH_SEL_6_MASK
#define	ADV_TIMER_CH_MUX_CH_SEL_6_RESET
#define	ADV_TIMER_CH_MUX_CH_SEL_7_BIT
#define	ADV_TIMER_CH_MUX_CH_SEL_7_WIDTH
#define	ADV_TIMER_CH_MUX_CH_SEL_7_MASK
#define	ADV_TIMER_CH_MUX_CH_SEL_7_RESET

Macro Definition Documentation

#define ADV_TIMER_CG_ENA_BIT

#define ADV_TIMER_CG_ENA_MASK

#define ADV_TIMER_CG_ENA_RESET

#define ADV_TIMER_CG_ENA_WIDTH

#define ADV_TIMER_CH_MUX_CH_SEL_0_BIT

#define ADV_TIMER_CH_MUX_CH_SEL_0_MASK

#define ADV_TIMER_CH_MUX_CH_SEL_0_RESET

#define ADV_TIMER_CH_MUX_CH_SEL_0_WIDTH

#define ADV_TIMER_CH_MUX_CH_SEL_1_BIT

#define ADV_TIMER_CH_MUX_CH_SEL_1_MASK

#define ADV_TIMER_CH_MUX_CH_SEL_1_RESET

#define ADV_TIMER_CH_MUX_CH_SEL_1_WIDTH

#define ADV_TIMER_CH_MUX_CH_SEL_2_BIT

#define ADV_TIMER_CH_MUX_CH_SEL_2_MASK

#define ADV_TIMER_CH_MUX_CH_SEL_2_RESET

#define ADV_TIMER_CH_MUX_CH_SEL_2_WIDTH

#define ADV_TIMER_CH_MUX_CH_SEL_3_BIT

#define ADV_TIMER_CH_MUX_CH_SEL_3_MASK

#define ADV_TIMER_CH_MUX_CH_SEL_3_RESET

#define ADV_TIMER_CH_MUX_CH_SEL_3_WIDTH

#define ADV_TIMER_CH_MUX_CH_SEL_4_BIT

#define ADV_TIMER_CH_MUX_CH_SEL_4_MASK

#define ADV_TIMER_CH_MUX_CH_SEL_4_RESET

#define ADV_TIMER_CH_MUX_CH_SEL_4_WIDTH

#define ADV_TIMER_CH_MUX_CH_SEL_5_BIT

#define ADV_TIMER_CH_MUX_CH_SEL_5_MASK

#define ADV_TIMER_CH_MUX_CH_SEL_5_RESET

#define ADV_TIMER_CH_MUX_CH_SEL_5_WIDTH

#define ADV_TIMER_CH_MUX_CH_SEL_6_BIT

#define ADV_TIMER_CH_MUX_CH_SEL_6_MASK

#define ADV_TIMER_CH_MUX_CH_SEL_6_RESET

#define ADV_TIMER_CH_MUX_CH_SEL_6_WIDTH

#define ADV_TIMER_CH_MUX_CH_SEL_7_BIT

#define ADV_TIMER_CH_MUX_CH_SEL_7_MASK

#define ADV_TIMER_CH_MUX_CH_SEL_7_RESET

#define ADV_TIMER_CH_MUX_CH_SEL_7_WIDTH

#define ADV_TIMER_EVENT_CFG_ENA_BIT

#define ADV_TIMER_EVENT_CFG_ENA_MASK

#define ADV_TIMER_EVENT_CFG_ENA_RESET

#define ADV_TIMER_EVENT_CFG_ENA_WIDTH

#define ADV_TIMER_EVENT_CFG_SEL0_BIT

#define ADV_TIMER_EVENT_CFG_SEL0_MASK

#define ADV_TIMER_EVENT_CFG_SEL0_RESET

#define ADV_TIMER_EVENT_CFG_SEL0_WIDTH

#define ADV_TIMER_EVENT_CFG_SEL1_BIT

#define ADV_TIMER_EVENT_CFG_SEL1_MASK

#define ADV_TIMER_EVENT_CFG_SEL1_RESET

#define ADV_TIMER_EVENT_CFG_SEL1_WIDTH

#define ADV_TIMER_EVENT_CFG_SEL2_BIT

#define ADV_TIMER_EVENT_CFG_SEL2_MASK

#define ADV_TIMER_EVENT_CFG_SEL2_RESET

#define ADV_TIMER_EVENT_CFG_SEL2_WIDTH

#define ADV_TIMER_EVENT_CFG_SEL3_BIT

#define ADV_TIMER_EVENT_CFG_SEL3_MASK

#define ADV_TIMER_EVENT_CFG_SEL3_RESET

#define ADV_TIMER_EVENT_CFG_SEL3_WIDTH

#define ADV_TIMER_T0_CMD_ARM_BIT

#define ADV_TIMER_T0_CMD_ARM_MASK

#define ADV_TIMER_T0_CMD_ARM_RESET

#define ADV_TIMER_T0_CMD_ARM_WIDTH

#define ADV_TIMER_T0_CMD_RESET_BIT

#define ADV_TIMER_T0_CMD_RESET_MASK

#define ADV_TIMER_T0_CMD_RESET_RESET

#define ADV_TIMER_T0_CMD_RESET_WIDTH

#define ADV_TIMER_T0_CMD_RFU_BIT

#define ADV_TIMER_T0_CMD_RFU_MASK

#define ADV_TIMER_T0_CMD_RFU_RESET

#define ADV_TIMER_T0_CMD_RFU_WIDTH

#define ADV_TIMER_T0_CMD_START_BIT

#define ADV_TIMER_T0_CMD_START_MASK

#define ADV_TIMER_T0_CMD_START_RESET

#define ADV_TIMER_T0_CMD_START_WIDTH

#define ADV_TIMER_T0_CMD_STOP_BIT

#define ADV_TIMER_T0_CMD_STOP_MASK

#define ADV_TIMER_T0_CMD_STOP_RESET

#define ADV_TIMER_T0_CMD_STOP_WIDTH

#define ADV_TIMER_T0_CMD_UPDATE_BIT

#define ADV_TIMER_T0_CMD_UPDATE_MASK

#define ADV_TIMER_T0_CMD_UPDATE_RESET

#define ADV_TIMER_T0_CMD_UPDATE_WIDTH

#define ADV_TIMER_T0_CONFIG_CLKSEL_BIT

#define ADV_TIMER_T0_CONFIG_CLKSEL_MASK

#define ADV_TIMER_T0_CONFIG_CLKSEL_RESET

#define ADV_TIMER_T0_CONFIG_CLKSEL_WIDTH

#define ADV_TIMER_T0_CONFIG_INSEL_BIT

#define ADV_TIMER_T0_CONFIG_INSEL_MASK

#define ADV_TIMER_T0_CONFIG_INSEL_RESET

#define ADV_TIMER_T0_CONFIG_INSEL_WIDTH

#define ADV_TIMER_T0_CONFIG_MODE_BIT

#define ADV_TIMER_T0_CONFIG_MODE_MASK

#define ADV_TIMER_T0_CONFIG_MODE_RESET

#define ADV_TIMER_T0_CONFIG_MODE_WIDTH

#define ADV_TIMER_T0_CONFIG_PRESC_BIT

#define ADV_TIMER_T0_CONFIG_PRESC_MASK

#define ADV_TIMER_T0_CONFIG_PRESC_RESET

#define ADV_TIMER_T0_CONFIG_PRESC_WIDTH

#define ADV_TIMER_T0_CONFIG_UPDOWNSEL_BIT

#define ADV_TIMER_T0_CONFIG_UPDOWNSEL_MASK

#define ADV_TIMER_T0_CONFIG_UPDOWNSEL_RESET

#define ADV_TIMER_T0_CONFIG_UPDOWNSEL_WIDTH

#define ADV_TIMER_T0_COUNTER_COUNTER_BIT

#define ADV_TIMER_T0_COUNTER_COUNTER_MASK

#define ADV_TIMER_T0_COUNTER_COUNTER_RESET

#define ADV_TIMER_T0_COUNTER_COUNTER_WIDTH

#define ADV_TIMER_T0_TH_CHANNEL0_MODE_BIT

#define ADV_TIMER_T0_TH_CHANNEL0_MODE_MASK

#define ADV_TIMER_T0_TH_CHANNEL0_MODE_RESET

#define ADV_TIMER_T0_TH_CHANNEL0_MODE_WIDTH

#define ADV_TIMER_T0_TH_CHANNEL0_TH_BIT

#define ADV_TIMER_T0_TH_CHANNEL0_TH_MASK

#define ADV_TIMER_T0_TH_CHANNEL0_TH_RESET

#define ADV_TIMER_T0_TH_CHANNEL0_TH_WIDTH

#define ADV_TIMER_T0_TH_CHANNEL1_MODE_BIT

#define ADV_TIMER_T0_TH_CHANNEL1_MODE_MASK

#define ADV_TIMER_T0_TH_CHANNEL1_MODE_RESET

#define ADV_TIMER_T0_TH_CHANNEL1_MODE_WIDTH

#define ADV_TIMER_T0_TH_CHANNEL1_TH_BIT

#define ADV_TIMER_T0_TH_CHANNEL1_TH_MASK

#define ADV_TIMER_T0_TH_CHANNEL1_TH_RESET

#define ADV_TIMER_T0_TH_CHANNEL1_TH_WIDTH

#define ADV_TIMER_T0_TH_CHANNEL2_MODE_BIT

#define ADV_TIMER_T0_TH_CHANNEL2_MODE_MASK

#define ADV_TIMER_T0_TH_CHANNEL2_MODE_RESET

#define ADV_TIMER_T0_TH_CHANNEL2_MODE_WIDTH

#define ADV_TIMER_T0_TH_CHANNEL2_TH_BIT

#define ADV_TIMER_T0_TH_CHANNEL2_TH_MASK

#define ADV_TIMER_T0_TH_CHANNEL2_TH_RESET

#define ADV_TIMER_T0_TH_CHANNEL2_TH_WIDTH

#define ADV_TIMER_T0_TH_CHANNEL3_MODE_BIT

#define ADV_TIMER_T0_TH_CHANNEL3_MODE_MASK

#define ADV_TIMER_T0_TH_CHANNEL3_MODE_RESET

#define ADV_TIMER_T0_TH_CHANNEL3_MODE_WIDTH

#define ADV_TIMER_T0_TH_CHANNEL3_TH_BIT

#define ADV_TIMER_T0_TH_CHANNEL3_TH_MASK

#define ADV_TIMER_T0_TH_CHANNEL3_TH_RESET

#define ADV_TIMER_T0_TH_CHANNEL3_TH_WIDTH

#define ADV_TIMER_T0_THRESHOLD_TH_HI_BIT

#define ADV_TIMER_T0_THRESHOLD_TH_HI_MASK

#define ADV_TIMER_T0_THRESHOLD_TH_HI_RESET

#define ADV_TIMER_T0_THRESHOLD_TH_HI_WIDTH

#define ADV_TIMER_T0_THRESHOLD_TH_LO_BIT

#define ADV_TIMER_T0_THRESHOLD_TH_LO_MASK

#define ADV_TIMER_T0_THRESHOLD_TH_LO_RESET

#define ADV_TIMER_T0_THRESHOLD_TH_LO_WIDTH

#define ADV_TIMER_T1_CMD_ARM_BIT

#define ADV_TIMER_T1_CMD_ARM_MASK

#define ADV_TIMER_T1_CMD_ARM_RESET

#define ADV_TIMER_T1_CMD_ARM_WIDTH

#define ADV_TIMER_T1_CMD_RESET_BIT

#define ADV_TIMER_T1_CMD_RESET_MASK

#define ADV_TIMER_T1_CMD_RESET_RESET

#define ADV_TIMER_T1_CMD_RESET_WIDTH

#define ADV_TIMER_T1_CMD_START_BIT

#define ADV_TIMER_T1_CMD_START_MASK

#define ADV_TIMER_T1_CMD_START_RESET

#define ADV_TIMER_T1_CMD_START_WIDTH

#define ADV_TIMER_T1_CMD_STOP_BIT

#define ADV_TIMER_T1_CMD_STOP_MASK

#define ADV_TIMER_T1_CMD_STOP_RESET

#define ADV_TIMER_T1_CMD_STOP_WIDTH

#define ADV_TIMER_T1_CMD_UPDATE_BIT

#define ADV_TIMER_T1_CMD_UPDATE_MASK

#define ADV_TIMER_T1_CMD_UPDATE_RESET

#define ADV_TIMER_T1_CMD_UPDATE_WIDTH

#define ADV_TIMER_T1_CONFIG_CLKSEL_BIT

#define ADV_TIMER_T1_CONFIG_CLKSEL_MASK

Referenced by hal_pwm_config_clksel_set().

#define ADV_TIMER_T1_CONFIG_CLKSEL_RESET

#define ADV_TIMER_T1_CONFIG_CLKSEL_WIDTH

#define ADV_TIMER_T1_CONFIG_INSEL_BIT

#define ADV_TIMER_T1_CONFIG_INSEL_MASK

Referenced by hal_pwm_config_insel_set().

#define ADV_TIMER_T1_CONFIG_INSEL_RESET

#define ADV_TIMER_T1_CONFIG_INSEL_WIDTH

#define ADV_TIMER_T1_CONFIG_MODE_BIT

#define ADV_TIMER_T1_CONFIG_MODE_MASK

Referenced by hal_pwm_config_mode_set().

#define ADV_TIMER_T1_CONFIG_MODE_RESET

#define ADV_TIMER_T1_CONFIG_MODE_WIDTH

#define ADV_TIMER_T1_CONFIG_PRESC_BIT

#define ADV_TIMER_T1_CONFIG_PRESC_MASK

Referenced by hal_pwm_config_presc_set().

#define ADV_TIMER_T1_CONFIG_PRESC_RESET

#define ADV_TIMER_T1_CONFIG_PRESC_WIDTH

#define ADV_TIMER_T1_CONFIG_UPDOWNSEL_BIT

#define ADV_TIMER_T1_CONFIG_UPDOWNSEL_MASK

Referenced by hal_pwm_config_updown_set().

#define ADV_TIMER_T1_CONFIG_UPDOWNSEL_RESET

#define ADV_TIMER_T1_CONFIG_UPDOWNSEL_WIDTH

#define ADV_TIMER_T1_COUNTER_COUNTER_BIT

#define ADV_TIMER_T1_COUNTER_COUNTER_MASK

#define ADV_TIMER_T1_COUNTER_COUNTER_RESET

#define ADV_TIMER_T1_COUNTER_COUNTER_WIDTH

#define ADV_TIMER_T1_TH_CHANNEL0_MODE_BIT

#define ADV_TIMER_T1_TH_CHANNEL0_MODE_MASK

#define ADV_TIMER_T1_TH_CHANNEL0_MODE_RESET

#define ADV_TIMER_T1_TH_CHANNEL0_MODE_WIDTH

#define ADV_TIMER_T1_TH_CHANNEL0_TH_BIT

#define ADV_TIMER_T1_TH_CHANNEL0_TH_MASK

#define ADV_TIMER_T1_TH_CHANNEL0_TH_RESET

#define ADV_TIMER_T1_TH_CHANNEL0_TH_WIDTH

#define ADV_TIMER_T1_TH_CHANNEL1_MODE_BIT

#define ADV_TIMER_T1_TH_CHANNEL1_MODE_MASK

#define ADV_TIMER_T1_TH_CHANNEL1_MODE_RESET

#define ADV_TIMER_T1_TH_CHANNEL1_MODE_WIDTH

#define ADV_TIMER_T1_TH_CHANNEL1_TH_BIT

#define ADV_TIMER_T1_TH_CHANNEL1_TH_MASK

#define ADV_TIMER_T1_TH_CHANNEL1_TH_RESET

#define ADV_TIMER_T1_TH_CHANNEL1_TH_WIDTH

#define ADV_TIMER_T1_TH_CHANNEL2_MODE_BIT

#define ADV_TIMER_T1_TH_CHANNEL2_MODE_MASK

#define ADV_TIMER_T1_TH_CHANNEL2_MODE_RESET

#define ADV_TIMER_T1_TH_CHANNEL2_MODE_WIDTH

#define ADV_TIMER_T1_TH_CHANNEL2_TH_BIT

#define ADV_TIMER_T1_TH_CHANNEL2_TH_MASK

#define ADV_TIMER_T1_TH_CHANNEL2_TH_RESET

#define ADV_TIMER_T1_TH_CHANNEL2_TH_WIDTH

#define ADV_TIMER_T1_TH_CHANNEL3_MODE_BIT

#define ADV_TIMER_T1_TH_CHANNEL3_MODE_MASK

#define ADV_TIMER_T1_TH_CHANNEL3_MODE_RESET

#define ADV_TIMER_T1_TH_CHANNEL3_MODE_WIDTH

#define ADV_TIMER_T1_TH_CHANNEL3_TH_BIT

#define ADV_TIMER_T1_TH_CHANNEL3_TH_MASK

#define ADV_TIMER_T1_TH_CHANNEL3_TH_RESET

#define ADV_TIMER_T1_TH_CHANNEL3_TH_WIDTH

#define ADV_TIMER_T1_THRESHOLD_TH_HI_BIT

#define ADV_TIMER_T1_THRESHOLD_TH_HI_MASK

#define ADV_TIMER_T1_THRESHOLD_TH_HI_RESET

#define ADV_TIMER_T1_THRESHOLD_TH_HI_WIDTH

#define ADV_TIMER_T1_THRESHOLD_TH_LO_BIT

#define ADV_TIMER_T1_THRESHOLD_TH_LO_MASK

#define ADV_TIMER_T1_THRESHOLD_TH_LO_RESET

#define ADV_TIMER_T1_THRESHOLD_TH_LO_WIDTH

#define ADV_TIMER_T2_CMD_ARM_BIT

#define ADV_TIMER_T2_CMD_ARM_MASK

#define ADV_TIMER_T2_CMD_ARM_RESET

#define ADV_TIMER_T2_CMD_ARM_WIDTH

#define ADV_TIMER_T2_CMD_RESET_BIT

#define ADV_TIMER_T2_CMD_RESET_MASK

#define ADV_TIMER_T2_CMD_RESET_RESET

#define ADV_TIMER_T2_CMD_RESET_WIDTH

#define ADV_TIMER_T2_CMD_START_BIT

#define ADV_TIMER_T2_CMD_START_MASK

#define ADV_TIMER_T2_CMD_START_RESET

#define ADV_TIMER_T2_CMD_START_WIDTH

#define ADV_TIMER_T2_CMD_STOP_BIT

#define ADV_TIMER_T2_CMD_STOP_MASK

#define ADV_TIMER_T2_CMD_STOP_RESET

#define ADV_TIMER_T2_CMD_STOP_WIDTH

#define ADV_TIMER_T2_CMD_UPDATE_BIT

#define ADV_TIMER_T2_CMD_UPDATE_MASK

#define ADV_TIMER_T2_CMD_UPDATE_RESET

#define ADV_TIMER_T2_CMD_UPDATE_WIDTH

#define ADV_TIMER_T2_CONFIG_CLKSEL_BIT

#define ADV_TIMER_T2_CONFIG_CLKSEL_MASK

#define ADV_TIMER_T2_CONFIG_CLKSEL_RESET

#define ADV_TIMER_T2_CONFIG_CLKSEL_WIDTH

#define ADV_TIMER_T2_CONFIG_INSEL_BIT

#define ADV_TIMER_T2_CONFIG_INSEL_MASK

#define ADV_TIMER_T2_CONFIG_INSEL_RESET

#define ADV_TIMER_T2_CONFIG_INSEL_WIDTH

#define ADV_TIMER_T2_CONFIG_MODE_BIT

#define ADV_TIMER_T2_CONFIG_MODE_MASK

#define ADV_TIMER_T2_CONFIG_MODE_RESET

#define ADV_TIMER_T2_CONFIG_MODE_WIDTH

#define ADV_TIMER_T2_CONFIG_PRESC_BIT

#define ADV_TIMER_T2_CONFIG_PRESC_MASK

#define ADV_TIMER_T2_CONFIG_PRESC_RESET

#define ADV_TIMER_T2_CONFIG_PRESC_WIDTH

#define ADV_TIMER_T2_CONFIG_UPDOWNSEL_BIT

#define ADV_TIMER_T2_CONFIG_UPDOWNSEL_MASK

#define ADV_TIMER_T2_CONFIG_UPDOWNSEL_RESET

#define ADV_TIMER_T2_CONFIG_UPDOWNSEL_WIDTH

#define ADV_TIMER_T2_COUNTER_COUNTER_BIT

#define ADV_TIMER_T2_COUNTER_COUNTER_MASK

#define ADV_TIMER_T2_COUNTER_COUNTER_RESET

#define ADV_TIMER_T2_COUNTER_COUNTER_WIDTH

#define ADV_TIMER_T2_TH_CHANNEL0_MODE_BIT

#define ADV_TIMER_T2_TH_CHANNEL0_MODE_MASK

#define ADV_TIMER_T2_TH_CHANNEL0_MODE_RESET

#define ADV_TIMER_T2_TH_CHANNEL0_MODE_WIDTH

#define ADV_TIMER_T2_TH_CHANNEL0_TH_BIT

#define ADV_TIMER_T2_TH_CHANNEL0_TH_MASK

#define ADV_TIMER_T2_TH_CHANNEL0_TH_RESET

#define ADV_TIMER_T2_TH_CHANNEL0_TH_WIDTH

#define ADV_TIMER_T2_TH_CHANNEL1_MODE_BIT

#define ADV_TIMER_T2_TH_CHANNEL1_MODE_MASK

#define ADV_TIMER_T2_TH_CHANNEL1_MODE_RESET

#define ADV_TIMER_T2_TH_CHANNEL1_MODE_WIDTH

#define ADV_TIMER_T2_TH_CHANNEL1_TH_BIT

#define ADV_TIMER_T2_TH_CHANNEL1_TH_MASK

#define ADV_TIMER_T2_TH_CHANNEL1_TH_RESET

#define ADV_TIMER_T2_TH_CHANNEL1_TH_WIDTH

#define ADV_TIMER_T2_TH_CHANNEL2_MODE_BIT

#define ADV_TIMER_T2_TH_CHANNEL2_MODE_MASK

#define ADV_TIMER_T2_TH_CHANNEL2_MODE_RESET

#define ADV_TIMER_T2_TH_CHANNEL2_MODE_WIDTH

#define ADV_TIMER_T2_TH_CHANNEL2_TH_BIT

#define ADV_TIMER_T2_TH_CHANNEL2_TH_MASK

#define ADV_TIMER_T2_TH_CHANNEL2_TH_RESET

#define ADV_TIMER_T2_TH_CHANNEL2_TH_WIDTH

#define ADV_TIMER_T2_TH_CHANNEL3_MODE_BIT

#define ADV_TIMER_T2_TH_CHANNEL3_MODE_MASK

#define ADV_TIMER_T2_TH_CHANNEL3_MODE_RESET

#define ADV_TIMER_T2_TH_CHANNEL3_MODE_WIDTH

#define ADV_TIMER_T2_TH_CHANNEL3_TH_BIT

#define ADV_TIMER_T2_TH_CHANNEL3_TH_MASK

#define ADV_TIMER_T2_TH_CHANNEL3_TH_RESET

#define ADV_TIMER_T2_TH_CHANNEL3_TH_WIDTH

#define ADV_TIMER_T2_THRESHOLD_TH_HI_BIT

#define ADV_TIMER_T2_THRESHOLD_TH_HI_MASK

#define ADV_TIMER_T2_THRESHOLD_TH_HI_RESET

#define ADV_TIMER_T2_THRESHOLD_TH_HI_WIDTH

#define ADV_TIMER_T2_THRESHOLD_TH_LO_BIT

#define ADV_TIMER_T2_THRESHOLD_TH_LO_MASK

#define ADV_TIMER_T2_THRESHOLD_TH_LO_RESET

#define ADV_TIMER_T2_THRESHOLD_TH_LO_WIDTH

#define ADV_TIMER_T3_CMD_ARM_BIT

#define ADV_TIMER_T3_CMD_ARM_MASK

#define ADV_TIMER_T3_CMD_ARM_RESET

#define ADV_TIMER_T3_CMD_ARM_WIDTH

#define ADV_TIMER_T3_CMD_RESET_BIT

#define ADV_TIMER_T3_CMD_RESET_MASK

#define ADV_TIMER_T3_CMD_RESET_RESET

#define ADV_TIMER_T3_CMD_RESET_WIDTH

#define ADV_TIMER_T3_CMD_START_BIT

#define ADV_TIMER_T3_CMD_START_MASK

#define ADV_TIMER_T3_CMD_START_RESET

#define ADV_TIMER_T3_CMD_START_WIDTH

#define ADV_TIMER_T3_CMD_STOP_BIT

#define ADV_TIMER_T3_CMD_STOP_MASK

#define ADV_TIMER_T3_CMD_STOP_RESET

#define ADV_TIMER_T3_CMD_STOP_WIDTH

#define ADV_TIMER_T3_CMD_UPDATE_BIT

#define ADV_TIMER_T3_CMD_UPDATE_MASK

#define ADV_TIMER_T3_CMD_UPDATE_RESET

#define ADV_TIMER_T3_CMD_UPDATE_WIDTH

#define ADV_TIMER_T3_CONFIG_CLKSEL_BIT

#define ADV_TIMER_T3_CONFIG_CLKSEL_MASK

#define ADV_TIMER_T3_CONFIG_CLKSEL_RESET

#define ADV_TIMER_T3_CONFIG_CLKSEL_WIDTH

#define ADV_TIMER_T3_CONFIG_INSEL_BIT

#define ADV_TIMER_T3_CONFIG_INSEL_MASK

#define ADV_TIMER_T3_CONFIG_INSEL_RESET

#define ADV_TIMER_T3_CONFIG_INSEL_WIDTH

#define ADV_TIMER_T3_CONFIG_MODE_BIT

#define ADV_TIMER_T3_CONFIG_MODE_MASK

#define ADV_TIMER_T3_CONFIG_MODE_RESET

#define ADV_TIMER_T3_CONFIG_MODE_WIDTH

#define ADV_TIMER_T3_CONFIG_PRESC_BIT

#define ADV_TIMER_T3_CONFIG_PRESC_MASK

#define ADV_TIMER_T3_CONFIG_PRESC_RESET

#define ADV_TIMER_T3_CONFIG_PRESC_WIDTH

#define ADV_TIMER_T3_CONFIG_UPDOWNSEL_BIT

#define ADV_TIMER_T3_CONFIG_UPDOWNSEL_MASK

#define ADV_TIMER_T3_CONFIG_UPDOWNSEL_RESET

#define ADV_TIMER_T3_CONFIG_UPDOWNSEL_WIDTH

#define ADV_TIMER_T3_COUNTER_COUNTER_BIT

#define ADV_TIMER_T3_COUNTER_COUNTER_MASK

#define ADV_TIMER_T3_COUNTER_COUNTER_RESET

#define ADV_TIMER_T3_COUNTER_COUNTER_WIDTH

#define ADV_TIMER_T3_TH_CHANNEL0_MODE_BIT

#define ADV_TIMER_T3_TH_CHANNEL0_MODE_MASK

#define ADV_TIMER_T3_TH_CHANNEL0_MODE_RESET

#define ADV_TIMER_T3_TH_CHANNEL0_MODE_WIDTH

#define ADV_TIMER_T3_TH_CHANNEL0_TH_BIT

#define ADV_TIMER_T3_TH_CHANNEL0_TH_MASK

#define ADV_TIMER_T3_TH_CHANNEL0_TH_RESET

#define ADV_TIMER_T3_TH_CHANNEL0_TH_WIDTH

#define ADV_TIMER_T3_TH_CHANNEL1_MODE_BIT

#define ADV_TIMER_T3_TH_CHANNEL1_MODE_MASK

#define ADV_TIMER_T3_TH_CHANNEL1_MODE_RESET

#define ADV_TIMER_T3_TH_CHANNEL1_MODE_WIDTH

#define ADV_TIMER_T3_TH_CHANNEL1_TH_BIT

#define ADV_TIMER_T3_TH_CHANNEL1_TH_MASK

#define ADV_TIMER_T3_TH_CHANNEL1_TH_RESET

#define ADV_TIMER_T3_TH_CHANNEL1_TH_WIDTH

#define ADV_TIMER_T3_TH_CHANNEL2_MODE_BIT

#define ADV_TIMER_T3_TH_CHANNEL2_MODE_MASK

#define ADV_TIMER_T3_TH_CHANNEL2_MODE_RESET

#define ADV_TIMER_T3_TH_CHANNEL2_MODE_WIDTH

#define ADV_TIMER_T3_TH_CHANNEL2_TH_BIT

#define ADV_TIMER_T3_TH_CHANNEL2_TH_MASK

#define ADV_TIMER_T3_TH_CHANNEL2_TH_RESET

#define ADV_TIMER_T3_TH_CHANNEL2_TH_WIDTH

#define ADV_TIMER_T3_TH_CHANNEL3_MODE_BIT

#define ADV_TIMER_T3_TH_CHANNEL3_MODE_MASK

#define ADV_TIMER_T3_TH_CHANNEL3_MODE_RESET

#define ADV_TIMER_T3_TH_CHANNEL3_MODE_WIDTH

#define ADV_TIMER_T3_TH_CHANNEL3_TH_BIT

#define ADV_TIMER_T3_TH_CHANNEL3_TH_MASK

#define ADV_TIMER_T3_TH_CHANNEL3_TH_RESET

#define ADV_TIMER_T3_TH_CHANNEL3_TH_WIDTH

#define ADV_TIMER_T3_THRESHOLD_TH_HI_BIT

#define ADV_TIMER_T3_THRESHOLD_TH_HI_MASK

#define ADV_TIMER_T3_THRESHOLD_TH_HI_RESET

#define ADV_TIMER_T3_THRESHOLD_TH_HI_WIDTH

#define ADV_TIMER_T3_THRESHOLD_TH_LO_BIT

#define ADV_TIMER_T3_THRESHOLD_TH_LO_MASK

#define ADV_TIMER_T3_THRESHOLD_TH_LO_RESET

#define ADV_TIMER_T3_THRESHOLD_TH_LO_WIDTH