power_manager_regfields.h File Reference

Macros
#define	POWER_MANAGER_DLCPD_MSR_PICL_BUSY_BIT
#define	POWER_MANAGER_DLCPD_MSR_PICL_BUSY_WIDTH
#define	POWER_MANAGER_DLCPD_MSR_PICL_BUSY_MASK
#define	POWER_MANAGER_DLCPD_MSR_PICL_BUSY_RESET
#define	POWER_MANAGER_DLCPD_MSR_SCU_BUSY_BIT
#define	POWER_MANAGER_DLCPD_MSR_SCU_BUSY_WIDTH
#define	POWER_MANAGER_DLCPD_MSR_SCU_BUSY_MASK
#define	POWER_MANAGER_DLCPD_MSR_SCU_BUSY_RESET
#define	POWER_MANAGER_DLCPD_MPACR_PAADDR_BIT
#define	POWER_MANAGER_DLCPD_MPACR_PAADDR_WIDTH
#define	POWER_MANAGER_DLCPD_MPACR_PAADDR_MASK
#define	POWER_MANAGER_DLCPD_MPACR_PAADDR_RESET
#define	POWER_MANAGER_DLCPD_MPACR_PADIR_BIT
#define	POWER_MANAGER_DLCPD_MPACR_PADIR_WIDTH
#define	POWER_MANAGER_DLCPD_MPACR_PADIR_MASK
#define	POWER_MANAGER_DLCPD_MPACR_PADIR_RESET
#define	POWER_MANAGER_DLCPD_MPACR_PASTART_BIT
#define	POWER_MANAGER_DLCPD_MPACR_PASTART_WIDTH
#define	POWER_MANAGER_DLCPD_MPACR_PASTART_MASK
#define	POWER_MANAGER_DLCPD_MPACR_PASTART_RESET
#define	POWER_MANAGER_DLCPD_MPADR_PRWDATA_BIT
#define	POWER_MANAGER_DLCPD_MPADR_PRWDATA_WIDTH
#define	POWER_MANAGER_DLCPD_MPADR_PRWDATA_MASK
#define	POWER_MANAGER_DLCPD_MPADR_PRWDATA_RESET
#define	POWER_MANAGER_DLCPD_IMR_ICU_OK_M_BIT
#define	POWER_MANAGER_DLCPD_IMR_ICU_OK_M_WIDTH
#define	POWER_MANAGER_DLCPD_IMR_ICU_OK_M_MASK
#define	POWER_MANAGER_DLCPD_IMR_ICU_OK_M_RESET
#define	POWER_MANAGER_DLCPD_IMR_ICU_DLY_M_BIT
#define	POWER_MANAGER_DLCPD_IMR_ICU_DLY_M_WIDTH
#define	POWER_MANAGER_DLCPD_IMR_ICU_DLY_M_MASK
#define	POWER_MANAGER_DLCPD_IMR_ICU_DLY_M_RESET
#define	POWER_MANAGER_DLCPD_IMR_ICU_DEN_M_BIT
#define	POWER_MANAGER_DLCPD_IMR_ICU_DEN_M_WIDTH
#define	POWER_MANAGER_DLCPD_IMR_ICU_DEN_M_MASK
#define	POWER_MANAGER_DLCPD_IMR_ICU_DEN_M_RESET
#define	POWER_MANAGER_DLCPD_IMR_ICU_UPD_M_BIT
#define	POWER_MANAGER_DLCPD_IMR_ICU_UPD_M_WIDTH
#define	POWER_MANAGER_DLCPD_IMR_ICU_UPD_M_MASK
#define	POWER_MANAGER_DLCPD_IMR_ICU_UPD_M_RESET
#define	POWER_MANAGER_DLCPD_IMR_PICL_OK_M_BIT
#define	POWER_MANAGER_DLCPD_IMR_PICL_OK_M_WIDTH
#define	POWER_MANAGER_DLCPD_IMR_PICL_OK_M_MASK
#define	POWER_MANAGER_DLCPD_IMR_PICL_OK_M_RESET
#define	POWER_MANAGER_DLCPD_IMR_SCU_OK_M_BIT
#define	POWER_MANAGER_DLCPD_IMR_SCU_OK_M_WIDTH
#define	POWER_MANAGER_DLCPD_IMR_SCU_OK_M_MASK
#define	POWER_MANAGER_DLCPD_IMR_SCU_OK_M_RESET
#define	POWER_MANAGER_DLCPD_IMR_SCU_FL_M_BIT
#define	POWER_MANAGER_DLCPD_IMR_SCU_FL_M_WIDTH
#define	POWER_MANAGER_DLCPD_IMR_SCU_FL_M_MASK
#define	POWER_MANAGER_DLCPD_IMR_SCU_FL_M_RESET
#define	POWER_MANAGER_DLCPD_IFR_ICU_OK_F_BIT
#define	POWER_MANAGER_DLCPD_IFR_ICU_OK_F_WIDTH
#define	POWER_MANAGER_DLCPD_IFR_ICU_OK_F_MASK
#define	POWER_MANAGER_DLCPD_IFR_ICU_OK_F_RESET
#define	POWER_MANAGER_DLCPD_IFR_ICU_DLY_F_BIT
#define	POWER_MANAGER_DLCPD_IFR_ICU_DLY_F_WIDTH
#define	POWER_MANAGER_DLCPD_IFR_ICU_DLY_F_MASK
#define	POWER_MANAGER_DLCPD_IFR_ICU_DLY_F_RESET
#define	POWER_MANAGER_DLCPD_IFR_ICU_DEN_F_BIT
#define	POWER_MANAGER_DLCPD_IFR_ICU_DEN_F_WIDTH
#define	POWER_MANAGER_DLCPD_IFR_ICU_DEN_F_MASK
#define	POWER_MANAGER_DLCPD_IFR_ICU_DEN_F_RESET
#define	POWER_MANAGER_DLCPD_IFR_ICU_UPD_F_BIT
#define	POWER_MANAGER_DLCPD_IFR_ICU_UPD_F_WIDTH
#define	POWER_MANAGER_DLCPD_IFR_ICU_UPD_F_MASK
#define	POWER_MANAGER_DLCPD_IFR_ICU_UPD_F_RESET
#define	POWER_MANAGER_DLCPD_IFR_PICL_OK_F_BIT
#define	POWER_MANAGER_DLCPD_IFR_PICL_OK_F_WIDTH
#define	POWER_MANAGER_DLCPD_IFR_PICL_OK_F_MASK
#define	POWER_MANAGER_DLCPD_IFR_PICL_OK_F_RESET
#define	POWER_MANAGER_DLCPD_IFR_SCU_OK_F_BIT
#define	POWER_MANAGER_DLCPD_IFR_SCU_OK_F_WIDTH
#define	POWER_MANAGER_DLCPD_IFR_SCU_OK_F_MASK
#define	POWER_MANAGER_DLCPD_IFR_SCU_OK_F_RESET
#define	POWER_MANAGER_DLCPD_IFR_SCU_FL_F_BIT
#define	POWER_MANAGER_DLCPD_IFR_SCU_FL_F_WIDTH
#define	POWER_MANAGER_DLCPD_IFR_SCU_FL_F_MASK
#define	POWER_MANAGER_DLCPD_IFR_SCU_FL_F_RESET
#define	POWER_MANAGER_DLCPD_IOK_IFR_ICU_OK_FLAGS_BIT
#define	POWER_MANAGER_DLCPD_IOK_IFR_ICU_OK_FLAGS_WIDTH
#define	POWER_MANAGER_DLCPD_IOK_IFR_ICU_OK_FLAGS_MASK
#define	POWER_MANAGER_DLCPD_IOK_IFR_ICU_OK_FLAGS_RESET
#define	POWER_MANAGER_DLCPD_IDL_IFR_ICU_DLY_FLAGS_BIT
#define	POWER_MANAGER_DLCPD_IDL_IFR_ICU_DLY_FLAGS_WIDTH
#define	POWER_MANAGER_DLCPD_IDL_IFR_ICU_DLY_FLAGS_MASK
#define	POWER_MANAGER_DLCPD_IDL_IFR_ICU_DLY_FLAGS_RESET
#define	POWER_MANAGER_DLCPD_IDN_IFR_ICU_DEN_FLAGS_BIT
#define	POWER_MANAGER_DLCPD_IDN_IFR_ICU_DEN_FLAGS_WIDTH
#define	POWER_MANAGER_DLCPD_IDN_IFR_ICU_DEN_FLAGS_MASK
#define	POWER_MANAGER_DLCPD_IDN_IFR_ICU_DEN_FLAGS_RESET
#define	POWER_MANAGER_DLCPD_IUP_IFR_ICU_UPD_FLAGS_BIT
#define	POWER_MANAGER_DLCPD_IUP_IFR_ICU_UPD_FLAGS_WIDTH
#define	POWER_MANAGER_DLCPD_IUP_IFR_ICU_UPD_FLAGS_MASK
#define	POWER_MANAGER_DLCPD_IUP_IFR_ICU_UPD_FLAGS_RESET

Macro Definition Documentation

#define POWER_MANAGER_DLCPD_IDL_IFR_ICU_DLY_FLAGS_BIT

#define POWER_MANAGER_DLCPD_IDL_IFR_ICU_DLY_FLAGS_MASK

#define POWER_MANAGER_DLCPD_IDL_IFR_ICU_DLY_FLAGS_RESET

#define POWER_MANAGER_DLCPD_IDL_IFR_ICU_DLY_FLAGS_WIDTH

#define POWER_MANAGER_DLCPD_IDN_IFR_ICU_DEN_FLAGS_BIT

#define POWER_MANAGER_DLCPD_IDN_IFR_ICU_DEN_FLAGS_MASK

#define POWER_MANAGER_DLCPD_IDN_IFR_ICU_DEN_FLAGS_RESET

#define POWER_MANAGER_DLCPD_IDN_IFR_ICU_DEN_FLAGS_WIDTH

#define POWER_MANAGER_DLCPD_IFR_ICU_DEN_F_BIT

#define POWER_MANAGER_DLCPD_IFR_ICU_DEN_F_MASK

#define POWER_MANAGER_DLCPD_IFR_ICU_DEN_F_RESET

#define POWER_MANAGER_DLCPD_IFR_ICU_DEN_F_WIDTH

#define POWER_MANAGER_DLCPD_IFR_ICU_DLY_F_BIT

#define POWER_MANAGER_DLCPD_IFR_ICU_DLY_F_MASK

#define POWER_MANAGER_DLCPD_IFR_ICU_DLY_F_RESET

#define POWER_MANAGER_DLCPD_IFR_ICU_DLY_F_WIDTH

#define POWER_MANAGER_DLCPD_IFR_ICU_OK_F_BIT

#define POWER_MANAGER_DLCPD_IFR_ICU_OK_F_MASK

#define POWER_MANAGER_DLCPD_IFR_ICU_OK_F_RESET

#define POWER_MANAGER_DLCPD_IFR_ICU_OK_F_WIDTH

#define POWER_MANAGER_DLCPD_IFR_ICU_UPD_F_BIT

#define POWER_MANAGER_DLCPD_IFR_ICU_UPD_F_MASK

#define POWER_MANAGER_DLCPD_IFR_ICU_UPD_F_RESET

#define POWER_MANAGER_DLCPD_IFR_ICU_UPD_F_WIDTH

#define POWER_MANAGER_DLCPD_IFR_PICL_OK_F_BIT

#define POWER_MANAGER_DLCPD_IFR_PICL_OK_F_MASK

#define POWER_MANAGER_DLCPD_IFR_PICL_OK_F_RESET

#define POWER_MANAGER_DLCPD_IFR_PICL_OK_F_WIDTH

#define POWER_MANAGER_DLCPD_IFR_SCU_FL_F_BIT

#define POWER_MANAGER_DLCPD_IFR_SCU_FL_F_MASK

#define POWER_MANAGER_DLCPD_IFR_SCU_FL_F_RESET

#define POWER_MANAGER_DLCPD_IFR_SCU_FL_F_WIDTH

#define POWER_MANAGER_DLCPD_IFR_SCU_OK_F_BIT

#define POWER_MANAGER_DLCPD_IFR_SCU_OK_F_MASK

#define POWER_MANAGER_DLCPD_IFR_SCU_OK_F_RESET

#define POWER_MANAGER_DLCPD_IFR_SCU_OK_F_WIDTH

#define POWER_MANAGER_DLCPD_IMR_ICU_DEN_M_BIT

#define POWER_MANAGER_DLCPD_IMR_ICU_DEN_M_MASK

#define POWER_MANAGER_DLCPD_IMR_ICU_DEN_M_RESET

#define POWER_MANAGER_DLCPD_IMR_ICU_DEN_M_WIDTH

#define POWER_MANAGER_DLCPD_IMR_ICU_DLY_M_BIT

#define POWER_MANAGER_DLCPD_IMR_ICU_DLY_M_MASK

#define POWER_MANAGER_DLCPD_IMR_ICU_DLY_M_RESET

#define POWER_MANAGER_DLCPD_IMR_ICU_DLY_M_WIDTH

#define POWER_MANAGER_DLCPD_IMR_ICU_OK_M_BIT

#define POWER_MANAGER_DLCPD_IMR_ICU_OK_M_MASK

#define POWER_MANAGER_DLCPD_IMR_ICU_OK_M_RESET

#define POWER_MANAGER_DLCPD_IMR_ICU_OK_M_WIDTH

#define POWER_MANAGER_DLCPD_IMR_ICU_UPD_M_BIT

#define POWER_MANAGER_DLCPD_IMR_ICU_UPD_M_MASK

#define POWER_MANAGER_DLCPD_IMR_ICU_UPD_M_RESET

#define POWER_MANAGER_DLCPD_IMR_ICU_UPD_M_WIDTH

#define POWER_MANAGER_DLCPD_IMR_PICL_OK_M_BIT

#define POWER_MANAGER_DLCPD_IMR_PICL_OK_M_MASK

#define POWER_MANAGER_DLCPD_IMR_PICL_OK_M_RESET

#define POWER_MANAGER_DLCPD_IMR_PICL_OK_M_WIDTH

#define POWER_MANAGER_DLCPD_IMR_SCU_FL_M_BIT

#define POWER_MANAGER_DLCPD_IMR_SCU_FL_M_MASK

#define POWER_MANAGER_DLCPD_IMR_SCU_FL_M_RESET

#define POWER_MANAGER_DLCPD_IMR_SCU_FL_M_WIDTH

#define POWER_MANAGER_DLCPD_IMR_SCU_OK_M_BIT

#define POWER_MANAGER_DLCPD_IMR_SCU_OK_M_MASK

#define POWER_MANAGER_DLCPD_IMR_SCU_OK_M_RESET

#define POWER_MANAGER_DLCPD_IMR_SCU_OK_M_WIDTH

#define POWER_MANAGER_DLCPD_IOK_IFR_ICU_OK_FLAGS_BIT

#define POWER_MANAGER_DLCPD_IOK_IFR_ICU_OK_FLAGS_MASK

#define POWER_MANAGER_DLCPD_IOK_IFR_ICU_OK_FLAGS_RESET

#define POWER_MANAGER_DLCPD_IOK_IFR_ICU_OK_FLAGS_WIDTH

#define POWER_MANAGER_DLCPD_IUP_IFR_ICU_UPD_FLAGS_BIT

#define POWER_MANAGER_DLCPD_IUP_IFR_ICU_UPD_FLAGS_MASK

#define POWER_MANAGER_DLCPD_IUP_IFR_ICU_UPD_FLAGS_RESET

#define POWER_MANAGER_DLCPD_IUP_IFR_ICU_UPD_FLAGS_WIDTH

#define POWER_MANAGER_DLCPD_MPACR_PAADDR_BIT

#define POWER_MANAGER_DLCPD_MPACR_PAADDR_MASK

#define POWER_MANAGER_DLCPD_MPACR_PAADDR_RESET

#define POWER_MANAGER_DLCPD_MPACR_PAADDR_WIDTH

#define POWER_MANAGER_DLCPD_MPACR_PADIR_BIT

#define POWER_MANAGER_DLCPD_MPACR_PADIR_MASK

#define POWER_MANAGER_DLCPD_MPACR_PADIR_RESET

#define POWER_MANAGER_DLCPD_MPACR_PADIR_WIDTH

#define POWER_MANAGER_DLCPD_MPACR_PASTART_BIT

#define POWER_MANAGER_DLCPD_MPACR_PASTART_MASK

#define POWER_MANAGER_DLCPD_MPACR_PASTART_RESET

#define POWER_MANAGER_DLCPD_MPACR_PASTART_WIDTH

#define POWER_MANAGER_DLCPD_MPADR_PRWDATA_BIT

#define POWER_MANAGER_DLCPD_MPADR_PRWDATA_MASK

#define POWER_MANAGER_DLCPD_MPADR_PRWDATA_RESET

#define POWER_MANAGER_DLCPD_MPADR_PRWDATA_WIDTH

#define POWER_MANAGER_DLCPD_MSR_PICL_BUSY_BIT

#define POWER_MANAGER_DLCPD_MSR_PICL_BUSY_MASK

#define POWER_MANAGER_DLCPD_MSR_PICL_BUSY_RESET

#define POWER_MANAGER_DLCPD_MSR_PICL_BUSY_WIDTH

#define POWER_MANAGER_DLCPD_MSR_SCU_BUSY_BIT

#define POWER_MANAGER_DLCPD_MSR_SCU_BUSY_MASK

#define POWER_MANAGER_DLCPD_MSR_SCU_BUSY_RESET

#define POWER_MANAGER_DLCPD_MSR_SCU_BUSY_WIDTH