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FreeRTOS port on GAP8/RISC-V
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| #define I3C_BUS_AVAIL_TIMER_REG_OFFSET |
Referenced by i3c_bus_avail_timer_reg_get(), and i3c_bus_avail_timer_reg_set().
| #define I3C_BUS_FREE_TIMER_REG_OFFSET |
Referenced by i3c_bus_free_timer_reg_get(), and i3c_bus_free_timer_reg_set().
| #define I3C_CMD_TR_REQ_REG_1_OFFSET |
Referenced by i3c_cmd_tr_req_reg_1_get(), and i3c_cmd_tr_req_reg_1_set().
| #define I3C_CMD_TR_REQ_REG_2_OFFSET |
Referenced by i3c_cmd_tr_req_reg_2_get(), and i3c_cmd_tr_req_reg_2_set().
| #define I3C_DATA_RX_FIFO_REG_OFFSET |
Referenced by i3c_data_rx_fifo_reg_get(), and i3c_data_rx_fifo_reg_set().
| #define I3C_DATA_TX_FIFO_REG_OFFSET |
Referenced by i3c_data_tx_fifo_reg_get(), and i3c_data_tx_fifo_reg_set().
| #define I3C_DEVICE_ADDR_TABLE_REG0_OFFSET |
Referenced by i3c_device_addr_table_reg0_get(), and i3c_device_addr_table_reg0_set().
| #define I3C_DEVICE_ADDR_TABLE_REG10_OFFSET |
Referenced by i3c_device_addr_table_reg10_get(), and i3c_device_addr_table_reg10_set().
| #define I3C_DEVICE_ADDR_TABLE_REG11_OFFSET |
Referenced by i3c_device_addr_table_reg11_get(), and i3c_device_addr_table_reg11_set().
| #define I3C_DEVICE_ADDR_TABLE_REG1_OFFSET |
Referenced by i3c_device_addr_table_reg1_get(), and i3c_device_addr_table_reg1_set().
| #define I3C_DEVICE_ADDR_TABLE_REG2_OFFSET |
Referenced by i3c_device_addr_table_reg2_get(), and i3c_device_addr_table_reg2_set().
| #define I3C_DEVICE_ADDR_TABLE_REG3_OFFSET |
Referenced by i3c_device_addr_table_reg3_get(), and i3c_device_addr_table_reg3_set().
| #define I3C_DEVICE_ADDR_TABLE_REG4_OFFSET |
Referenced by i3c_device_addr_table_reg4_get(), and i3c_device_addr_table_reg4_set().
| #define I3C_DEVICE_ADDR_TABLE_REG5_OFFSET |
Referenced by i3c_device_addr_table_reg5_get(), and i3c_device_addr_table_reg5_set().
| #define I3C_DEVICE_ADDR_TABLE_REG6_OFFSET |
Referenced by i3c_device_addr_table_reg6_get(), and i3c_device_addr_table_reg6_set().
| #define I3C_DEVICE_ADDR_TABLE_REG7_OFFSET |
Referenced by i3c_device_addr_table_reg7_get(), and i3c_device_addr_table_reg7_set().
| #define I3C_DEVICE_ADDR_TABLE_REG8_OFFSET |
Referenced by i3c_device_addr_table_reg8_get(), and i3c_device_addr_table_reg8_set().
| #define I3C_DEVICE_ADDR_TABLE_REG9_OFFSET |
Referenced by i3c_device_addr_table_reg9_get(), and i3c_device_addr_table_reg9_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_0_OFFSET |
Referenced by i3c_device_char_table_reg0_0_get(), and i3c_device_char_table_reg0_0_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_10_OFFSET |
Referenced by i3c_device_char_table_reg0_10_get(), and i3c_device_char_table_reg0_10_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_11_OFFSET |
Referenced by i3c_device_char_table_reg0_11_get(), and i3c_device_char_table_reg0_11_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_1_OFFSET |
Referenced by i3c_device_char_table_reg0_1_get(), and i3c_device_char_table_reg0_1_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_2_OFFSET |
Referenced by i3c_device_char_table_reg0_2_get(), and i3c_device_char_table_reg0_2_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_3_OFFSET |
Referenced by i3c_device_char_table_reg0_3_get(), and i3c_device_char_table_reg0_3_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_4_OFFSET |
Referenced by i3c_device_char_table_reg0_4_get(), and i3c_device_char_table_reg0_4_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_5_OFFSET |
Referenced by i3c_device_char_table_reg0_5_get(), and i3c_device_char_table_reg0_5_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_6_OFFSET |
Referenced by i3c_device_char_table_reg0_6_get(), and i3c_device_char_table_reg0_6_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_7_OFFSET |
Referenced by i3c_device_char_table_reg0_7_get(), and i3c_device_char_table_reg0_7_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_8_OFFSET |
Referenced by i3c_device_char_table_reg0_8_get(), and i3c_device_char_table_reg0_8_set().
| #define I3C_DEVICE_CHAR_TABLE_REG0_9_OFFSET |
Referenced by i3c_device_char_table_reg0_9_get(), and i3c_device_char_table_reg0_9_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_0_OFFSET |
Referenced by i3c_device_char_table_reg1_0_get(), and i3c_device_char_table_reg1_0_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_10_OFFSET |
Referenced by i3c_device_char_table_reg1_10_get(), and i3c_device_char_table_reg1_10_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_11_OFFSET |
Referenced by i3c_device_char_table_reg1_11_get(), and i3c_device_char_table_reg1_11_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_1_OFFSET |
Referenced by i3c_device_char_table_reg1_1_get(), and i3c_device_char_table_reg1_1_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_2_OFFSET |
Referenced by i3c_device_char_table_reg1_2_get(), and i3c_device_char_table_reg1_2_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_3_OFFSET |
Referenced by i3c_device_char_table_reg1_3_get(), and i3c_device_char_table_reg1_3_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_4_OFFSET |
Referenced by i3c_device_char_table_reg1_4_get(), and i3c_device_char_table_reg1_4_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_5_OFFSET |
Referenced by i3c_device_char_table_reg1_5_get(), and i3c_device_char_table_reg1_5_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_6_OFFSET |
Referenced by i3c_device_char_table_reg1_6_get(), and i3c_device_char_table_reg1_6_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_7_OFFSET |
Referenced by i3c_device_char_table_reg1_7_get(), and i3c_device_char_table_reg1_7_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_8_OFFSET |
Referenced by i3c_device_char_table_reg1_8_get(), and i3c_device_char_table_reg1_8_set().
| #define I3C_DEVICE_CHAR_TABLE_REG1_9_OFFSET |
Referenced by i3c_device_char_table_reg1_9_get(), and i3c_device_char_table_reg1_9_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_OFFSET |
Referenced by i3c_device_char_table_reg2_0_get(), and i3c_device_char_table_reg2_0_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_OFFSET |
Referenced by i3c_device_char_table_reg2_10_get(), and i3c_device_char_table_reg2_10_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_OFFSET |
Referenced by i3c_device_char_table_reg2_11_get(), and i3c_device_char_table_reg2_11_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_1_OFFSET |
Referenced by i3c_device_char_table_reg2_1_get(), and i3c_device_char_table_reg2_1_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_OFFSET |
Referenced by i3c_device_char_table_reg2_2_get(), and i3c_device_char_table_reg2_2_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_OFFSET |
Referenced by i3c_device_char_table_reg2_3_get(), and i3c_device_char_table_reg2_3_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_OFFSET |
Referenced by i3c_device_char_table_reg2_4_get(), and i3c_device_char_table_reg2_4_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_OFFSET |
Referenced by i3c_device_char_table_reg2_5_get(), and i3c_device_char_table_reg2_5_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_OFFSET |
Referenced by i3c_device_char_table_reg2_6_get(), and i3c_device_char_table_reg2_6_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_OFFSET |
Referenced by i3c_device_char_table_reg2_7_get(), and i3c_device_char_table_reg2_7_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_OFFSET |
Referenced by i3c_device_char_table_reg2_8_get(), and i3c_device_char_table_reg2_8_set().
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_OFFSET |
Referenced by i3c_device_char_table_reg2_9_get(), and i3c_device_char_table_reg2_9_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_0_OFFSET |
Referenced by i3c_device_char_table_reg3_0_get(), and i3c_device_char_table_reg3_0_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_10_OFFSET |
Referenced by i3c_device_char_table_reg3_10_get(), and i3c_device_char_table_reg3_10_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_11_OFFSET |
Referenced by i3c_device_char_table_reg3_11_get(), and i3c_device_char_table_reg3_11_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_1_OFFSET |
Referenced by i3c_device_char_table_reg3_1_get(), and i3c_device_char_table_reg3_1_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_2_OFFSET |
Referenced by i3c_device_char_table_reg3_2_get(), and i3c_device_char_table_reg3_2_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_3_OFFSET |
Referenced by i3c_device_char_table_reg3_3_get(), and i3c_device_char_table_reg3_3_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_4_OFFSET |
Referenced by i3c_device_char_table_reg3_4_get(), and i3c_device_char_table_reg3_4_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_5_OFFSET |
Referenced by i3c_device_char_table_reg3_5_get(), and i3c_device_char_table_reg3_5_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_6_OFFSET |
Referenced by i3c_device_char_table_reg3_6_get(), and i3c_device_char_table_reg3_6_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_7_OFFSET |
Referenced by i3c_device_char_table_reg3_7_get(), and i3c_device_char_table_reg3_7_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_8_OFFSET |
Referenced by i3c_device_char_table_reg3_8_get(), and i3c_device_char_table_reg3_8_set().
| #define I3C_DEVICE_CHAR_TABLE_REG3_9_OFFSET |
Referenced by i3c_device_char_table_reg3_9_get(), and i3c_device_char_table_reg3_9_set().
| #define I3C_IBI_DATA_REG_OFFSET |
Referenced by i3c_ibi_data_reg_get(), and i3c_ibi_data_reg_set().
| #define I3C_IBI_RESP_REG_OFFSET |
Referenced by i3c_ibi_resp_reg_get(), and i3c_ibi_resp_reg_set().
| #define I3C_IRQ_STATUS_REG_OFFSET |
Referenced by i3c_irq_status_reg_get(), and i3c_irq_status_reg_set().
| #define I3C_MST_CNTL_EN_REG_OFFSET |
Referenced by i3c_mst_cntl_en_reg_get(), and i3c_mst_cntl_en_reg_set().
| #define I3C_RESP_REG_OFFSET |
Referenced by i3c_resp_reg_get(), and i3c_resp_reg_set().
| #define I3C_TCAS_TIMER_REG_OFFSET |
Referenced by i3c_tcas_timer_reg_get(), and i3c_tcas_timer_reg_set().
| #define I3C_TCBP_TIMER_REG_OFFSET |
Referenced by i3c_tcbp_timer_reg_get(), and i3c_tcbp_timer_reg_set().
| #define I3C_TCBSR_TIMER_REG_OFFSET |
Referenced by i3c_tcbsr_timer_reg_get(), and i3c_tcbsr_timer_reg_set().
| #define I3C_TDS_TIMER_REG_OFFSET |
Referenced by i3c_tds_timer_reg_get(), and i3c_tds_timer_reg_set().
| #define I3C_THD_DDR_TIMER_REG_OFFSET |
Referenced by i3c_thd_ddr_timer_reg_get(), and i3c_thd_ddr_timer_reg_set().
| #define I3C_THD_PP_TIMER_REG_OFFSET |
Referenced by i3c_thd_pp_timer_reg_get(), and i3c_thd_pp_timer_reg_set().
| #define I3C_THD_STA_TIMER_REG_OFFSET |
Referenced by i3c_thd_sta_timer_reg_get(), and i3c_thd_sta_timer_reg_set().
| #define I3C_THIGH_OD_TIMER_REG_OFFSET |
Referenced by i3c_thigh_od_timer_reg_get(), and i3c_thigh_od_timer_reg_set().
| #define I3C_THIGH_PP_TIMER_REG_OFFSET |
Referenced by i3c_thigh_pp_timer_reg_get(), and i3c_thigh_pp_timer_reg_set().
| #define I3C_THIGH_TIMER_REG_OFFSET |
Referenced by i3c_thigh_timer_reg_get(), and i3c_thigh_timer_reg_set().
| #define I3C_TIDLE_TIMER_REG_OFFSET |
Referenced by i3c_tidle_timer_reg_get(), and i3c_tidle_timer_reg_set().
| #define I3C_TLOW_OD_TIMER_REG_OFFSET |
Referenced by i3c_tlow_od_timer_reg_get(), and i3c_tlow_od_timer_reg_set().
| #define I3C_TLOW_PP_TIMER_REG_OFFSET |
Referenced by i3c_tlow_pp_timer_reg_get(), and i3c_tlow_pp_timer_reg_set().
| #define I3C_TLOW_TIMER_REG_OFFSET |
Referenced by i3c_tlow_timer_reg_get(), and i3c_tlow_timer_reg_set().
| #define I3C_TSCO_TIMER_REG_OFFSET |
Referenced by i3c_tsco_timer_reg_get(), and i3c_tsco_timer_reg_set().
| #define I3C_TSU_STA_TIMER_REG_OFFSET |
Referenced by i3c_tsu_sta_timer_reg_get(), and i3c_tsu_sta_timer_reg_set().
| #define I3C_TSU_STOP_TIMER_REG_OFFSET |
Referenced by i3c_tsu_stop_timer_reg_get(), and i3c_tsu_stop_timer_reg_set().
| #define I3C_TVD_DATA_TIMER_REG_OFFSET |
Referenced by i3c_tvd_data_timer_reg_get(), and i3c_tvd_data_timer_reg_set().
