 |
FreeRTOS port on GAP8/RISC-V
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 |
| #define I3C_BUS_AVAIL_TIMER_REG_BUS_AVAIL_TIMER_BIT |
| #define I3C_BUS_AVAIL_TIMER_REG_BUS_AVAIL_TIMER_MASK |
| #define I3C_BUS_AVAIL_TIMER_REG_BUS_AVAIL_TIMER_RESET |
| #define I3C_BUS_AVAIL_TIMER_REG_BUS_AVAIL_TIMER_WIDTH |
| #define I3C_BUS_FREE_TIMER_REG_BUS_FREE_TIMER_BIT |
| #define I3C_BUS_FREE_TIMER_REG_BUS_FREE_TIMER_MASK |
| #define I3C_BUS_FREE_TIMER_REG_BUS_FREE_TIMER_RESET |
| #define I3C_BUS_FREE_TIMER_REG_BUS_FREE_TIMER_WIDTH |
| #define I3C_CMD_TR_REQ_REG_1_DATA_BIT |
| #define I3C_CMD_TR_REQ_REG_1_DATA_MASK |
| #define I3C_CMD_TR_REQ_REG_1_DATA_RESET |
| #define I3C_CMD_TR_REQ_REG_1_DATA_WIDTH |
| #define I3C_CMD_TR_REQ_REG_2_CMD_REQ_BIT |
| #define I3C_CMD_TR_REQ_REG_2_CMD_REQ_MASK |
| #define I3C_CMD_TR_REQ_REG_2_CMD_REQ_RESET |
| #define I3C_CMD_TR_REQ_REG_2_CMD_REQ_WIDTH |
| #define I3C_DATA_RX_FIFO_REG_DATA_RX_BIT |
| #define I3C_DATA_RX_FIFO_REG_DATA_RX_MASK |
| #define I3C_DATA_RX_FIFO_REG_DATA_RX_RESET |
| #define I3C_DATA_RX_FIFO_REG_DATA_RX_WIDTH |
| #define I3C_DATA_TX_FIFO_REG_DATA_TX_BIT |
| #define I3C_DATA_TX_FIFO_REG_DATA_TX_MASK |
| #define I3C_DATA_TX_FIFO_REG_DATA_TX_RESET |
| #define I3C_DATA_TX_FIFO_REG_DATA_TX_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG0_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG0_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG0_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG0_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG0_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG0_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG0_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG0_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG0_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG0_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG0_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG0_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG0_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG0_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG0_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG0_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG0_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG0_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG0_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG0_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG0_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG0_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG0_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG0_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG0_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG0_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG0_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG0_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG0_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG0_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG0_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG0_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG10_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG10_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG10_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG10_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG10_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG10_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG10_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG10_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG10_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG10_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG10_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG10_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG10_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG10_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG10_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG10_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG10_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG10_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG10_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG10_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG10_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG10_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG10_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG10_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG10_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG10_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG10_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG10_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG10_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG10_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG10_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG10_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG11_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG11_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG11_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG11_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG11_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG11_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG11_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG11_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG11_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG11_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG11_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG11_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG11_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG11_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG11_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG11_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG11_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG11_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG11_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG11_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG11_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG11_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG11_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG11_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG11_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG11_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG11_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG11_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG11_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG11_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG11_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG11_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG1_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG1_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG1_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG1_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG1_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG1_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG1_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG1_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG1_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG1_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG1_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG1_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG1_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG1_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG1_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG1_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG1_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG1_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG1_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG1_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG1_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG1_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG1_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG1_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG1_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG1_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG1_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG1_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG1_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG1_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG1_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG1_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG2_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG2_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG2_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG2_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG2_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG2_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG2_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG2_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG2_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG2_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG2_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG2_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG2_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG2_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG2_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG2_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG2_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG2_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG2_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG2_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG2_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG2_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG2_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG2_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG2_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG2_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG2_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG2_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG2_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG2_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG2_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG2_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG3_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG3_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG3_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG3_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG3_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG3_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG3_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG3_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG3_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG3_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG3_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG3_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG3_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG3_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG3_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG3_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG3_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG3_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG3_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG3_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG3_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG3_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG3_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG3_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG3_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG3_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG3_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG3_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG3_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG3_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG3_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG3_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG4_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG4_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG4_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG4_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG4_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG4_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG4_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG4_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG4_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG4_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG4_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG4_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG4_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG4_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG4_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG4_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG4_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG4_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG4_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG4_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG4_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG4_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG4_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG4_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG4_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG4_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG4_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG4_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG4_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG4_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG4_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG4_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG5_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG5_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG5_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG5_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG5_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG5_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG5_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG5_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG5_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG5_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG5_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG5_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG5_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG5_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG5_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG5_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG5_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG5_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG5_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG5_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG5_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG5_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG5_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG5_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG5_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG5_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG5_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG5_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG5_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG5_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG5_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG5_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG6_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG6_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG6_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG6_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG6_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG6_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG6_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG6_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG6_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG6_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG6_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG6_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG6_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG6_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG6_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG6_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG6_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG6_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG6_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG6_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG6_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG6_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG6_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG6_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG6_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG6_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG6_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG6_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG6_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG6_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG6_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG6_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG7_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG7_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG7_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG7_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG7_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG7_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG7_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG7_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG7_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG7_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG7_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG7_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG7_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG7_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG7_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG7_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG7_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG7_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG7_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG7_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG7_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG7_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG7_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG7_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG7_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG7_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG7_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG7_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG7_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG7_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG7_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG7_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG8_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG8_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG8_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG8_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG8_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG8_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG8_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG8_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG8_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG8_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG8_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG8_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG8_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG8_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG8_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG8_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG8_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG8_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG8_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG8_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG8_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG8_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG8_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG8_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG8_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG8_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG8_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG8_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG8_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG8_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG8_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG8_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG9_DEVICE_TYPE_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG9_DEVICE_TYPE_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG9_DEVICE_TYPE_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG9_DEVICE_TYPE_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG9_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG9_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG9_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG9_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG9_IBI_PAYLOAD_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG9_IBI_PAYLOAD_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG9_IBI_PAYLOAD_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG9_IBI_PAYLOAD_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG9_IN_BAND_REQ_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG9_IN_BAND_REQ_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG9_IN_BAND_REQ_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG9_IN_BAND_REQ_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG9_RESERVED_0_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG9_RESERVED_0_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG9_RESERVED_0_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG9_RESERVED_0_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG9_RESERVED_5_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG9_RESERVED_5_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG9_RESERVED_5_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG9_RESERVED_5_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG9_STATIC_ADDR_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG9_STATIC_ADDR_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG9_STATIC_ADDR_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG9_STATIC_ADDR_WIDTH |
| #define I3C_DEVICE_ADDR_TABLE_REG9_TIMESTAMP_BIT |
| #define I3C_DEVICE_ADDR_TABLE_REG9_TIMESTAMP_MASK |
| #define I3C_DEVICE_ADDR_TABLE_REG9_TIMESTAMP_RESET |
| #define I3C_DEVICE_ADDR_TABLE_REG9_TIMESTAMP_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_0_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_0_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_0_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_0_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_10_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_10_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_10_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_10_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_11_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_11_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_11_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_11_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_2_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_2_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_2_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_2_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_3_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_3_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_3_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_3_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_4_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_4_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_4_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_4_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_5_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_5_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_5_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_5_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_6_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_6_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_6_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_6_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_7_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_7_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_7_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_7_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_8_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_8_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_8_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_8_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG0_9_PID_HIGH_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG0_9_PID_HIGH_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG0_9_PID_HIGH_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG0_9_PID_HIGH_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_0_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_0_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_0_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_0_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_0_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_0_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_0_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_0_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_10_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_10_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_10_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_10_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_10_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_10_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_10_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_10_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_11_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_11_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_11_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_11_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_11_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_11_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_11_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_11_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_2_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_2_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_2_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_2_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_2_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_2_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_2_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_2_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_3_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_3_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_3_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_3_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_3_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_3_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_3_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_3_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_4_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_4_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_4_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_4_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_4_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_4_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_4_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_4_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_5_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_5_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_5_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_5_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_5_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_5_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_5_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_5_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_6_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_6_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_6_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_6_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_6_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_6_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_6_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_6_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_7_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_7_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_7_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_7_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_7_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_7_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_7_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_7_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_8_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_8_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_8_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_8_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_8_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_8_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_8_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_8_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_9_PID_LOW_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_9_PID_LOW_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_9_PID_LOW_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_9_PID_LOW_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG1_9_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG1_9_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG1_9_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG1_9_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_0_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_10_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_11_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_2_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_3_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_4_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_5_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_6_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_7_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_8_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_BCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_BCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_BCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_BCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_DCR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_DCR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_DCR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_DCR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_DYNAMIC_ADDR_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_DYNAMIC_ADDR_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_DYNAMIC_ADDR_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_DYNAMIC_ADDR_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG2_9_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_0_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_0_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_0_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_0_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_10_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_10_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_10_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_10_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_11_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_11_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_11_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_11_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_2_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_2_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_2_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_2_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_3_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_3_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_3_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_3_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_4_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_4_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_4_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_4_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_5_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_5_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_5_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_5_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_6_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_6_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_6_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_6_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_7_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_7_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_7_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_7_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_8_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_8_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_8_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_8_RESERVED_0_WIDTH |
| #define I3C_DEVICE_CHAR_TABLE_REG3_9_RESERVED_0_BIT |
| #define I3C_DEVICE_CHAR_TABLE_REG3_9_RESERVED_0_MASK |
| #define I3C_DEVICE_CHAR_TABLE_REG3_9_RESERVED_0_RESET |
| #define I3C_DEVICE_CHAR_TABLE_REG3_9_RESERVED_0_WIDTH |
| #define I3C_IBI_DATA_REG_IBI_DATA_BIT |
| #define I3C_IBI_DATA_REG_IBI_DATA_MASK |
| #define I3C_IBI_DATA_REG_IBI_DATA_RESET |
| #define I3C_IBI_DATA_REG_IBI_DATA_WIDTH |
| #define I3C_IBI_RESP_REG_DATA_LEN_BIT |
| #define I3C_IBI_RESP_REG_DATA_LEN_MASK |
| #define I3C_IBI_RESP_REG_DATA_LEN_RESET |
| #define I3C_IBI_RESP_REG_DATA_LEN_WIDTH |
| #define I3C_IBI_RESP_REG_IBI_ID_BIT |
| #define I3C_IBI_RESP_REG_IBI_ID_MASK |
| #define I3C_IBI_RESP_REG_IBI_ID_RESET |
| #define I3C_IBI_RESP_REG_IBI_ID_WIDTH |
| #define I3C_IBI_RESP_REG_IBI_STS_BIT |
| #define I3C_IBI_RESP_REG_IBI_STS_MASK |
| #define I3C_IBI_RESP_REG_IBI_STS_RESET |
| #define I3C_IBI_RESP_REG_IBI_STS_WIDTH |
| #define I3C_IBI_RESP_REG_RESERVED_0_BIT |
| #define I3C_IBI_RESP_REG_RESERVED_0_MASK |
| #define I3C_IBI_RESP_REG_RESERVED_0_RESET |
| #define I3C_IBI_RESP_REG_RESERVED_0_WIDTH |
| #define I3C_IBI_RESP_REG_RESERVED_5_BIT |
| #define I3C_IBI_RESP_REG_RESERVED_5_MASK |
| #define I3C_IBI_RESP_REG_RESERVED_5_RESET |
| #define I3C_IBI_RESP_REG_RESERVED_5_WIDTH |
| #define I3C_IBI_RESP_REG_TS_PRESENT_BIT |
| #define I3C_IBI_RESP_REG_TS_PRESENT_MASK |
| #define I3C_IBI_RESP_REG_TS_PRESENT_RESET |
| #define I3C_IBI_RESP_REG_TS_PRESENT_WIDTH |
| #define I3C_IRQ_STATUS_REG_CMD_REQ_FIFO_FULL_BIT |
| #define I3C_IRQ_STATUS_REG_CMD_REQ_FIFO_FULL_MASK |
| #define I3C_IRQ_STATUS_REG_CMD_REQ_FIFO_FULL_RESET |
| #define I3C_IRQ_STATUS_REG_CMD_REQ_FIFO_FULL_WIDTH |
| #define I3C_IRQ_STATUS_REG_DATA_RX_FIFO_FULL_BIT |
| #define I3C_IRQ_STATUS_REG_DATA_RX_FIFO_FULL_MASK |
| #define I3C_IRQ_STATUS_REG_DATA_RX_FIFO_FULL_RESET |
| #define I3C_IRQ_STATUS_REG_DATA_RX_FIFO_FULL_WIDTH |
| #define I3C_IRQ_STATUS_REG_DATA_TX_FIFO_EMPTY_BIT |
| #define I3C_IRQ_STATUS_REG_DATA_TX_FIFO_EMPTY_MASK |
| #define I3C_IRQ_STATUS_REG_DATA_TX_FIFO_EMPTY_RESET |
| #define I3C_IRQ_STATUS_REG_DATA_TX_FIFO_EMPTY_WIDTH |
| #define I3C_IRQ_STATUS_REG_DATA_TX_FIFO_FULL_BIT |
| #define I3C_IRQ_STATUS_REG_DATA_TX_FIFO_FULL_MASK |
| #define I3C_IRQ_STATUS_REG_DATA_TX_FIFO_FULL_RESET |
| #define I3C_IRQ_STATUS_REG_DATA_TX_FIFO_FULL_WIDTH |
| #define I3C_IRQ_STATUS_REG_IBI_DATA_RX_FIFO_FULL_BIT |
| #define I3C_IRQ_STATUS_REG_IBI_DATA_RX_FIFO_FULL_MASK |
| #define I3C_IRQ_STATUS_REG_IBI_DATA_RX_FIFO_FULL_RESET |
| #define I3C_IRQ_STATUS_REG_IBI_DATA_RX_FIFO_FULL_WIDTH |
| #define I3C_IRQ_STATUS_REG_IBI_TRANSFER_DONE_BIT |
| #define I3C_IRQ_STATUS_REG_IBI_TRANSFER_DONE_MASK |
| #define I3C_IRQ_STATUS_REG_IBI_TRANSFER_DONE_RESET |
| #define I3C_IRQ_STATUS_REG_IBI_TRANSFER_DONE_WIDTH |
| #define I3C_IRQ_STATUS_REG_RESERVED_0_BIT |
| #define I3C_IRQ_STATUS_REG_RESERVED_0_MASK |
| #define I3C_IRQ_STATUS_REG_RESERVED_0_RESET |
| #define I3C_IRQ_STATUS_REG_RESERVED_0_WIDTH |
| #define I3C_IRQ_STATUS_REG_RESP_COMPL_BIT |
| #define I3C_IRQ_STATUS_REG_RESP_COMPL_MASK |
| #define I3C_IRQ_STATUS_REG_RESP_COMPL_RESET |
| #define I3C_IRQ_STATUS_REG_RESP_COMPL_WIDTH |
| #define I3C_IRQ_STATUS_REG_RESP_DONE_BIT |
| #define I3C_IRQ_STATUS_REG_RESP_DONE_MASK |
| #define I3C_IRQ_STATUS_REG_RESP_DONE_RESET |
| #define I3C_IRQ_STATUS_REG_RESP_DONE_WIDTH |
| #define I3C_IRQ_STATUS_REG_RST_COMPLETION_BIT |
| #define I3C_IRQ_STATUS_REG_RST_COMPLETION_MASK |
| #define I3C_IRQ_STATUS_REG_RST_COMPLETION_RESET |
| #define I3C_IRQ_STATUS_REG_RST_COMPLETION_WIDTH |
| #define I3C_MST_CNTL_EN_REG_MASTER_CONTROL_EN_BIT |
| #define I3C_MST_CNTL_EN_REG_MASTER_CONTROL_EN_MASK |
| #define I3C_MST_CNTL_EN_REG_MASTER_CONTROL_EN_RESET |
| #define I3C_MST_CNTL_EN_REG_MASTER_CONTROL_EN_WIDTH |
| #define I3C_MST_CNTL_EN_REG_MASTER_RST_EN_BIT |
| #define I3C_MST_CNTL_EN_REG_MASTER_RST_EN_MASK |
| #define I3C_MST_CNTL_EN_REG_MASTER_RST_EN_RESET |
| #define I3C_MST_CNTL_EN_REG_MASTER_RST_EN_WIDTH |
| #define I3C_MST_CNTL_EN_REG_RESERVED_0_BIT |
| #define I3C_MST_CNTL_EN_REG_RESERVED_0_MASK |
| #define I3C_MST_CNTL_EN_REG_RESERVED_0_RESET |
| #define I3C_MST_CNTL_EN_REG_RESERVED_0_WIDTH |
| #define I3C_RESP_REG_RESP_REG_BIT |
| #define I3C_RESP_REG_RESP_REG_MASK |
| #define I3C_RESP_REG_RESP_REG_RESET |
| #define I3C_RESP_REG_RESP_REG_WIDTH |
| #define I3C_TCAS_TIMER_REG_TCAS_TIMER_BIT |
| #define I3C_TCAS_TIMER_REG_TCAS_TIMER_MASK |
| #define I3C_TCAS_TIMER_REG_TCAS_TIMER_RESET |
| #define I3C_TCAS_TIMER_REG_TCAS_TIMER_WIDTH |
| #define I3C_TCBP_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TCBP_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TCBP_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TCBP_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TCBP_TIMER_REG_TCBP_TIMER_BIT |
| #define I3C_TCBP_TIMER_REG_TCBP_TIMER_MASK |
| #define I3C_TCBP_TIMER_REG_TCBP_TIMER_RESET |
| #define I3C_TCBP_TIMER_REG_TCBP_TIMER_WIDTH |
| #define I3C_TCBSR_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TCBSR_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TCBSR_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TCBSR_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TCBSR_TIMER_REG_TCBSR_TIMER_BIT |
| #define I3C_TCBSR_TIMER_REG_TCBSR_TIMER_MASK |
| #define I3C_TCBSR_TIMER_REG_TCBSR_TIMER_RESET |
| #define I3C_TCBSR_TIMER_REG_TCBSR_TIMER_WIDTH |
| #define I3C_TDS_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TDS_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TDS_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TDS_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TDS_TIMER_REG_TDS_TIMER_BIT |
| #define I3C_TDS_TIMER_REG_TDS_TIMER_MASK |
| #define I3C_TDS_TIMER_REG_TDS_TIMER_RESET |
| #define I3C_TDS_TIMER_REG_TDS_TIMER_WIDTH |
| #define I3C_THD_DDR_TIMER_REG_RESERVED_0_BIT |
| #define I3C_THD_DDR_TIMER_REG_RESERVED_0_MASK |
| #define I3C_THD_DDR_TIMER_REG_RESERVED_0_RESET |
| #define I3C_THD_DDR_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_THD_DDR_TIMER_REG_THD_DDR_TIMER_BIT |
| #define I3C_THD_DDR_TIMER_REG_THD_DDR_TIMER_MASK |
| #define I3C_THD_DDR_TIMER_REG_THD_DDR_TIMER_RESET |
| #define I3C_THD_DDR_TIMER_REG_THD_DDR_TIMER_WIDTH |
| #define I3C_THD_PP_TIMER_REG_RESERVED_0_BIT |
| #define I3C_THD_PP_TIMER_REG_RESERVED_0_MASK |
| #define I3C_THD_PP_TIMER_REG_RESERVED_0_RESET |
| #define I3C_THD_PP_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_THD_PP_TIMER_REG_THD_PP_TIMER_BIT |
| #define I3C_THD_PP_TIMER_REG_THD_PP_TIMER_MASK |
| #define I3C_THD_PP_TIMER_REG_THD_PP_TIMER_RESET |
| #define I3C_THD_PP_TIMER_REG_THD_PP_TIMER_WIDTH |
| #define I3C_THD_STA_TIMER_REG_THD_STA_TIMER_BIT |
| #define I3C_THD_STA_TIMER_REG_THD_STA_TIMER_MASK |
| #define I3C_THD_STA_TIMER_REG_THD_STA_TIMER_RESET |
| #define I3C_THD_STA_TIMER_REG_THD_STA_TIMER_WIDTH |
| #define I3C_THIGH_OD_TIMER_REG_RESERVED_0_BIT |
| #define I3C_THIGH_OD_TIMER_REG_RESERVED_0_MASK |
| #define I3C_THIGH_OD_TIMER_REG_RESERVED_0_RESET |
| #define I3C_THIGH_OD_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_THIGH_OD_TIMER_REG_THIGH_OD_TIMER_BIT |
| #define I3C_THIGH_OD_TIMER_REG_THIGH_OD_TIMER_MASK |
| #define I3C_THIGH_OD_TIMER_REG_THIGH_OD_TIMER_RESET |
| #define I3C_THIGH_OD_TIMER_REG_THIGH_OD_TIMER_WIDTH |
| #define I3C_THIGH_PP_TIMER_REG_RESERVED_0_BIT |
| #define I3C_THIGH_PP_TIMER_REG_RESERVED_0_MASK |
| #define I3C_THIGH_PP_TIMER_REG_RESERVED_0_RESET |
| #define I3C_THIGH_PP_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_THIGH_PP_TIMER_REG_THIGH_PP_TIMER_BIT |
| #define I3C_THIGH_PP_TIMER_REG_THIGH_PP_TIMER_MASK |
| #define I3C_THIGH_PP_TIMER_REG_THIGH_PP_TIMER_RESET |
| #define I3C_THIGH_PP_TIMER_REG_THIGH_PP_TIMER_WIDTH |
| #define I3C_THIGH_TIMER_REG_RESERVED_0_BIT |
| #define I3C_THIGH_TIMER_REG_RESERVED_0_MASK |
| #define I3C_THIGH_TIMER_REG_RESERVED_0_RESET |
| #define I3C_THIGH_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_THIGH_TIMER_REG_THIGH_TIMER_BIT |
| #define I3C_THIGH_TIMER_REG_THIGH_TIMER_MASK |
| #define I3C_THIGH_TIMER_REG_THIGH_TIMER_RESET |
| #define I3C_THIGH_TIMER_REG_THIGH_TIMER_WIDTH |
| #define I3C_TIDLE_TIMER_REG_TIDLE_TIMER_BIT |
| #define I3C_TIDLE_TIMER_REG_TIDLE_TIMER_MASK |
| #define I3C_TIDLE_TIMER_REG_TIDLE_TIMER_RESET |
| #define I3C_TIDLE_TIMER_REG_TIDLE_TIMER_WIDTH |
| #define I3C_TLOW_OD_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TLOW_OD_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TLOW_OD_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TLOW_OD_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TLOW_OD_TIMER_REG_TLOW_OD_TIMER_BIT |
| #define I3C_TLOW_OD_TIMER_REG_TLOW_OD_TIMER_MASK |
| #define I3C_TLOW_OD_TIMER_REG_TLOW_OD_TIMER_RESET |
| #define I3C_TLOW_OD_TIMER_REG_TLOW_OD_TIMER_WIDTH |
| #define I3C_TLOW_PP_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TLOW_PP_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TLOW_PP_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TLOW_PP_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TLOW_PP_TIMER_REG_TLOW_PP_TIMER_BIT |
| #define I3C_TLOW_PP_TIMER_REG_TLOW_PP_TIMER_MASK |
| #define I3C_TLOW_PP_TIMER_REG_TLOW_PP_TIMER_RESET |
| #define I3C_TLOW_PP_TIMER_REG_TLOW_PP_TIMER_WIDTH |
| #define I3C_TLOW_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TLOW_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TLOW_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TLOW_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TLOW_TIMER_REG_TLOW_TIMER_BIT |
| #define I3C_TLOW_TIMER_REG_TLOW_TIMER_MASK |
| #define I3C_TLOW_TIMER_REG_TLOW_TIMER_RESET |
| #define I3C_TLOW_TIMER_REG_TLOW_TIMER_WIDTH |
| #define I3C_TSCO_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TSCO_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TSCO_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TSCO_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TSCO_TIMER_REG_TSCO_TIMER_BIT |
| #define I3C_TSCO_TIMER_REG_TSCO_TIMER_MASK |
| #define I3C_TSCO_TIMER_REG_TSCO_TIMER_RESET |
| #define I3C_TSCO_TIMER_REG_TSCO_TIMER_WIDTH |
| #define I3C_TSU_STA_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TSU_STA_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TSU_STA_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TSU_STA_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TSU_STA_TIMER_REG_TSU_STA_TIMER_BIT |
| #define I3C_TSU_STA_TIMER_REG_TSU_STA_TIMER_MASK |
| #define I3C_TSU_STA_TIMER_REG_TSU_STA_TIMER_RESET |
| #define I3C_TSU_STA_TIMER_REG_TSU_STA_TIMER_WIDTH |
| #define I3C_TSU_STOP_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TSU_STOP_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TSU_STOP_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TSU_STOP_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TSU_STOP_TIMER_REG_TSU_STOP_TIMER_BIT |
| #define I3C_TSU_STOP_TIMER_REG_TSU_STOP_TIMER_MASK |
| #define I3C_TSU_STOP_TIMER_REG_TSU_STOP_TIMER_RESET |
| #define I3C_TSU_STOP_TIMER_REG_TSU_STOP_TIMER_WIDTH |
| #define I3C_TVD_DATA_TIMER_REG_RESERVED_0_BIT |
| #define I3C_TVD_DATA_TIMER_REG_RESERVED_0_MASK |
| #define I3C_TVD_DATA_TIMER_REG_RESERVED_0_RESET |
| #define I3C_TVD_DATA_TIMER_REG_RESERVED_0_WIDTH |
| #define I3C_TVD_DATA_TIMER_REG_TVD_DATA_TIMER_BIT |
| #define I3C_TVD_DATA_TIMER_REG_TVD_DATA_TIMER_MASK |
| #define I3C_TVD_DATA_TIMER_REG_TVD_DATA_TIMER_RESET |
| #define I3C_TVD_DATA_TIMER_REG_TVD_DATA_TIMER_WIDTH |
