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FreeRTOS port on GAP8/RISC-V
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| #define HWCE_ACQUIRE_ERR_BIT |
| #define HWCE_ACQUIRE_ERR_MASK |
| #define HWCE_ACQUIRE_ERR_RESET |
| #define HWCE_ACQUIRE_ERR_WIDTH |
| #define HWCE_ACQUIRE_ID_ERR_BIT |
| #define HWCE_ACQUIRE_ID_ERR_MASK |
| #define HWCE_ACQUIRE_ID_ERR_RESET |
| #define HWCE_ACQUIRE_ID_ERR_WIDTH |
| #define HWCE_FINISHED_JOBS_JOBS_BIT |
| #define HWCE_FINISHED_JOBS_JOBS_MASK |
| #define HWCE_FINISHED_JOBS_JOBS_RESET |
| #define HWCE_FINISHED_JOBS_JOBS_WIDTH |
| #define HWCE_GEN_CONFIG0_CONV_BIT |
| #define HWCE_GEN_CONFIG0_CONV_MASK |
| #define HWCE_GEN_CONFIG0_CONV_RESET |
| #define HWCE_GEN_CONFIG0_CONV_WIDTH |
| #define HWCE_GEN_CONFIG0_NCP_BIT |
| #define HWCE_GEN_CONFIG0_NCP_MASK |
| #define HWCE_GEN_CONFIG0_NCP_RESET |
| #define HWCE_GEN_CONFIG0_NCP_WIDTH |
| #define HWCE_GEN_CONFIG0_NF_BIT |
| #define HWCE_GEN_CONFIG0_NF_MASK |
| #define HWCE_GEN_CONFIG0_NF_RESET |
| #define HWCE_GEN_CONFIG0_NF_WIDTH |
| #define HWCE_GEN_CONFIG0_NY_BIT |
| #define HWCE_GEN_CONFIG0_NY_MASK |
| #define HWCE_GEN_CONFIG0_NY_RESET |
| #define HWCE_GEN_CONFIG0_NY_WIDTH |
| #define HWCE_GEN_CONFIG0_QF_BIT |
| #define HWCE_GEN_CONFIG0_QF_MASK |
| #define HWCE_GEN_CONFIG0_QF_RESET |
| #define HWCE_GEN_CONFIG0_QF_WIDTH |
| #define HWCE_GEN_CONFIG0_RND_BIT |
| #define HWCE_GEN_CONFIG0_RND_MASK |
| #define HWCE_GEN_CONFIG0_RND_RESET |
| #define HWCE_GEN_CONFIG0_RND_WIDTH |
| #define HWCE_GEN_CONFIG0_WSTRIDE_BIT |
| #define HWCE_GEN_CONFIG0_WSTRIDE_MASK |
| #define HWCE_GEN_CONFIG0_WSTRIDE_RESET |
| #define HWCE_GEN_CONFIG0_WSTRIDE_WIDTH |
| #define HWCE_GEN_CONFIG1_QMODEX_BIT |
| #define HWCE_GEN_CONFIG1_QMODEX_MASK |
| #define HWCE_GEN_CONFIG1_QMODEX_RESET |
| #define HWCE_GEN_CONFIG1_QMODEX_WIDTH |
| #define HWCE_GEN_CONFIG1_QMODEY_BIT |
| #define HWCE_GEN_CONFIG1_QMODEY_MASK |
| #define HWCE_GEN_CONFIG1_QMODEY_RESET |
| #define HWCE_GEN_CONFIG1_QMODEY_WIDTH |
| #define HWCE_GEN_CONFIG1_QSHIFTX_BIT |
| #define HWCE_GEN_CONFIG1_QSHIFTX_MASK |
| #define HWCE_GEN_CONFIG1_QSHIFTX_RESET |
| #define HWCE_GEN_CONFIG1_QSHIFTX_WIDTH |
| #define HWCE_GEN_CONFIG1_QSHIFTY_BIT |
| #define HWCE_GEN_CONFIG1_QSHIFTY_MASK |
| #define HWCE_GEN_CONFIG1_QSHIFTY_RESET |
| #define HWCE_GEN_CONFIG1_QSHIFTY_WIDTH |
| #define HWCE_GEN_CONFIG1_THSTRIDE_BIT |
| #define HWCE_GEN_CONFIG1_THSTRIDE_MASK |
| #define HWCE_GEN_CONFIG1_THSTRIDE_RESET |
| #define HWCE_GEN_CONFIG1_THSTRIDE_WIDTH |
| #define HWCE_GEN_CONFIG2_NORM_BIT |
| #define HWCE_GEN_CONFIG2_NORM_MASK |
| #define HWCE_GEN_CONFIG2_NORM_RESET |
| #define HWCE_GEN_CONFIG2_NORM_WIDTH |
| #define HWCE_GEN_CONFIG2_QMODEW_BIT |
| #define HWCE_GEN_CONFIG2_QMODEW_MASK |
| #define HWCE_GEN_CONFIG2_QMODEW_RESET |
| #define HWCE_GEN_CONFIG2_QMODEW_WIDTH |
| #define HWCE_GEN_CONFIG2_QSHIFTW_BIT |
| #define HWCE_GEN_CONFIG2_QSHIFTW_MASK |
| #define HWCE_GEN_CONFIG2_QSHIFTW_RESET |
| #define HWCE_GEN_CONFIG2_QSHIFTW_WIDTH |
| #define HWCE_GEN_CONFIG2_RECT_BIT |
| #define HWCE_GEN_CONFIG2_RECT_MASK |
| #define HWCE_GEN_CONFIG2_RECT_RESET |
| #define HWCE_GEN_CONFIG2_RECT_WIDTH |
| #define HWCE_GEN_CONFIG2_WAIT_NFEAT_BIT |
| #define HWCE_GEN_CONFIG2_WAIT_NFEAT_MASK |
| #define HWCE_GEN_CONFIG2_WAIT_NFEAT_RESET |
| #define HWCE_GEN_CONFIG2_WAIT_NFEAT_WIDTH |
| #define HWCE_GEN_CONFIG3_QOFFSW_BIT |
| #define HWCE_GEN_CONFIG3_QOFFSW_MASK |
| #define HWCE_GEN_CONFIG3_QOFFSW_RESET |
| #define HWCE_GEN_CONFIG3_QOFFSW_WIDTH |
| #define HWCE_GEN_CONFIG3_QOFFSX_BIT |
| #define HWCE_GEN_CONFIG3_QOFFSX_MASK |
| #define HWCE_GEN_CONFIG3_QOFFSX_RESET |
| #define HWCE_GEN_CONFIG3_QOFFSX_WIDTH |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFLEN_BIT |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFLEN_MASK |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFLEN_RESET |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFLEN_WIDTH |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFSKIPHI_BIT |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFSKIPHI_MASK |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFSKIPHI_RESET |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFSKIPHI_WIDTH |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFSKIPLO_BIT |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFSKIPLO_MASK |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFSKIPLO_RESET |
| #define HWCE_JOB_CONFIG0_ALIASED_LBUFSKIPLO_WIDTH |
| #define HWCE_JOB_CONFIG0_ALIASED_NOYCONST_BIT |
| #define HWCE_JOB_CONFIG0_ALIASED_NOYCONST_MASK |
| #define HWCE_JOB_CONFIG0_ALIASED_NOYCONST_RESET |
| #define HWCE_JOB_CONFIG0_ALIASED_NOYCONST_WIDTH |
| #define HWCE_JOB_CONFIG1_ALIASED_LO_BIT |
| #define HWCE_JOB_CONFIG1_ALIASED_LO_MASK |
| #define HWCE_JOB_CONFIG1_ALIASED_LO_RESET |
| #define HWCE_JOB_CONFIG1_ALIASED_LO_WIDTH |
| #define HWCE_JOB_CONFIG1_ALIASED_NOUTFEAT_BIT |
| #define HWCE_JOB_CONFIG1_ALIASED_NOUTFEAT_MASK |
| #define HWCE_JOB_CONFIG1_ALIASED_NOUTFEAT_RESET |
| #define HWCE_JOB_CONFIG1_ALIASED_NOUTFEAT_WIDTH |
| #define HWCE_JOB_CONFIG1_ALIASED_RECT_BIT |
| #define HWCE_JOB_CONFIG1_ALIASED_RECT_MASK |
| #define HWCE_JOB_CONFIG1_ALIASED_RECT_RESET |
| #define HWCE_JOB_CONFIG1_ALIASED_RECT_WIDTH |
| #define HWCE_JOB_CONFIG1_ALIASED_VECT_DISABLE_MASK_BIT |
| #define HWCE_JOB_CONFIG1_ALIASED_VECT_DISABLE_MASK_MASK |
| #define HWCE_JOB_CONFIG1_ALIASED_VECT_DISABLE_MASK_RESET |
| #define HWCE_JOB_CONFIG1_ALIASED_VECT_DISABLE_MASK_WIDTH |
| #define HWCE_JOB_CONFIG1_ALIASED_WIF_PARAM_BIT |
| #define HWCE_JOB_CONFIG1_ALIASED_WIF_PARAM_MASK |
| #define HWCE_JOB_CONFIG1_ALIASED_WIF_PARAM_RESET |
| #define HWCE_JOB_CONFIG1_ALIASED_WIF_PARAM_WIDTH |
| #define HWCE_JOB_CONFIG1_ALIASED_WOF_PARAM_BIT |
| #define HWCE_JOB_CONFIG1_ALIASED_WOF_PARAM_MASK |
| #define HWCE_JOB_CONFIG1_ALIASED_WOF_PARAM_RESET |
| #define HWCE_JOB_CONFIG1_ALIASED_WOF_PARAM_WIDTH |
| #define HWCE_JOB_CONFIG2_ALIASED_BYE_BIT |
| #define HWCE_JOB_CONFIG2_ALIASED_BYE_MASK |
| #define HWCE_JOB_CONFIG2_ALIASED_BYE_RESET |
| #define HWCE_JOB_CONFIG2_ALIASED_BYE_WIDTH |
| #define HWCE_JOB_CONFIG2_ALIASED_BYNFEAT_BIT |
| #define HWCE_JOB_CONFIG2_ALIASED_BYNFEAT_MASK |
| #define HWCE_JOB_CONFIG2_ALIASED_BYNFEAT_RESET |
| #define HWCE_JOB_CONFIG2_ALIASED_BYNFEAT_WIDTH |
| #define HWCE_JOB_CONFIG2_ALIASED_LBUFPRECNT_BIT |
| #define HWCE_JOB_CONFIG2_ALIASED_LBUFPRECNT_MASK |
| #define HWCE_JOB_CONFIG2_ALIASED_LBUFPRECNT_RESET |
| #define HWCE_JOB_CONFIG2_ALIASED_LBUFPRECNT_WIDTH |
| #define HWCE_JOB_CONFIG2_ALIASED_NORM_BIT |
| #define HWCE_JOB_CONFIG2_ALIASED_NORM_MASK |
| #define HWCE_JOB_CONFIG2_ALIASED_NORM_RESET |
| #define HWCE_JOB_CONFIG2_ALIASED_NORM_WIDTH |
| #define HWCE_JOB_CONFIG2_ALIASED_S2_BIT |
| #define HWCE_JOB_CONFIG2_ALIASED_S2_MASK |
| #define HWCE_JOB_CONFIG2_ALIASED_S2_RESET |
| #define HWCE_JOB_CONFIG2_ALIASED_S2_WIDTH |
| #define HWCE_JOB_CONFIG2_ALIASED_XLREM_BIT |
| #define HWCE_JOB_CONFIG2_ALIASED_XLREM_MASK |
| #define HWCE_JOB_CONFIG2_ALIASED_XLREM_RESET |
| #define HWCE_JOB_CONFIG2_ALIASED_XLREM_WIDTH |
| #define HWCE_JOB_CONFIG2_ALIASED_YLEN_BIT |
| #define HWCE_JOB_CONFIG2_ALIASED_YLEN_MASK |
| #define HWCE_JOB_CONFIG2_ALIASED_YLEN_RESET |
| #define HWCE_JOB_CONFIG2_ALIASED_YLEN_WIDTH |
| #define HWCE_JOB_CONFIG2_ALIASED_YLREM_BIT |
| #define HWCE_JOB_CONFIG2_ALIASED_YLREM_MASK |
| #define HWCE_JOB_CONFIG2_ALIASED_YLREM_RESET |
| #define HWCE_JOB_CONFIG2_ALIASED_YLREM_WIDTH |
| #define HWCE_OFFLOADER_ID_ID_BIT |
| #define HWCE_OFFLOADER_ID_ID_MASK |
| #define HWCE_OFFLOADER_ID_ID_RESET |
| #define HWCE_OFFLOADER_ID_ID_WIDTH |
| #define HWCE_RUNNING_JOB_ID_BIT |
| #define HWCE_RUNNING_JOB_ID_MASK |
| #define HWCE_RUNNING_JOB_ID_RESET |
| #define HWCE_RUNNING_JOB_ID_WIDTH |
| #define HWCE_SOFT_CLEAR_ANY_BIT |
| #define HWCE_SOFT_CLEAR_ANY_MASK |
| #define HWCE_SOFT_CLEAR_ANY_RESET |
| #define HWCE_SOFT_CLEAR_ANY_WIDTH |
| #define HWCE_STATUS_ST_BIT |
| #define HWCE_STATUS_ST_MASK |
| #define HWCE_STATUS_ST_RESET |
| #define HWCE_STATUS_ST_WIDTH |
| #define HWCE_SW_EVT_EVT_BIT |
| #define HWCE_SW_EVT_EVT_MASK |
| #define HWCE_SW_EVT_EVT_RESET |
| #define HWCE_SW_EVT_EVT_WIDTH |
| #define HWCE_TRIGGER_ANY_BIT |
| #define HWCE_TRIGGER_ANY_MASK |
| #define HWCE_TRIGGER_ANY_RESET |
| #define HWCE_TRIGGER_ANY_WIDTH |
| #define HWCE_W_BASE_ADDR_ALIASED_ADDR_BIT |
| #define HWCE_W_BASE_ADDR_ALIASED_ADDR_MASK |
| #define HWCE_W_BASE_ADDR_ALIASED_ADDR_RESET |
| #define HWCE_W_BASE_ADDR_ALIASED_ADDR_WIDTH |
| #define HWCE_X_FEAT_STRIDE_LENGTH_ALIASED_LENGTH_BIT |
| #define HWCE_X_FEAT_STRIDE_LENGTH_ALIASED_LENGTH_MASK |
| #define HWCE_X_FEAT_STRIDE_LENGTH_ALIASED_LENGTH_RESET |
| #define HWCE_X_FEAT_STRIDE_LENGTH_ALIASED_LENGTH_WIDTH |
| #define HWCE_X_FEAT_STRIDE_LENGTH_ALIASED_STRIDE_BIT |
| #define HWCE_X_FEAT_STRIDE_LENGTH_ALIASED_STRIDE_MASK |
| #define HWCE_X_FEAT_STRIDE_LENGTH_ALIASED_STRIDE_RESET |
| #define HWCE_X_FEAT_STRIDE_LENGTH_ALIASED_STRIDE_WIDTH |
| #define HWCE_X_IN_BASE_ADDR_ALIASED_ADDR_BIT |
| #define HWCE_X_IN_BASE_ADDR_ALIASED_ADDR_MASK |
| #define HWCE_X_IN_BASE_ADDR_ALIASED_ADDR_RESET |
| #define HWCE_X_IN_BASE_ADDR_ALIASED_ADDR_WIDTH |
| #define HWCE_X_LINE_STRIDE_LENGTH_ALIASED_LENGTH_BIT |
| #define HWCE_X_LINE_STRIDE_LENGTH_ALIASED_LENGTH_MASK |
| #define HWCE_X_LINE_STRIDE_LENGTH_ALIASED_LENGTH_RESET |
| #define HWCE_X_LINE_STRIDE_LENGTH_ALIASED_LENGTH_WIDTH |
| #define HWCE_X_LINE_STRIDE_LENGTH_ALIASED_STRIDE_BIT |
| #define HWCE_X_LINE_STRIDE_LENGTH_ALIASED_STRIDE_MASK |
| #define HWCE_X_LINE_STRIDE_LENGTH_ALIASED_STRIDE_RESET |
| #define HWCE_X_LINE_STRIDE_LENGTH_ALIASED_STRIDE_WIDTH |
| #define HWCE_X_TRANS_SIZE_ALIASED_SIZE_BIT |
| #define HWCE_X_TRANS_SIZE_ALIASED_SIZE_MASK |
| #define HWCE_X_TRANS_SIZE_ALIASED_SIZE_RESET |
| #define HWCE_X_TRANS_SIZE_ALIASED_SIZE_WIDTH |
| #define HWCE_Y_FEAT_STRIDE_LENGTH_ALIASED_LENGTH_BIT |
| #define HWCE_Y_FEAT_STRIDE_LENGTH_ALIASED_LENGTH_MASK |
| #define HWCE_Y_FEAT_STRIDE_LENGTH_ALIASED_LENGTH_RESET |
| #define HWCE_Y_FEAT_STRIDE_LENGTH_ALIASED_LENGTH_WIDTH |
| #define HWCE_Y_FEAT_STRIDE_LENGTH_ALIASED_STRIDE_BIT |
| #define HWCE_Y_FEAT_STRIDE_LENGTH_ALIASED_STRIDE_MASK |
| #define HWCE_Y_FEAT_STRIDE_LENGTH_ALIASED_STRIDE_RESET |
| #define HWCE_Y_FEAT_STRIDE_LENGTH_ALIASED_STRIDE_WIDTH |
| #define HWCE_Y_IN_0_BASE_ADDR_ALIASED_ADDR_BIT |
| #define HWCE_Y_IN_0_BASE_ADDR_ALIASED_ADDR_MASK |
| #define HWCE_Y_IN_0_BASE_ADDR_ALIASED_ADDR_RESET |
| #define HWCE_Y_IN_0_BASE_ADDR_ALIASED_ADDR_WIDTH |
| #define HWCE_Y_IN_1_BASE_ADDR_ALIASED_ADDR_BIT |
| #define HWCE_Y_IN_1_BASE_ADDR_ALIASED_ADDR_MASK |
| #define HWCE_Y_IN_1_BASE_ADDR_ALIASED_ADDR_RESET |
| #define HWCE_Y_IN_1_BASE_ADDR_ALIASED_ADDR_WIDTH |
| #define HWCE_Y_IN_2_BASE_ADDR_ALIASED_ADDR_BIT |
| #define HWCE_Y_IN_2_BASE_ADDR_ALIASED_ADDR_MASK |
| #define HWCE_Y_IN_2_BASE_ADDR_ALIASED_ADDR_RESET |
| #define HWCE_Y_IN_2_BASE_ADDR_ALIASED_ADDR_WIDTH |
| #define HWCE_Y_LINE_STRIDE_LENGTH_ALIASED_LENGTH_BIT |
| #define HWCE_Y_LINE_STRIDE_LENGTH_ALIASED_LENGTH_MASK |
| #define HWCE_Y_LINE_STRIDE_LENGTH_ALIASED_LENGTH_RESET |
| #define HWCE_Y_LINE_STRIDE_LENGTH_ALIASED_LENGTH_WIDTH |
| #define HWCE_Y_LINE_STRIDE_LENGTH_ALIASED_STRIDE_BIT |
| #define HWCE_Y_LINE_STRIDE_LENGTH_ALIASED_STRIDE_MASK |
| #define HWCE_Y_LINE_STRIDE_LENGTH_ALIASED_STRIDE_RESET |
| #define HWCE_Y_LINE_STRIDE_LENGTH_ALIASED_STRIDE_WIDTH |
| #define HWCE_Y_OUT_0_BASE_ADDR_ALIASED_ADDR_BIT |
| #define HWCE_Y_OUT_0_BASE_ADDR_ALIASED_ADDR_MASK |
| #define HWCE_Y_OUT_0_BASE_ADDR_ALIASED_ADDR_RESET |
| #define HWCE_Y_OUT_0_BASE_ADDR_ALIASED_ADDR_WIDTH |
| #define HWCE_Y_OUT_1_BASE_ADDR_ALIASED_ADDR_BIT |
| #define HWCE_Y_OUT_1_BASE_ADDR_ALIASED_ADDR_MASK |
| #define HWCE_Y_OUT_1_BASE_ADDR_ALIASED_ADDR_RESET |
| #define HWCE_Y_OUT_1_BASE_ADDR_ALIASED_ADDR_WIDTH |
| #define HWCE_Y_OUT_2_BASE_ADDR_ALIASED_ADDR_BIT |
| #define HWCE_Y_OUT_2_BASE_ADDR_ALIASED_ADDR_MASK |
| #define HWCE_Y_OUT_2_BASE_ADDR_ALIASED_ADDR_RESET |
| #define HWCE_Y_OUT_2_BASE_ADDR_ALIASED_ADDR_WIDTH |
| #define HWCE_Y_TRANS_SIZE_ALIASED_SIZE_BIT |
| #define HWCE_Y_TRANS_SIZE_ALIASED_SIZE_MASK |
| #define HWCE_Y_TRANS_SIZE_ALIASED_SIZE_RESET |
| #define HWCE_Y_TRANS_SIZE_ALIASED_SIZE_WIDTH |
