CMSIS Core Register Access Functions

Macros
#define	__get_BASEPRI()
#define	__get_PRIMASK()
#define	__get_BASEPRI()
#define	__get_PRIMASK()

Functions
	__attribute__ ((always_inline)) __STATIC_INLINE uint32_t __get_CPRIV(void)
	Get PRIVLVL Register. More...
typedef signed short v2s	__attribute__ ((vector_size(4)))
	Restore the MIE bit. More...

Description

Macro Definition Documentation

#define __get_BASEPRI

(

)

#define __get_BASEPRI

(

)

#define __get_PRIMASK

(

)

#define __get_PRIMASK

(

)

Typedef Documentation

__attribute__

inline

Disable EBREAKM core stall.

Enable EBREAKM core stall.

Get PRIVLVL Register.

Data Memory Barrier.

Data Synchronization Barrier.

Instruction Synchronization Barrier.

Get the running mode is Machine Mode.

Get the running mode is User Mode.

Set Main Stack Pointer.

Get Main Stack Pointer.

Set Process Stack Pointer.

Get Process Stack Pointer.

Get USTATUS Register.

Get MSTATUS Register.

Get UCAUSE Register.

Get MCAUSE Register.

Set mstatus Register.

Set ustatus Register.

Disable IRQ Interrupts.

Enable IRQ Interrupts.

Restore the MIE bit of MSTATUS

Enables IRQ interrupts by setting the MPIE-bit in the MSTATUS. Can only be executed in Privileged modes.

Disables IRQ interrupts by clearing the MPIE-bit in the CPSR. Can only be executed in Privileged modes.

Writes the given value to the ustatus Register.

Parameters

[in]

control

ustatus Register value to set

Writes the given value to the mstatus Register.

Parameters

[in]

control

mstatus Register value to set

Returns the content of the MCAUSE Register.

Returns

MCAUSE Register value

Returns the content of the UCAUSE Register.

Returns

UCAUSE Register value

Returns the content of the MSTATUS Register.

Returns

MSTATUS Register value

Returns the content of the USTATUS Register.

Returns

USTATUS Register value

Returns the current value of the Process Stack Pointer (PSP).

Returns

PSP Register value

Assigns the given value to the Process Stack Pointer (PSP).

Parameters

[in]

topOfProcStack

Process Stack Pointer value to set

Returns the current value of the Main Stack Pointer (MSP).

Returns

MSP Register value

Assigns the given value to the Main Stack Pointer (MSP).

Parameters

[in]

topOfMainStack

Main Stack Pointer value to set

Read 0xC10 privilege register

Returns

Is User mode

Read 0xC10 privilege register

Returns

Is Machine mode

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

Returns the content of the PRIVLVL Register.

Returns

PRIVLVL Register value

Enables EBREAKM core stall by setting the ebreakm bit in the DCSR. Can only be executed in Privileged modes.

Disables EBREAKM core stall by clearing the ebreakm bit in the DCSR. Can only be executed in Privileged modes.

Function Documentation

__attribute__

(

(always_inline)

)

Disable EBREAKM core stall.

Enable EBREAKM core stall.

Data Memory Barrier.

Data Synchronization Barrier.

Instruction Synchronization Barrier.

Get the running mode is Machine Mode.

Get the running mode is User Mode.

Set Main Stack Pointer.

Get Main Stack Pointer.

Set Process Stack Pointer.

Get Process Stack Pointer.

Get USTATUS Register.

Get MSTATUS Register.

Get UCAUSE Register.

Get MCAUSE Register.

Set mstatus Register.

Set ustatus Register.

Disable IRQ Interrupts.

Enable IRQ Interrupts.

Restore the MIE bit.

Returns the content of the PRIVLVL Register.

Returns

PRIVLVL Register value

Restore the MIE bit of MSTATUS

Enables IRQ interrupts by setting the MPIE-bit in the MSTATUS. Can only be executed in Privileged modes.

Disables IRQ interrupts by clearing the MPIE-bit in the CPSR. Can only be executed in Privileged modes.

Writes the given value to the ustatus Register.

Parameters

[in]

control

ustatus Register value to set

Writes the given value to the mstatus Register.

Parameters

[in]

control

mstatus Register value to set

Returns the content of the MCAUSE Register.

Returns

MCAUSE Register value

Returns the content of the UCAUSE Register.

Returns

UCAUSE Register value

Returns the content of the MSTATUS Register.

Returns

MSTATUS Register value

Returns the content of the USTATUS Register.

Returns

USTATUS Register value

Returns the current value of the Process Stack Pointer (PSP).

Returns

PSP Register value

Assigns the given value to the Process Stack Pointer (PSP).

Parameters

[in]

topOfProcStack

Process Stack Pointer value to set

Returns the current value of the Main Stack Pointer (MSP).

Returns

MSP Register value

Assigns the given value to the Main Stack Pointer (MSP).

Parameters

[in]

topOfMainStack

Main Stack Pointer value to set

Read 0xC10 privilege register

Returns

Is User mode

Read 0xC10 privilege register

Returns

Is Machine mode

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

Enables EBREAKM core stall by setting the ebreakm bit in the DCSR. Can only be executed in Privileged modes.

Disables EBREAKM core stall by clearing the ebreakm bit in the DCSR. Can only be executed in Privileged modes.