FreeRTOS port on GAP8/RISC-V
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Data Structures | |
union | rtc_rtc_sr_t |
union | rtc_rtc_cr_t |
union | rtc_rtc_ccr_t |
union | rtc_rtc_icr_t |
union | rtc_rtc_imr_t |
union | rtc_rtc_ifr_t |
union | rtc_calendar_control_t |
union | rtc_calendar_time_t |
union | rtc_calendar_date_t |
union | rtc_alarm_control_t |
union | rtc_alarm1_time_t |
union | rtc_alarm1_date_t |
union | rtc_countdown_control_t |
union | rtc_countdown1_init_t |
union | rtc_countdown1_timer_t |
union | rtc_ckin_div1_t |
union | rtc_ckref_conf_t |
union | rtc_rtc_test_reg_a_t |
#define ALARM1_DATE_OFFSET |
RTC alarm 1 date register.
#define ALARM1_TIME_OFFSET |
RTC alarm 1 time register.
#define ALARM_CONTROL_OFFSET |
RTC alarm control register.
#define CALENDAR_CONTROL_OFFSET |
RTC calendar control register.
#define CALENDAR_DATE_OFFSET |
RTC calendar date register.
#define CALENDAR_TIME_OFFSET |
RTC calendar time register.
#define CKIN_DIV1_OFFSET |
RTC CKIN divider 1 register.
#define CKREF_CONF_OFFSET |
RTC reference clock configuration register.
#define COUNTDOWN1_INIT_OFFSET |
RTC countdown 1 initialisation register.
#define COUNTDOWN1_TIMER_OFFSET |
RTC countdown 1 timer register.
#define COUNTDOWN_CONTROL_OFFSET |
RTC countdown control register.
#define RTC_ALARM1_DATE_DAY0 | ( | val | ) |
#define RTC_ALARM1_DATE_DAY0_MASK |
#define RTC_ALARM1_DATE_DAY0_SHIFT |
#define RTC_ALARM1_DATE_DAY1 | ( | val | ) |
#define RTC_ALARM1_DATE_DAY1_MASK |
#define RTC_ALARM1_DATE_DAY1_SHIFT |
#define RTC_ALARM1_DATE_MON0 | ( | val | ) |
#define RTC_ALARM1_DATE_MON0_MASK |
#define RTC_ALARM1_DATE_MON0_SHIFT |
#define RTC_ALARM1_DATE_MON1 | ( | val | ) |
#define RTC_ALARM1_DATE_MON1_MASK |
#define RTC_ALARM1_DATE_MON1_SHIFT |
#define RTC_ALARM1_DATE_YEA0 | ( | val | ) |
#define RTC_ALARM1_DATE_YEA0_MASK |
#define RTC_ALARM1_DATE_YEA0_SHIFT |
#define RTC_ALARM1_DATE_YEA1 | ( | val | ) |
#define RTC_ALARM1_DATE_YEA1_MASK |
#define RTC_ALARM1_DATE_YEA1_SHIFT |
#define RTC_ALARM1_TIME_HOU0 | ( | val | ) |
#define RTC_ALARM1_TIME_HOU0_MASK |
#define RTC_ALARM1_TIME_HOU0_SHIFT |
#define RTC_ALARM1_TIME_HOU1 | ( | val | ) |
#define RTC_ALARM1_TIME_HOU1_MASK |
#define RTC_ALARM1_TIME_HOU1_SHIFT |
#define RTC_ALARM1_TIME_MIN0 | ( | val | ) |
#define RTC_ALARM1_TIME_MIN0_MASK |
#define RTC_ALARM1_TIME_MIN0_SHIFT |
#define RTC_ALARM1_TIME_MIN1 | ( | val | ) |
#define RTC_ALARM1_TIME_MIN1_MASK |
#define RTC_ALARM1_TIME_MIN1_SHIFT |
#define RTC_ALARM1_TIME_SEC0 | ( | val | ) |
#define RTC_ALARM1_TIME_SEC0_MASK |
#define RTC_ALARM1_TIME_SEC0_SHIFT |
#define RTC_ALARM1_TIME_SEC1 | ( | val | ) |
#define RTC_ALARM1_TIME_SEC1_MASK |
#define RTC_ALARM1_TIME_SEC1_SHIFT |
#define RTC_ALARM_CONTROL_CFG | ( | val | ) |
#define RTC_ALARM_CONTROL_CFG_MASK |
#define RTC_ALARM_CONTROL_CFG_SHIFT |
#define RTC_ALARM_CONTROL_MODE | ( | val | ) |
#define RTC_ALARM_CONTROL_MODE_MASK |
#define RTC_ALARM_CONTROL_MODE_SHIFT |
#define RTC_ALARM_CONTROL_SB | ( | val | ) |
#define RTC_ALARM_CONTROL_SB_MASK |
#define RTC_ALARM_CONTROL_SB_SHIFT |
#define RTC_CALENDAR_CONTROL_SB | ( | val | ) |
#define RTC_CALENDAR_CONTROL_SB_MASK |
#define RTC_CALENDAR_CONTROL_SB_SHIFT |
#define RTC_CALENDAR_DATE_DAY0 | ( | val | ) |
#define RTC_CALENDAR_DATE_DAY0_MASK |
#define RTC_CALENDAR_DATE_DAY0_SHIFT |
#define RTC_CALENDAR_DATE_DAY1 | ( | val | ) |
#define RTC_CALENDAR_DATE_DAY1_MASK |
#define RTC_CALENDAR_DATE_DAY1_SHIFT |
#define RTC_CALENDAR_DATE_MON0 | ( | val | ) |
#define RTC_CALENDAR_DATE_MON0_MASK |
#define RTC_CALENDAR_DATE_MON0_SHIFT |
#define RTC_CALENDAR_DATE_MON1 | ( | val | ) |
#define RTC_CALENDAR_DATE_MON1_MASK |
#define RTC_CALENDAR_DATE_MON1_SHIFT |
#define RTC_CALENDAR_DATE_YEA0 | ( | val | ) |
#define RTC_CALENDAR_DATE_YEA0_MASK |
#define RTC_CALENDAR_DATE_YEA0_SHIFT |
#define RTC_CALENDAR_DATE_YEA1 | ( | val | ) |
#define RTC_CALENDAR_DATE_YEA1_MASK |
#define RTC_CALENDAR_DATE_YEA1_SHIFT |
#define RTC_CALENDAR_TIME_HOU0 | ( | val | ) |
#define RTC_CALENDAR_TIME_HOU0_MASK |
#define RTC_CALENDAR_TIME_HOU0_SHIFT |
#define RTC_CALENDAR_TIME_HOU1 | ( | val | ) |
#define RTC_CALENDAR_TIME_HOU1_MASK |
#define RTC_CALENDAR_TIME_HOU1_SHIFT |
#define RTC_CALENDAR_TIME_MIN0 | ( | val | ) |
#define RTC_CALENDAR_TIME_MIN0_MASK |
#define RTC_CALENDAR_TIME_MIN0_SHIFT |
#define RTC_CALENDAR_TIME_MIN1 | ( | val | ) |
#define RTC_CALENDAR_TIME_MIN1_MASK |
#define RTC_CALENDAR_TIME_MIN1_SHIFT |
#define RTC_CALENDAR_TIME_SEC0 | ( | val | ) |
#define RTC_CALENDAR_TIME_SEC0_MASK |
#define RTC_CALENDAR_TIME_SEC0_SHIFT |
#define RTC_CALENDAR_TIME_SEC1 | ( | val | ) |
#define RTC_CALENDAR_TIME_SEC1_MASK |
#define RTC_CALENDAR_TIME_SEC1_SHIFT |
#define RTC_CCR_OFFSET |
RTC clock control register.
#define RTC_CKIN_DIV1_VAL | ( | val | ) |
#define RTC_CKIN_DIV1_VAL_MASK |
#define RTC_CKIN_DIV1_VAL_SHIFT |
#define RTC_CKREF_CONF_VAL | ( | val | ) |
#define RTC_CKREF_CONF_VAL_MASK |
#define RTC_CKREF_CONF_VAL_SHIFT |
#define RTC_COUNTDOWN1_INIT_VAL | ( | val | ) |
#define RTC_COUNTDOWN1_INIT_VAL_MASK |
#define RTC_COUNTDOWN1_INIT_VAL_SHIFT |
#define RTC_COUNTDOWN1_TIMER_VAL | ( | val | ) |
#define RTC_COUNTDOWN1_TIMER_VAL_MASK |
#define RTC_COUNTDOWN1_TIMER_VAL_SHIFT |
#define RTC_COUNTDOWN_CONTROL_MODE | ( | val | ) |
#define RTC_COUNTDOWN_CONTROL_MODE_MASK |
#define RTC_COUNTDOWN_CONTROL_MODE_SHIFT |
#define RTC_COUNTDOWN_CONTROL_SB | ( | val | ) |
#define RTC_COUNTDOWN_CONTROL_SB_MASK |
#define RTC_COUNTDOWN_CONTROL_SB_SHIFT |
#define RTC_CR_OFFSET |
RTC control register.
#define RTC_ICR_OFFSET |
RTC interrupt control register.
#define RTC_IFR_OFFSET |
RTC interrupt flag register.
#define RTC_IMR_OFFSET |
RTC interrupt mask register.
#define RTC_RTC_CCR_CKOUT_SB | ( | val | ) |
#define RTC_RTC_CCR_CKOUT_SB_MASK |
#define RTC_RTC_CCR_CKOUT_SB_SHIFT |
#define RTC_RTC_CCR_DIV1_AUTOCAL | ( | val | ) |
#define RTC_RTC_CCR_DIV1_AUTOCAL_MASK |
#define RTC_RTC_CCR_DIV1_AUTOCAL_SHIFT |
#define RTC_RTC_CCR_DIV1_COMP | ( | val | ) |
#define RTC_RTC_CCR_DIV1_COMP_MASK |
#define RTC_RTC_CCR_DIV1_COMP_SHIFT |
#define RTC_RTC_CR_CAL_EN | ( | val | ) |
#define RTC_RTC_CR_CAL_EN_MASK |
#define RTC_RTC_CR_CAL_EN_SHIFT |
#define RTC_RTC_CR_SB | ( | val | ) |
#define RTC_RTC_CR_SB_MASK |
#define RTC_RTC_CR_SB_SHIFT |
#define RTC_RTC_CR_SOFT_RST | ( | val | ) |
#define RTC_RTC_CR_SOFT_RST_MASK |
#define RTC_RTC_CR_SOFT_RST_SHIFT |
#define RTC_RTC_ICR_MODE | ( | val | ) |
#define RTC_RTC_ICR_MODE_MASK |
#define RTC_RTC_ICR_MODE_SHIFT |
#define RTC_RTC_IFR_ALARM_FLAG | ( | val | ) |
#define RTC_RTC_IFR_ALARM_FLAG_MASK |
#define RTC_RTC_IFR_ALARM_FLAG_SHIFT |
#define RTC_RTC_IFR_CAL_FLAG | ( | val | ) |
#define RTC_RTC_IFR_CAL_FLAG_MASK |
#define RTC_RTC_IFR_CAL_FLAG_SHIFT |
#define RTC_RTC_IFR_TIMER_FLAG | ( | val | ) |
#define RTC_RTC_IFR_TIMER_FLAG_MASK |
#define RTC_RTC_IFR_TIMER_FLAG_SHIFT |
#define RTC_RTC_IMR_ALARM_MASK | ( | val | ) |
#define RTC_RTC_IMR_ALARM_MASK_MASK |
#define RTC_RTC_IMR_ALARM_MASK_SHIFT |
#define RTC_RTC_IMR_CAL_MASK | ( | val | ) |
#define RTC_RTC_IMR_CAL_MASK_MASK |
#define RTC_RTC_IMR_CAL_MASK_SHIFT |
#define RTC_RTC_IMR_TIMER_MASK | ( | val | ) |
#define RTC_RTC_IMR_TIMER_MASK_MASK |
#define RTC_RTC_IMR_TIMER_MASK_SHIFT |
#define RTC_RTC_SR_IRQ | ( | val | ) |
#define RTC_RTC_SR_IRQ_MASK |
#define RTC_RTC_SR_IRQ_SHIFT |
#define RTC_SR_OFFSET |
RTC Internal Register Offset RTC status register.
#define RTC_TEST_REG_A_OFFSET |
RTC test register.