FreeRTOS port on GAP8/RISC-V
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Macros
gap8/pmsis/include/pmsis/targets/memory_map.h File Reference

Macros

#define FC_TCDM_ADDR
 
#define FC_TCDM_ADDR_ALIAS
 
#define L2_SHARED_ADDR
 
#define ROM_ADDR
 
#define SOC_PERIPHERALS_ADDR
 
#define FLL_ADDR(id)
 
#define GPIO_ADDR
 
#define UDMA_CTRL_ADDR
 
#define APB_SOC_CTRL_ADDR
 
#define ADV_TIMER_ADDR
 
#define SOC_EU_ADDR
 
#define DLC_ADDR
 
#define RTC_ADDR
 
#define EFUSE_ADDR
 
#define UDMA_GC_ADDR
 
#define UDMA_PERIPH_BASE_ADDR
 
#define UDMA_SPIM(id)
 
#define UDMA_HYPER(id)
 
#define UDMA_UART(id)
 
#define UDMA_I2C(id)
 
#define UDMA_DMACPY(id)
 
#define UDMA_I2S(id)
 
#define UDMA_CPI(id)
 
#define ARCHI_CLUSTER_BASE_ADDR
 
#define ARCHI_CLUSTER_GLOBAL_ADDR(cid)
 
#define CL_L1_ADDR
 
#define CL_L1_ADDR_ALIAS
 
#define CL_L1_TS_ADDR
 
#define CL_PERIPHERALS_ADDR
 
#define ARCHI_CL_PERIPHERALS_ADDR
 
#define ARCHI_CL_PERIPHERALS_GLOBAL_ADDR(cid)
 
#define CL_CTRL_ADDR
 
#define CL_GLOB_CTRL_ADDR(cid)
 
#define CL_TIMER_ADDR
 
#define CL_GLOB_EU_CORE_ADDR(cid)
 
#define CL_GLOB_EU_BARRIER_ADDR(cid)
 
#define CL_GLOB_EU_SW_EVENT_ADDR(cid)
 
#define CL_GLOB_EU_SOC_EVENT_ADDR(cid)
 
#define CL_GLOB_EU_DISPATCH_ADDR(cid)
 
#define CL_ICACHE_ADDR
 
#define CL_GLOB_ICACHE_ADDR(cid)
 
#define CL_DMA_ADDR
 
#define CL_DEMUX_EU_CORE_ADDR
 
#define CL_DEMUX_EU_LOOP_ADDR
 
#define CL_DEMUX_EU_DISPATCH_ADDR
 
#define CL_DEMUX_EU_MUTEX_ADDR
 
#define CL_DEMUX_EU_SW_EVENT_ADDR
 
#define CL_DEMUX_EU_BARRIER_ADDR
 
#define CL_DEMUX_DMA_ADDR
 

Macro Definition Documentation

#define ADV_TIMER_ADDR
#define APB_SOC_CTRL_ADDR
#define ARCHI_CL_PERIPHERALS_ADDR
#define ARCHI_CL_PERIPHERALS_GLOBAL_ADDR (   cid)
#define ARCHI_CLUSTER_BASE_ADDR

Cluster.

#define ARCHI_CLUSTER_GLOBAL_ADDR (   cid)
#define CL_CTRL_ADDR
#define CL_DEMUX_DMA_ADDR
#define CL_DEMUX_EU_BARRIER_ADDR
#define CL_DEMUX_EU_CORE_ADDR
#define CL_DEMUX_EU_DISPATCH_ADDR
#define CL_DEMUX_EU_LOOP_ADDR
#define CL_DEMUX_EU_MUTEX_ADDR
#define CL_DEMUX_EU_SW_EVENT_ADDR
#define CL_DMA_ADDR
#define CL_GLOB_CTRL_ADDR (   cid)
#define CL_GLOB_EU_BARRIER_ADDR (   cid)
#define CL_GLOB_EU_CORE_ADDR (   cid)
#define CL_GLOB_EU_DISPATCH_ADDR (   cid)
#define CL_GLOB_EU_SOC_EVENT_ADDR (   cid)
#define CL_GLOB_EU_SW_EVENT_ADDR (   cid)
#define CL_GLOB_ICACHE_ADDR (   cid)
#define CL_ICACHE_ADDR
#define CL_L1_ADDR
#define CL_L1_ADDR_ALIAS
#define CL_L1_TS_ADDR
#define CL_PERIPHERALS_ADDR
#define CL_TIMER_ADDR
#define DLC_ADDR
#define EFUSE_ADDR
#define FC_TCDM_ADDR
#define FC_TCDM_ADDR_ALIAS
#define FLL_ADDR (   id)
#define GPIO_ADDR
#define L2_SHARED_ADDR

Referenced by pi_free().

#define ROM_ADDR
#define RTC_ADDR
#define SOC_EU_ADDR
#define SOC_PERIPHERALS_ADDR
#define UDMA_CPI (   id)
#define UDMA_CTRL_ADDR

Referenced by hal_udma_ctrl_cfg_event_evt0_set(), hal_udma_ctrl_cfg_event_evt1_set(), hal_udma_ctrl_cfg_event_evt2_set(), hal_udma_ctrl_cfg_event_evt3_set(), hal_udma_ctrl_datamove0_cfg_set_ids(), hal_udma_ctrl_datamove0_enable(), hal_udma_ctrl_datamove0_stop(), hal_udma_ctrl_datamove1_cfg_set_ids(), hal_udma_ctrl_datamove1_enable(), hal_udma_ctrl_datamove1_stop(), hal_udma_ctrl_fifo_pop16(), hal_udma_ctrl_fifo_pop24(), hal_udma_ctrl_fifo_pop32(), hal_udma_ctrl_fifo_pop8(), hal_udma_ctrl_fifo_push16(), hal_udma_ctrl_fifo_push24(), hal_udma_ctrl_fifo_push32(), hal_udma_ctrl_fifo_push8(), hal_udma_ctrl_set_pop_fifo(), and hal_udma_ctrl_set_push_fifo().

#define UDMA_DMACPY (   id)
#define UDMA_GC_ADDR
#define UDMA_HYPER (   id)
#define UDMA_I2C (   id)
#define UDMA_I2S (   id)
#define UDMA_PERIPH_BASE_ADDR
#define UDMA_SPIM (   id)
#define UDMA_UART (   id)