fll_regfields.h File Reference

Macros
#define	FLL_FSR_LOCK0_BIT
#define	FLL_FSR_LOCK0_WIDTH
#define	FLL_FSR_LOCK0_MASK
#define	FLL_FSR_LOCK0_RESET
#define	FLL_FSR_CLMP_LO_ERR0_BIT
#define	FLL_FSR_CLMP_LO_ERR0_WIDTH
#define	FLL_FSR_CLMP_LO_ERR0_MASK
#define	FLL_FSR_CLMP_LO_ERR0_RESET
#define	FLL_FSR_CLMP_HI_ERR0_BIT
#define	FLL_FSR_CLMP_HI_ERR0_WIDTH
#define	FLL_FSR_CLMP_HI_ERR0_MASK
#define	FLL_FSR_CLMP_HI_ERR0_RESET
#define	FLL_FSR_FDC_SAT_ERR0_BIT
#define	FLL_FSR_FDC_SAT_ERR0_WIDTH
#define	FLL_FSR_FDC_SAT_ERR0_MASK
#define	FLL_FSR_FDC_SAT_ERR0_RESET
#define	FLL_FSR_LOCK1_BIT
#define	FLL_FSR_LOCK1_WIDTH
#define	FLL_FSR_LOCK1_MASK
#define	FLL_FSR_LOCK1_RESET
#define	FLL_FSR_CLMP_LO_ERR1_BIT
#define	FLL_FSR_CLMP_LO_ERR1_WIDTH
#define	FLL_FSR_CLMP_LO_ERR1_MASK
#define	FLL_FSR_CLMP_LO_ERR1_RESET
#define	FLL_FSR_CLMP_HI_ERR1_BIT
#define	FLL_FSR_CLMP_HI_ERR1_WIDTH
#define	FLL_FSR_CLMP_HI_ERR1_MASK
#define	FLL_FSR_CLMP_HI_ERR1_RESET
#define	FLL_FSR_FDC_SAT_ERR1_BIT
#define	FLL_FSR_FDC_SAT_ERR1_WIDTH
#define	FLL_FSR_FDC_SAT_ERR1_MASK
#define	FLL_FSR_FDC_SAT_ERR1_RESET
#define	FLL_FSR_LOCK2_BIT
#define	FLL_FSR_LOCK2_WIDTH
#define	FLL_FSR_LOCK2_MASK
#define	FLL_FSR_LOCK2_RESET
#define	FLL_FSR_CLMP_LO_ERR2_BIT
#define	FLL_FSR_CLMP_LO_ERR2_WIDTH
#define	FLL_FSR_CLMP_LO_ERR2_MASK
#define	FLL_FSR_CLMP_LO_ERR2_RESET
#define	FLL_FSR_CLMP_HI_ERR2_BIT
#define	FLL_FSR_CLMP_HI_ERR2_WIDTH
#define	FLL_FSR_CLMP_HI_ERR2_MASK
#define	FLL_FSR_CLMP_HI_ERR2_RESET
#define	FLL_FSR_FDC_SAT_ERR2_BIT
#define	FLL_FSR_FDC_SAT_ERR2_WIDTH
#define	FLL_FSR_FDC_SAT_ERR2_MASK
#define	FLL_FSR_FDC_SAT_ERR2_RESET
#define	FLL_FSR_LOCK3_BIT
#define	FLL_FSR_LOCK3_WIDTH
#define	FLL_FSR_LOCK3_MASK
#define	FLL_FSR_LOCK3_RESET
#define	FLL_FSR_CLMP_LO_ERR3_BIT
#define	FLL_FSR_CLMP_LO_ERR3_WIDTH
#define	FLL_FSR_CLMP_LO_ERR3_MASK
#define	FLL_FSR_CLMP_LO_ERR3_RESET
#define	FLL_FSR_CLMP_HI_ERR3_BIT
#define	FLL_FSR_CLMP_HI_ERR3_WIDTH
#define	FLL_FSR_CLMP_HI_ERR3_MASK
#define	FLL_FSR_CLMP_HI_ERR3_RESET
#define	FLL_FSR_FDC_SAT_ERR3_BIT
#define	FLL_FSR_FDC_SAT_ERR3_WIDTH
#define	FLL_FSR_FDC_SAT_ERR3_MASK
#define	FLL_FSR_FDC_SAT_ERR3_RESET
#define	FLL_DRR_DCO_MIN_BIT
#define	FLL_DRR_DCO_MIN_WIDTH
#define	FLL_DRR_DCO_MIN_MASK
#define	FLL_DRR_DCO_MIN_RESET
#define	FLL_DRR_DCO_MAX_BIT
#define	FLL_DRR_DCO_MAX_WIDTH
#define	FLL_DRR_DCO_MAX_MASK
#define	FLL_DRR_DCO_MAX_RESET
#define	FLL_TTR_REFRESH_BIT
#define	FLL_TTR_REFRESH_WIDTH
#define	FLL_TTR_REFRESH_MASK
#define	FLL_TTR_REFRESH_RESET
#define	FLL_F0CR1_DCO_EN_BIT
#define	FLL_F0CR1_DCO_EN_WIDTH
#define	FLL_F0CR1_DCO_EN_MASK
#define	FLL_F0CR1_OP_MODE_BIT
#define	FLL_F0CR1_OP_MODE_WIDTH
#define	FLL_F0CR1_OP_MODE_MASK
#define	FLL_F0CR1_TTM_EN_BIT
#define	FLL_F0CR1_TTM_EN_WIDTH
#define	FLL_F0CR1_TTM_EN_MASK
#define	FLL_F0CR1_LOOP_GAIN_BIT
#define	FLL_F0CR1_LOOP_GAIN_WIDTH
#define	FLL_F0CR1_LOOP_GAIN_MASK
#define	FLL_F0CR1_LOCK_TOL_BIT
#define	FLL_F0CR1_LOCK_TOL_WIDTH
#define	FLL_F0CR1_LOCK_TOL_MASK
#define	FLL_F0CR1_ITG_PER_BIT
#define	FLL_F0CR1_ITG_PER_WIDTH
#define	FLL_F0CR1_ITG_PER_MASK
#define	FLL_F0CR1_STBL_BIT
#define	FLL_F0CR1_STBL_WIDTH
#define	FLL_F0CR1_STBL_MASK
#define	FLL_F0CR2_MFI_BIT
#define	FLL_F0CR2_MFI_WIDTH
#define	FLL_F0CR2_MFI_MASK
#define	FLL_F0CR2_DCO_CODE_BIT
#define	FLL_F0CR2_DCO_CODE_WIDTH
#define	FLL_F0CR2_DCO_CODE_MASK
#define	FLL_F1CR1_DCO_EN_BIT
#define	FLL_F1CR1_DCO_EN_WIDTH
#define	FLL_F1CR1_DCO_EN_MASK
#define	FLL_F1CR1_OP_MODE_BIT
#define	FLL_F1CR1_OP_MODE_WIDTH
#define	FLL_F1CR1_OP_MODE_MASK
#define	FLL_F1CR1_TTM_EN_BIT
#define	FLL_F1CR1_TTM_EN_WIDTH
#define	FLL_F1CR1_TTM_EN_MASK
#define	FLL_F1CR1_LOOP_GAIN_BIT
#define	FLL_F1CR1_LOOP_GAIN_WIDTH
#define	FLL_F1CR1_LOOP_GAIN_MASK
#define	FLL_F1CR1_LOCK_TOL_BIT
#define	FLL_F1CR1_LOCK_TOL_WIDTH
#define	FLL_F1CR1_LOCK_TOL_MASK
#define	FLL_F1CR1_ITG_PER_BIT
#define	FLL_F1CR1_ITG_PER_WIDTH
#define	FLL_F1CR1_ITG_PER_MASK
#define	FLL_F1CR1_STBL_BIT
#define	FLL_F1CR1_STBL_WIDTH
#define	FLL_F1CR1_STBL_MASK
#define	FLL_F1CR2_MFI_BIT
#define	FLL_F1CR2_MFI_WIDTH
#define	FLL_F1CR2_MFI_MASK
#define	FLL_F1CR2_DCO_CODE_BIT
#define	FLL_F1CR2_DCO_CODE_WIDTH
#define	FLL_F1CR2_DCO_CODE_MASK
#define	FLL_F2CR1_DCO_EN_BIT
#define	FLL_F2CR1_DCO_EN_WIDTH
#define	FLL_F2CR1_DCO_EN_MASK
#define	FLL_F2CR1_OP_MODE_BIT
#define	FLL_F2CR1_OP_MODE_WIDTH
#define	FLL_F2CR1_OP_MODE_MASK
#define	FLL_F2CR1_TTM_EN_BIT
#define	FLL_F2CR1_TTM_EN_WIDTH
#define	FLL_F2CR1_TTM_EN_MASK
#define	FLL_F2CR1_LOOP_GAIN_BIT
#define	FLL_F2CR1_LOOP_GAIN_WIDTH
#define	FLL_F2CR1_LOOP_GAIN_MASK
#define	FLL_F2CR1_LOCK_TOL_BIT
#define	FLL_F2CR1_LOCK_TOL_WIDTH
#define	FLL_F2CR1_LOCK_TOL_MASK
#define	FLL_F2CR1_ITG_PER_BIT
#define	FLL_F2CR1_ITG_PER_WIDTH
#define	FLL_F2CR1_ITG_PER_MASK
#define	FLL_F2CR1_STBL_BIT
#define	FLL_F2CR1_STBL_WIDTH
#define	FLL_F2CR1_STBL_MASK
#define	FLL_F2CR2_MFI_BIT
#define	FLL_F2CR2_MFI_WIDTH
#define	FLL_F2CR2_MFI_MASK
#define	FLL_F2CR2_DCO_CODE_BIT
#define	FLL_F2CR2_DCO_CODE_WIDTH
#define	FLL_F2CR2_DCO_CODE_MASK
#define	FLL_F3CR1_DCO_EN_BIT
#define	FLL_F3CR1_DCO_EN_WIDTH
#define	FLL_F3CR1_DCO_EN_MASK
#define	FLL_F3CR1_OP_MODE_BIT
#define	FLL_F3CR1_OP_MODE_WIDTH
#define	FLL_F3CR1_OP_MODE_MASK
#define	FLL_F3CR1_TTM_EN_BIT
#define	FLL_F3CR1_TTM_EN_WIDTH
#define	FLL_F3CR1_TTM_EN_MASK
#define	FLL_F3CR1_LOOP_GAIN_BIT
#define	FLL_F3CR1_LOOP_GAIN_WIDTH
#define	FLL_F3CR1_LOOP_GAIN_MASK
#define	FLL_F3CR1_LOCK_TOL_BIT
#define	FLL_F3CR1_LOCK_TOL_WIDTH
#define	FLL_F3CR1_LOCK_TOL_MASK
#define	FLL_F3CR1_ITG_PER_BIT
#define	FLL_F3CR1_ITG_PER_WIDTH
#define	FLL_F3CR1_ITG_PER_MASK
#define	FLL_F3CR1_STBL_BIT
#define	FLL_F3CR1_STBL_WIDTH
#define	FLL_F3CR1_STBL_MASK
#define	FLL_F3CR2_MFI_BIT
#define	FLL_F3CR2_MFI_WIDTH
#define	FLL_F3CR2_MFI_MASK
#define	FLL_F3CR2_DCO_CODE_BIT
#define	FLL_F3CR2_DCO_CODE_WIDTH
#define	FLL_F3CR2_DCO_CODE_MASK
#define	FLL_CCR1_CLK0_DIV_BIT
#define	FLL_CCR1_CLK0_DIV_WIDTH
#define	FLL_CCR1_CLK0_DIV_MASK
#define	FLL_CCR1_CLK1_DIV_BIT
#define	FLL_CCR1_CLK1_DIV_WIDTH
#define	FLL_CCR1_CLK1_DIV_MASK
#define	FLL_CCR1_CLK2_DIV_BIT
#define	FLL_CCR1_CLK2_DIV_WIDTH
#define	FLL_CCR1_CLK2_DIV_MASK
#define	FLL_CCR1_CLK3_DIV_BIT
#define	FLL_CCR1_CLK3_DIV_WIDTH
#define	FLL_CCR1_CLK3_DIV_MASK
#define	FLL_CCR2_CLK0_SEL_BIT
#define	FLL_CCR2_CLK0_SEL_WIDTH
#define	FLL_CCR2_CLK0_SEL_MASK
#define	FLL_CCR2_CLK1_SEL_BIT
#define	FLL_CCR2_CLK1_SEL_WIDTH
#define	FLL_CCR2_CLK1_SEL_MASK
#define	FLL_CCR2_CLK2_SEL_BIT
#define	FLL_CCR2_CLK2_SEL_WIDTH
#define	FLL_CCR2_CLK2_SEL_MASK
#define	FLL_CCR2_CLK3_SEL_BIT
#define	FLL_CCR2_CLK3_SEL_WIDTH
#define	FLL_CCR2_CLK3_SEL_MASK
#define	FLL_CCR2_CKG0_BIT
#define	FLL_CCR2_CKG0_WIDTH
#define	FLL_CCR2_CKG0_MASK
#define	FLL_CCR2_CKG1_BIT
#define	FLL_CCR2_CKG1_WIDTH
#define	FLL_CCR2_CKG1_MASK
#define	FLL_CCR2_CKG2_BIT
#define	FLL_CCR2_CKG2_WIDTH
#define	FLL_CCR2_CKG2_MASK
#define	FLL_CCR2_CKG3_BIT
#define	FLL_CCR2_CKG3_WIDTH
#define	FLL_CCR2_CKG3_MASK

Macro Definition Documentation

#define FLL_CCR1_CLK0_DIV_BIT

#define FLL_CCR1_CLK0_DIV_MASK

Referenced by hal_fll_clock_div_get(), and hal_fll_clock_div_set().

#define FLL_CCR1_CLK0_DIV_WIDTH

#define FLL_CCR1_CLK1_DIV_BIT

#define FLL_CCR1_CLK1_DIV_MASK

#define FLL_CCR1_CLK1_DIV_WIDTH

#define FLL_CCR1_CLK2_DIV_BIT

#define FLL_CCR1_CLK2_DIV_MASK

#define FLL_CCR1_CLK2_DIV_WIDTH

#define FLL_CCR1_CLK3_DIV_BIT

#define FLL_CCR1_CLK3_DIV_MASK

#define FLL_CCR1_CLK3_DIV_WIDTH

#define FLL_CCR2_CKG0_BIT

#define FLL_CCR2_CKG0_MASK

#define FLL_CCR2_CKG0_WIDTH

#define FLL_CCR2_CKG1_BIT

#define FLL_CCR2_CKG1_MASK

#define FLL_CCR2_CKG1_WIDTH

#define FLL_CCR2_CKG2_BIT

#define FLL_CCR2_CKG2_MASK

#define FLL_CCR2_CKG2_WIDTH

#define FLL_CCR2_CKG3_BIT

#define FLL_CCR2_CKG3_MASK

#define FLL_CCR2_CKG3_WIDTH

#define FLL_CCR2_CLK0_SEL_BIT

#define FLL_CCR2_CLK0_SEL_MASK

#define FLL_CCR2_CLK0_SEL_WIDTH

#define FLL_CCR2_CLK1_SEL_BIT

#define FLL_CCR2_CLK1_SEL_MASK

#define FLL_CCR2_CLK1_SEL_WIDTH

#define FLL_CCR2_CLK2_SEL_BIT

#define FLL_CCR2_CLK2_SEL_MASK

#define FLL_CCR2_CLK2_SEL_WIDTH

#define FLL_CCR2_CLK3_SEL_BIT

#define FLL_CCR2_CLK3_SEL_MASK

#define FLL_CCR2_CLK3_SEL_WIDTH

#define FLL_DRR_DCO_MAX_BIT

#define FLL_DRR_DCO_MAX_MASK

#define FLL_DRR_DCO_MAX_RESET

#define FLL_DRR_DCO_MAX_WIDTH

#define FLL_DRR_DCO_MIN_BIT

#define FLL_DRR_DCO_MIN_MASK

#define FLL_DRR_DCO_MIN_RESET

#define FLL_DRR_DCO_MIN_WIDTH

#define FLL_F0CR1_DCO_EN_BIT

#define FLL_F0CR1_DCO_EN_MASK

#define FLL_F0CR1_DCO_EN_WIDTH

#define FLL_F0CR1_ITG_PER_BIT

#define FLL_F0CR1_ITG_PER_MASK

#define FLL_F0CR1_ITG_PER_WIDTH

#define FLL_F0CR1_LOCK_TOL_BIT

#define FLL_F0CR1_LOCK_TOL_MASK

#define FLL_F0CR1_LOCK_TOL_WIDTH

#define FLL_F0CR1_LOOP_GAIN_BIT

#define FLL_F0CR1_LOOP_GAIN_MASK

#define FLL_F0CR1_LOOP_GAIN_WIDTH

#define FLL_F0CR1_OP_MODE_BIT

#define FLL_F0CR1_OP_MODE_MASK

#define FLL_F0CR1_OP_MODE_WIDTH

#define FLL_F0CR1_STBL_BIT

#define FLL_F0CR1_STBL_MASK

#define FLL_F0CR1_STBL_WIDTH

#define FLL_F0CR1_TTM_EN_BIT

#define FLL_F0CR1_TTM_EN_MASK

#define FLL_F0CR1_TTM_EN_WIDTH

#define FLL_F0CR2_DCO_CODE_BIT

#define FLL_F0CR2_DCO_CODE_MASK

#define FLL_F0CR2_DCO_CODE_WIDTH

#define FLL_F0CR2_MFI_BIT

#define FLL_F0CR2_MFI_MASK

#define FLL_F0CR2_MFI_WIDTH

#define FLL_F1CR1_DCO_EN_BIT

#define FLL_F1CR1_DCO_EN_MASK

#define FLL_F1CR1_DCO_EN_WIDTH

#define FLL_F1CR1_ITG_PER_BIT

#define FLL_F1CR1_ITG_PER_MASK

#define FLL_F1CR1_ITG_PER_WIDTH

#define FLL_F1CR1_LOCK_TOL_BIT

#define FLL_F1CR1_LOCK_TOL_MASK

#define FLL_F1CR1_LOCK_TOL_WIDTH

#define FLL_F1CR1_LOOP_GAIN_BIT

#define FLL_F1CR1_LOOP_GAIN_MASK

#define FLL_F1CR1_LOOP_GAIN_WIDTH

#define FLL_F1CR1_OP_MODE_BIT

#define FLL_F1CR1_OP_MODE_MASK

#define FLL_F1CR1_OP_MODE_WIDTH

#define FLL_F1CR1_STBL_BIT

#define FLL_F1CR1_STBL_MASK

#define FLL_F1CR1_STBL_WIDTH

#define FLL_F1CR1_TTM_EN_BIT

#define FLL_F1CR1_TTM_EN_MASK

#define FLL_F1CR1_TTM_EN_WIDTH

#define FLL_F1CR2_DCO_CODE_BIT

#define FLL_F1CR2_DCO_CODE_MASK

#define FLL_F1CR2_DCO_CODE_WIDTH

#define FLL_F1CR2_MFI_BIT

#define FLL_F1CR2_MFI_MASK

#define FLL_F1CR2_MFI_WIDTH

#define FLL_F2CR1_DCO_EN_BIT

#define FLL_F2CR1_DCO_EN_MASK

#define FLL_F2CR1_DCO_EN_WIDTH

#define FLL_F2CR1_ITG_PER_BIT

#define FLL_F2CR1_ITG_PER_MASK

#define FLL_F2CR1_ITG_PER_WIDTH

#define FLL_F2CR1_LOCK_TOL_BIT

#define FLL_F2CR1_LOCK_TOL_MASK

#define FLL_F2CR1_LOCK_TOL_WIDTH

#define FLL_F2CR1_LOOP_GAIN_BIT

#define FLL_F2CR1_LOOP_GAIN_MASK

#define FLL_F2CR1_LOOP_GAIN_WIDTH

#define FLL_F2CR1_OP_MODE_BIT

#define FLL_F2CR1_OP_MODE_MASK

#define FLL_F2CR1_OP_MODE_WIDTH

#define FLL_F2CR1_STBL_BIT

#define FLL_F2CR1_STBL_MASK

#define FLL_F2CR1_STBL_WIDTH

#define FLL_F2CR1_TTM_EN_BIT

#define FLL_F2CR1_TTM_EN_MASK

#define FLL_F2CR1_TTM_EN_WIDTH

#define FLL_F2CR2_DCO_CODE_BIT

#define FLL_F2CR2_DCO_CODE_MASK

#define FLL_F2CR2_DCO_CODE_WIDTH

#define FLL_F2CR2_MFI_BIT

#define FLL_F2CR2_MFI_MASK

#define FLL_F2CR2_MFI_WIDTH

#define FLL_F3CR1_DCO_EN_BIT

#define FLL_F3CR1_DCO_EN_MASK

#define FLL_F3CR1_DCO_EN_WIDTH

#define FLL_F3CR1_ITG_PER_BIT

#define FLL_F3CR1_ITG_PER_MASK

#define FLL_F3CR1_ITG_PER_WIDTH

#define FLL_F3CR1_LOCK_TOL_BIT

#define FLL_F3CR1_LOCK_TOL_MASK

#define FLL_F3CR1_LOCK_TOL_WIDTH

#define FLL_F3CR1_LOOP_GAIN_BIT

#define FLL_F3CR1_LOOP_GAIN_MASK

#define FLL_F3CR1_LOOP_GAIN_WIDTH

#define FLL_F3CR1_OP_MODE_BIT

#define FLL_F3CR1_OP_MODE_MASK

#define FLL_F3CR1_OP_MODE_WIDTH

#define FLL_F3CR1_STBL_BIT

#define FLL_F3CR1_STBL_MASK

#define FLL_F3CR1_STBL_WIDTH

#define FLL_F3CR1_TTM_EN_BIT

#define FLL_F3CR1_TTM_EN_MASK

#define FLL_F3CR1_TTM_EN_WIDTH

#define FLL_F3CR2_DCO_CODE_BIT

#define FLL_F3CR2_DCO_CODE_MASK

#define FLL_F3CR2_DCO_CODE_WIDTH

#define FLL_F3CR2_MFI_BIT

#define FLL_F3CR2_MFI_MASK

#define FLL_F3CR2_MFI_WIDTH

#define FLL_FSR_CLMP_HI_ERR0_BIT

#define FLL_FSR_CLMP_HI_ERR0_MASK

Referenced by hal_fll_status_get().

#define FLL_FSR_CLMP_HI_ERR0_RESET

#define FLL_FSR_CLMP_HI_ERR0_WIDTH

#define FLL_FSR_CLMP_HI_ERR1_BIT

#define FLL_FSR_CLMP_HI_ERR1_MASK

#define FLL_FSR_CLMP_HI_ERR1_RESET

#define FLL_FSR_CLMP_HI_ERR1_WIDTH

#define FLL_FSR_CLMP_HI_ERR2_BIT

#define FLL_FSR_CLMP_HI_ERR2_MASK

#define FLL_FSR_CLMP_HI_ERR2_RESET

#define FLL_FSR_CLMP_HI_ERR2_WIDTH

#define FLL_FSR_CLMP_HI_ERR3_BIT

#define FLL_FSR_CLMP_HI_ERR3_MASK

#define FLL_FSR_CLMP_HI_ERR3_RESET

#define FLL_FSR_CLMP_HI_ERR3_WIDTH

#define FLL_FSR_CLMP_LO_ERR0_BIT

#define FLL_FSR_CLMP_LO_ERR0_MASK

Referenced by hal_fll_status_get().

#define FLL_FSR_CLMP_LO_ERR0_RESET

#define FLL_FSR_CLMP_LO_ERR0_WIDTH

#define FLL_FSR_CLMP_LO_ERR1_BIT

#define FLL_FSR_CLMP_LO_ERR1_MASK

#define FLL_FSR_CLMP_LO_ERR1_RESET

#define FLL_FSR_CLMP_LO_ERR1_WIDTH

#define FLL_FSR_CLMP_LO_ERR2_BIT

#define FLL_FSR_CLMP_LO_ERR2_MASK

#define FLL_FSR_CLMP_LO_ERR2_RESET

#define FLL_FSR_CLMP_LO_ERR2_WIDTH

#define FLL_FSR_CLMP_LO_ERR3_BIT

#define FLL_FSR_CLMP_LO_ERR3_MASK

#define FLL_FSR_CLMP_LO_ERR3_RESET

#define FLL_FSR_CLMP_LO_ERR3_WIDTH

#define FLL_FSR_FDC_SAT_ERR0_BIT

#define FLL_FSR_FDC_SAT_ERR0_MASK

Referenced by hal_fll_status_get().

#define FLL_FSR_FDC_SAT_ERR0_RESET

#define FLL_FSR_FDC_SAT_ERR0_WIDTH

#define FLL_FSR_FDC_SAT_ERR1_BIT

#define FLL_FSR_FDC_SAT_ERR1_MASK

#define FLL_FSR_FDC_SAT_ERR1_RESET

#define FLL_FSR_FDC_SAT_ERR1_WIDTH

#define FLL_FSR_FDC_SAT_ERR2_BIT

#define FLL_FSR_FDC_SAT_ERR2_MASK

#define FLL_FSR_FDC_SAT_ERR2_RESET

#define FLL_FSR_FDC_SAT_ERR2_WIDTH

#define FLL_FSR_FDC_SAT_ERR3_BIT

#define FLL_FSR_FDC_SAT_ERR3_MASK

#define FLL_FSR_FDC_SAT_ERR3_RESET

#define FLL_FSR_FDC_SAT_ERR3_WIDTH

#define FLL_FSR_LOCK0_BIT

#define FLL_FSR_LOCK0_MASK

Referenced by hal_fll_status_get().

#define FLL_FSR_LOCK0_RESET

#define FLL_FSR_LOCK0_WIDTH

#define FLL_FSR_LOCK1_BIT

#define FLL_FSR_LOCK1_MASK

#define FLL_FSR_LOCK1_RESET

#define FLL_FSR_LOCK1_WIDTH

#define FLL_FSR_LOCK2_BIT

#define FLL_FSR_LOCK2_MASK

#define FLL_FSR_LOCK2_RESET

#define FLL_FSR_LOCK2_WIDTH

#define FLL_FSR_LOCK3_BIT

#define FLL_FSR_LOCK3_MASK

#define FLL_FSR_LOCK3_RESET

#define FLL_FSR_LOCK3_WIDTH

#define FLL_TTR_REFRESH_BIT

#define FLL_TTR_REFRESH_MASK

#define FLL_TTR_REFRESH_RESET

#define FLL_TTR_REFRESH_WIDTH