FreeRTOS port on GAP8/RISC-V
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#define FC_MPU_APB_RULE0_A_BIT |
#define FC_MPU_APB_RULE0_A_MASK |
#define FC_MPU_APB_RULE0_A_WIDTH |
#define FC_MPU_APB_RULE0_BASE_BIT |
#define FC_MPU_APB_RULE0_BASE_MASK |
#define FC_MPU_APB_RULE0_BASE_WIDTH |
#define FC_MPU_APB_RULE0_SIZE_BIT |
#define FC_MPU_APB_RULE0_SIZE_MASK |
#define FC_MPU_APB_RULE0_SIZE_WIDTH |
#define FC_MPU_APB_RULE0_ST_BIT |
#define FC_MPU_APB_RULE0_ST_MASK |
#define FC_MPU_APB_RULE0_ST_WIDTH |
#define FC_MPU_FC_TCDM_RULE0_A_BIT |
#define FC_MPU_FC_TCDM_RULE0_A_MASK |
#define FC_MPU_FC_TCDM_RULE0_A_WIDTH |
#define FC_MPU_FC_TCDM_RULE0_BASE_BIT |
#define FC_MPU_FC_TCDM_RULE0_BASE_MASK |
#define FC_MPU_FC_TCDM_RULE0_BASE_WIDTH |
#define FC_MPU_FC_TCDM_RULE0_SIZE_BIT |
#define FC_MPU_FC_TCDM_RULE0_SIZE_MASK |
#define FC_MPU_FC_TCDM_RULE0_SIZE_WIDTH |
#define FC_MPU_FC_TCDM_RULE0_ST_BIT |
#define FC_MPU_FC_TCDM_RULE0_ST_MASK |
#define FC_MPU_FC_TCDM_RULE0_ST_WIDTH |
#define FC_MPU_L2_RULE0_A_BIT |
#define FC_MPU_L2_RULE0_A_MASK |
#define FC_MPU_L2_RULE0_A_WIDTH |
#define FC_MPU_L2_RULE0_BASE_BIT |
#define FC_MPU_L2_RULE0_BASE_MASK |
#define FC_MPU_L2_RULE0_BASE_WIDTH |
#define FC_MPU_L2_RULE0_SIZE_BIT |
#define FC_MPU_L2_RULE0_SIZE_MASK |
#define FC_MPU_L2_RULE0_SIZE_WIDTH |
#define FC_MPU_L2_RULE0_ST_BIT |
#define FC_MPU_L2_RULE0_ST_MASK |
#define FC_MPU_L2_RULE0_ST_WIDTH |
#define FC_MPU_MPU_ENABLE_ENABLE_BIT |
#define FC_MPU_MPU_ENABLE_ENABLE_MASK |
#define FC_MPU_MPU_ENABLE_ENABLE_WIDTH |