FreeRTOS port on GAP8/RISC-V
|
Macros | |
#define | FC_ICACHE_CTRL_ENABLE_EN_BIT |
#define | FC_ICACHE_CTRL_ENABLE_EN_WIDTH |
#define | FC_ICACHE_CTRL_ENABLE_EN_MASK |
#define | FC_ICACHE_CTRL_ENABLE_EN_RESET |
#define | FC_ICACHE_CTRL_FLUSH_FL_BIT |
#define | FC_ICACHE_CTRL_FLUSH_FL_WIDTH |
#define | FC_ICACHE_CTRL_FLUSH_FL_MASK |
#define | FC_ICACHE_CTRL_FLUSH_FL_RESET |
#define | FC_ICACHE_CTRL_SEL_FLUSH_ADDR_BIT |
#define | FC_ICACHE_CTRL_SEL_FLUSH_ADDR_WIDTH |
#define | FC_ICACHE_CTRL_SEL_FLUSH_ADDR_MASK |
#define | FC_ICACHE_CTRL_SEL_FLUSH_ADDR_RESET |
#define | FC_ICACHE_CTRL_STATUS_STATUS_BIT |
#define | FC_ICACHE_CTRL_STATUS_STATUS_WIDTH |
#define | FC_ICACHE_CTRL_STATUS_STATUS_MASK |
#define | FC_ICACHE_CTRL_STATUS_STATUS_RESET |
#define FC_ICACHE_CTRL_ENABLE_EN_BIT |
#define FC_ICACHE_CTRL_ENABLE_EN_MASK |
#define FC_ICACHE_CTRL_ENABLE_EN_RESET |
#define FC_ICACHE_CTRL_ENABLE_EN_WIDTH |
#define FC_ICACHE_CTRL_FLUSH_FL_BIT |
#define FC_ICACHE_CTRL_FLUSH_FL_MASK |
#define FC_ICACHE_CTRL_FLUSH_FL_RESET |
#define FC_ICACHE_CTRL_FLUSH_FL_WIDTH |
#define FC_ICACHE_CTRL_SEL_FLUSH_ADDR_BIT |
#define FC_ICACHE_CTRL_SEL_FLUSH_ADDR_MASK |
#define FC_ICACHE_CTRL_SEL_FLUSH_ADDR_RESET |
#define FC_ICACHE_CTRL_SEL_FLUSH_ADDR_WIDTH |
#define FC_ICACHE_CTRL_STATUS_STATUS_BIT |
#define FC_ICACHE_CTRL_STATUS_STATUS_MASK |
#define FC_ICACHE_CTRL_STATUS_STATUS_RESET |
#define FC_ICACHE_CTRL_STATUS_STATUS_WIDTH |