cluster_icache_ctrl_regfields.h File Reference

Macros
#define	CLUSTER_ICACHE_CTRL_ENABLE_EN_PRI_BIT
#define	CLUSTER_ICACHE_CTRL_ENABLE_EN_PRI_WIDTH
#define	CLUSTER_ICACHE_CTRL_ENABLE_EN_PRI_MASK
#define	CLUSTER_ICACHE_CTRL_ENABLE_EN_PRI_RESET
#define	CLUSTER_ICACHE_CTRL_ENABLE_EN_SH_BIT
#define	CLUSTER_ICACHE_CTRL_ENABLE_EN_SH_WIDTH
#define	CLUSTER_ICACHE_CTRL_ENABLE_EN_SH_MASK
#define	CLUSTER_ICACHE_CTRL_ENABLE_EN_SH_RESET
#define	CLUSTER_ICACHE_CTRL_FLUSH_FL_PRI_BIT
#define	CLUSTER_ICACHE_CTRL_FLUSH_FL_PRI_WIDTH
#define	CLUSTER_ICACHE_CTRL_FLUSH_FL_PRI_MASK
#define	CLUSTER_ICACHE_CTRL_FLUSH_FL_PRI_RESET
#define	CLUSTER_ICACHE_CTRL_FLUSH_FL_SH_BIT
#define	CLUSTER_ICACHE_CTRL_FLUSH_FL_SH_WIDTH
#define	CLUSTER_ICACHE_CTRL_FLUSH_FL_SH_MASK
#define	CLUSTER_ICACHE_CTRL_FLUSH_FL_SH_RESET
#define	CLUSTER_ICACHE_CTRL_L0_FLUSH_L0_FL_BIT
#define	CLUSTER_ICACHE_CTRL_L0_FLUSH_L0_FL_WIDTH
#define	CLUSTER_ICACHE_CTRL_L0_FLUSH_L0_FL_MASK
#define	CLUSTER_ICACHE_CTRL_L0_FLUSH_L0_FL_RESET
#define	CLUSTER_ICACHE_CTRL_SEL_FLUSH_ADDR_BIT
#define	CLUSTER_ICACHE_CTRL_SEL_FLUSH_ADDR_WIDTH
#define	CLUSTER_ICACHE_CTRL_SEL_FLUSH_ADDR_MASK
#define	CLUSTER_ICACHE_CTRL_SEL_FLUSH_ADDR_RESET
#define	CLUSTER_ICACHE_CTRL_ENABLE_SPECIAL_CORE_CACHE_ENABLE_BIT
#define	CLUSTER_ICACHE_CTRL_ENABLE_SPECIAL_CORE_CACHE_ENABLE_WIDTH
#define	CLUSTER_ICACHE_CTRL_ENABLE_SPECIAL_CORE_CACHE_ENABLE_MASK
#define	CLUSTER_ICACHE_CTRL_ENABLE_SPECIAL_CORE_CACHE_ENABLE_RESET
#define	CLUSTER_ICACHE_CTRL_ENABLE_L1_L15_PREFETCH_ENABLE_BIT
#define	CLUSTER_ICACHE_CTRL_ENABLE_L1_L15_PREFETCH_ENABLE_WIDTH
#define	CLUSTER_ICACHE_CTRL_ENABLE_L1_L15_PREFETCH_ENABLE_MASK
#define	CLUSTER_ICACHE_CTRL_ENABLE_L1_L15_PREFETCH_ENABLE_RESET

Macro Definition Documentation

#define CLUSTER_ICACHE_CTRL_ENABLE_EN_PRI_BIT

#define CLUSTER_ICACHE_CTRL_ENABLE_EN_PRI_MASK

#define CLUSTER_ICACHE_CTRL_ENABLE_EN_PRI_RESET

#define CLUSTER_ICACHE_CTRL_ENABLE_EN_PRI_WIDTH

#define CLUSTER_ICACHE_CTRL_ENABLE_EN_SH_BIT

#define CLUSTER_ICACHE_CTRL_ENABLE_EN_SH_MASK

#define CLUSTER_ICACHE_CTRL_ENABLE_EN_SH_RESET

#define CLUSTER_ICACHE_CTRL_ENABLE_EN_SH_WIDTH

#define CLUSTER_ICACHE_CTRL_ENABLE_L1_L15_PREFETCH_ENABLE_BIT

#define CLUSTER_ICACHE_CTRL_ENABLE_L1_L15_PREFETCH_ENABLE_MASK

#define CLUSTER_ICACHE_CTRL_ENABLE_L1_L15_PREFETCH_ENABLE_RESET

#define CLUSTER_ICACHE_CTRL_ENABLE_L1_L15_PREFETCH_ENABLE_WIDTH

#define CLUSTER_ICACHE_CTRL_ENABLE_SPECIAL_CORE_CACHE_ENABLE_BIT

#define CLUSTER_ICACHE_CTRL_ENABLE_SPECIAL_CORE_CACHE_ENABLE_MASK

#define CLUSTER_ICACHE_CTRL_ENABLE_SPECIAL_CORE_CACHE_ENABLE_RESET

#define CLUSTER_ICACHE_CTRL_ENABLE_SPECIAL_CORE_CACHE_ENABLE_WIDTH

#define CLUSTER_ICACHE_CTRL_FLUSH_FL_PRI_BIT

#define CLUSTER_ICACHE_CTRL_FLUSH_FL_PRI_MASK

#define CLUSTER_ICACHE_CTRL_FLUSH_FL_PRI_RESET

#define CLUSTER_ICACHE_CTRL_FLUSH_FL_PRI_WIDTH

#define CLUSTER_ICACHE_CTRL_FLUSH_FL_SH_BIT

#define CLUSTER_ICACHE_CTRL_FLUSH_FL_SH_MASK

#define CLUSTER_ICACHE_CTRL_FLUSH_FL_SH_RESET

#define CLUSTER_ICACHE_CTRL_FLUSH_FL_SH_WIDTH

#define CLUSTER_ICACHE_CTRL_L0_FLUSH_L0_FL_BIT

#define CLUSTER_ICACHE_CTRL_L0_FLUSH_L0_FL_MASK

#define CLUSTER_ICACHE_CTRL_L0_FLUSH_L0_FL_RESET

#define CLUSTER_ICACHE_CTRL_L0_FLUSH_L0_FL_WIDTH

#define CLUSTER_ICACHE_CTRL_SEL_FLUSH_ADDR_BIT

#define CLUSTER_ICACHE_CTRL_SEL_FLUSH_ADDR_MASK

#define CLUSTER_ICACHE_CTRL_SEL_FLUSH_ADDR_RESET

#define CLUSTER_ICACHE_CTRL_SEL_FLUSH_ADDR_WIDTH