FLL Control and Configuration

GAP9 is equipped with a quadruple FLL, which is used for generating clocks for the SoC, Cluster, SFU and Periph Domains. It can generate the clock in open-loop mode or based on REF FAST clock (close-loop mode).

For more details about FLL, please read the section 4.2.4 FLL in datasheet.

Boot in Open Loop Mode

If the REF FAST Clock is not presented, we can boot the chip in Open Loop Mode. To enable this mode in boot, you just need to add this in your Makefile:

APP_CFLAGS += -DCONFIG_OPEN_LOOP_BOOT

Open/Close Loop Mode Swich

By using the following API, you could switch the FLL mode between open loop and close loop:

// Pass all the DCO to open loop
pi_fll_ioctl(PI_FREQ_DOMAIN_ALL, PI_FLL_IOCTL_FULL_DCO_OPEN_LOOP_SET, 0);

// Pass all the DCO to close loop
pi_fll_ioctl(PI_FREQ_DOMAIN_ALL, PI_FLL_IOCTL_FULL_DCO_CLOSE_LOOP_SET, 0);

Warning

When the DCOs are running in open loop mode, some features based on the REF FAST Clock may need to change the clock source as well. For example, the Timers. All the timers used by the runtime (system tick and high precision timer) should be re-configured accordingly.

if (op_mode) // From close loop, going into open loop
{
    printf("Pass to open loop\n");
    pi_timer_ioctl(NULL, PI_TIMER_IOCTL_SYS_TIMER_SRC_SET, (void *) PI_TIMER_SRC_FLL);
    pi_fll_ioctl(PI_FREQ_DOMAIN_ALL, PI_FLL_IOCTL_FULL_DCO_OPEN_LOOP_SET, 0);
    op_mode = 0;
}
else // From open loop, going into close loop
{
    printf("Pass to close loop, need clk\n");
    pi_fll_ioctl(PI_FREQ_DOMAIN_ALL, PI_FLL_IOCTL_FULL_DCO_CLOSE_LOOP_SET, 0);
    pi_timer_ioctl(NULL, PI_TIMER_IOCTL_SYS_TIMER_SRC_SET, (void *) PI_TIMER_SRC_REF_CLK_FAST);
    op_mode = 1;
}