Senior Digital IC Verification Engineer

Context:

GreenWaves is a fabless semiconductor company founded in 2014 and based in Grenoble, France. We design and market ultra low power processors for energy constrained products such as hearables, wearables, IoT & medical monitoring products.

GreenWaves’ system-on-chips enable companies to develop and bring to market products with new to world features enabled by state of the art machine learning and digital signal processing techniques. Our leading edge development tools enable audio and machine learning developers to productively harness the power of GAP processors.

GreenWaves GAP9 processor powers features such as neural network based noise removal and adaptive noise cancellation, multi-channel spatial sound and listening enhancement technologies in next generation earbuds and headphones with market leading energy efficiency.

As a growing, talented and highly multicultural team with sharp personalities, we are proud of what we do and how we do it. Our non-hierarchical culture means living our core values: ownership, collaboration, agility, dedication to customers and engagement. We believe that work is more than just a to-do list. You are empowered to build a leading company and to share its success!

We are looking for talented, enthusiastic, and committed people to be a part of our GreenWaves family.

Responsibilities:

We are looking for an experienced integrated circuit verification engineer to reinforce our team. As a member of the IC team, you will actively contribute to the verification of our next generations of chips:

  • Continuous improvement of verification strategy and environments: setup of good practices, flow flexibility and reuse strategy, continuous integration/non-regression procedures, in-house vs. 3rd party VIPs, test automation, methodology for coverage assessment, LP-oriented verification, etc.
  • Contribution to verification plans for IPs, subsystems and full chips, alongside SoC architects and designers: list of features, test strategy (IP-level vs. top-level, RTL vs. netlist vs. PG simulations), target coverage, tests scenarios and conformity matrix
  • Setup of testbenches (SystemVerilog/UVM) at IP, subsystem and/or top chip levels, for RTL or netlist; implementation of individual tests, analysis of results and bug reporting
  • Interfacing with SDK team for embedded SW developments required for verification
  • Interfacing with IC designer for analysis and fixing of bugs
  • Associated documentation and reports

Required skills:

  • Command of ASIC verification methodologies and techniques, including setting up UVM environments and automated flows
  • Expert in RTL and netlist simulation and debug using EDA tools (e.g. Questasim, Xcelium)
  • Knowledge of usual EDA scripting languages (TCL, Bash, Makefile)
  • Familiarity with versioning/revision control systems (git)
  • Pragmatism, liking for debug and problem solving, proactivity in building proposals (technical, organizational, priorities, etc.)
  • Work comfortably in an international environment, exchanging by email, telephone or video call
  • Good level in English, for daily communication with colleagues and partners

Desired skills:

  • Previous experience in verification of complex MCU, with a significant number of power and clock domains
  • RTL static checks (lint, CDC, LP checks)
  • Power and performance assessment verification
  • Skills in corner case-driven, coverage-driven and possibly formal verification
  • Knowledge of C programming in embedded environments
  • Python programming
Job Type: Full time (CDI)
Job Category: Engineering
Job Location: Grenoble. France (Alsace-Lorraine near train/tram)
Remuneration: Competetive compensation and stock option plan

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