|Senior ASIC Verification Engineer

Senior ASIC Verification Engineer

Context:

Greenwaves Technologies is a 5-year-old fabless semiconductor startup established in Grenoble, France. Our first product GAP8 is the world’s first IoT Application Processor armed with 8+1 RISC-V based cores and a high performance HW convolution engine. It is a simple yet very sophisticated unique processor architecture, which delivers an energy efficiency that is 20x better than the state-of-the-art, opening a large range of battery powered applications. Examples of applications are people counting, keyword spotting, combined with beamforming, object recognition, face detection and vibration analysis. GAP8 is especially effective on machine learning inference algorithms (CNN, SVM, Bayesian, Boosting, Cepstral analysis). Yet, GAP8 is by and large programmed just like a regular MCU.

Our technology is very much ahead of the state-of-art, and our chip is just about to prove its revolutionary potential on a wide open global market. For a team, it is a very motivating challenge that each of us could be part of in proportion to one’s own enthusiasm at work. As a growing and highly multicultural team with sharp personalities, Greenwaves Technologies is very proud of its specific collaborative management style. The company is and will be what we each of us make of it, as we experience every day, and we are looking for talented, enthusiastic, curious and committed people, who will be ready to bring their energy and skills for a significant contribution to the success of the company’s project.

Responsibilities:

As a member of the circuit design team, you will actively contribute to the verification of our next generations of chips:

  • Continuous improvement of verification environments: flow flexibility and reuse strategy, reuse enablement of in-house verification IPs, automation of tests and non-regression procedures, RTL vs. netlist, pgpin, etc.;
  • Elaboration/update of verification plan in relation with SoC architects and designers: features to be tested, test strategy, target coverage, tests scenarios and conformity matrix;
  • Setup of testbenches (SystemVerilog/UVM) at IP, subsystem and/or top chip levels, at RTL or netlist level, implementation of individual tests, analysis of results and report of encountered bugs;
  • Interfacing with software team for specific embedded SW developments required for test;
  • Interfacing with the design team for analysis and fixing of bugs;
  • Associated documentation.

Required skills:

Technical:

  • Command of ASIC verification methods and techniques, including setting up UVM environments and automated flows;
  • Skills in corner case-driven, coverage-driven and possibly formal verification;
  • RTL simulation and debug using EDA tools (e.g. Questasim, Xcelium);
  • Knowledge of usual EDA scripting languages (TCL, Bash, Makefile);
  • C programming in embedded environments;
  • Familiarity with versioning/revision control systems.

Non-technical:

  • Proactivity in building proposals (technical, organizational, priorities, etc.) and sharing them with fellow team members;
  • Strong team spirit and communication abilities, ability to convince;
  • Liking for debug and problem solving;
  • Good level of spoken and written English, to be used daily to communicate with colleagues and international partners;
  • Organizational skills;
  • Ability to work autonomously and proactively on assigned tasks.

Desired skills:

  • Command of UVM-based verification and setup of complex UVM testbenches;
  • Skills in power and performance verification;
  • Python programming;
  • Knowledge of RTL static checks (lint, CDC, power checks…) is a plus;
  • Git proficiency;
  • Knowledge of the overall ASIC design flow, at least at a high level;

Expected background:

  • Master Degree or plus with a specialization in microelectronics;
  • A first experience in RTL verification using UVM methodology is mandatory;
  • Experience in other parts of ASIC design flow is a plus: design, RTL checks, synthesis, equivalence checking, etc.
Job Category: Engineering
Job Type: Full time (CDI)
Job Location: Grenoble. France (Alsace-Lorraine near train/tram)
Remuneration: Competitive compensation and stock option plan

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2019-12-20T14:56:59+00:00