|RTL Designer (ASIC) with strong microprocessor background

RTL Designer (ASIC)
with strong microprocessor background


Greenwaves Technologies is a 5-year-old fabless semiconductor startup established in Grenoble, France. Our first product GAP8 is the world’s first IoT Application Processor armed with 8+1 RISC-V based cores and a high performance HW convolution engine. It is a simple yet very sophisticated unique processor architecture, which delivers an energy efficiency that is 20x better than the state-of-the-art, opening a large range of battery powered applications. Examples of applications are people counting, keyword spotting, combined with beamforming, object recognition, face detection and vibration analysis. GAP8 is especially effective on machine learning inference algorithms (CNN, SVM, Bayesian, Boosting, Cepstral analysis). Yet, GAP8 is by and large programmed just like a regular MCU.

Our technology is very much ahead of the state-of-art, and our chip is just about to prove its revolutionary potential on a wide open global market. For a team, it is a very motivating challenge that each of us can be part of in proportion to one’s own enthusiasm at work. As a growing and highly multicultural team with sharp personalities, Greenwaves Technologies is very proud of its specific collaborative management style. The company is and will be what each of us make of it, as we experience every day, and we are looking for talented, enthusiastic, curious and committed people, who will be ready to bring their energy and skills for a significant contribution to the success of the company’s project.


As a member of the circuit design team, you will actively contribute to the evolution of CPU cores and closely linked IPs (e.g. synchronization & interrupt management) for the next generations of chips:

  • Specification of new features to be supported (e.g. dual issue, new inter-CPU synchronization schemes, etc.), in relation with SoC architects and software teams, using high level models to evaluate the gains, where appropriate;
  • Definition of the required microarchitecture updates or new IPs to implement these new features;
  • Corresponding RTL (SystemVerilog) design;
  • Performance assessment though SDC constraints and synthesis trials, and through simulation at CPU subsystem-level or possibly at chip-level, in collaboration with verification and software teams;
  • Interfacing with the verification team to elaborate verification plan and analyse encountered bugs;
  • Interfacing with the physical implementation team to optimize RTL based on post place & route implementation results;
  • Associated documentation.

Required skills:


  • Command of CPU/DSP core microarchitecture principles (RISC family) and their optimisation: fetching strategies, datapath, interrupt management, …
  • Familiarity with low power design techniques and methodologies;
  • Good knowledge of (synthesizable) Verilog and/or SystemVerilog;
  • Knowledge of the overall ASIC design flow, at least at a high level;
  • RTL simulation and debug using EDA tools (e.g. Questasim, Xcelium);
  • Knowledge of usual EDA scripting languages (TCL, Bash, Makefile);
  • Timing constraints (SDC);
  • Familiarity with versioning/revision control systems.


  • Good level of spoken and written English, to be used daily to communicate with colleagues and international partners;
  • Ability to think outside the box to propose innovative technical solutions;
  • Organizational skills, rigor and ability to precisely report and document accomplished work;
  • Strong team spirit and communication abilities;
  • Ability to work autonomously and proactively.

Desired skills:

  • Knowledge of RISC-V ISA;
  • Knowledge of CPF and/or UPF formats;
  • Git proficiency;
  • Knowledge of verification techniques (e.g. UVM) is a plus;
  • C programming in embedded environments.

Expected background:

  • Master Degree or more with a specialization in microelectronics;
  • Significant experience in ASIC RTL design of complex programmable cores, preferably RISC processors, if possible for an ultra low-power target;
  • Experience in other parts of ASIC design flow is a plus: RTL checks, verification, backend, timing analysis, etc.

Job Type: Full time (CDI)
Job Category: Engineering
Job Location: Grenoble. France (Alsace-Lorraine near train/tram)

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