|SoC IP Design and Verification

SoC IP Design and Verification

Job Number: I1907

We are actively participating in two Open Source projects that provide some of the components in GAP8’s design, the RISC-V Instruction Set Architecture (ISA) and Parallel Ultra Low Power (PULP) projects. The target of this internship is mainly to design and maintain the IP micro-DMA (uDMA) which is responsible for communication with peripherals.


  • Help in next processor uDMA IP design and verification, with three steps:
    • Research in the flow and development methodologies
    • Investigation and development of methods to evaluate coverage of test cases
    • Complete the development of efficient test cases to cover main part of the Verification.
  • Elaborate documentation for uDMA peripheral IPs

Required skills:

  • Master Degree or plus in Electrical Engineering or Computer Engineering
  • More than 2 to 5 years experience in ASIC design or verification
  • Knowledge of Verilog and/or System Verilog. UVM is a plus. SV object-oriented and TB structuring knowledge would be nice.
  • Knowledge in software programming: C language is a must. Bash, TCL, Python would be appreciated.
  • Passionate about debugging and strong problem solving
  • Ability to work autonomously and proactively on tasks
  • Work comfortably in an international environment, exchanging by email, message, telephone or conf-calls: Fluency in English
  • is necessary.
  • Strong team spirit and communication, happy to collaborate and share with colleagues, even remotely.

Bonus skills:

  • Experiences in ASIC synthesis, Static timing analysis, equivalence checking, low power architecture, multi clock domain architecture
  • Signal processing (Image, voice, audio, vibration) experience

Job Category: Engineering
Job Type: Internship (6 Months)
Job Location: Grenoble. France (Alsace-Lorraine near train/tram)

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