|ASIC Front-end Designer

ASIC Front-end Designer

Greenwaves Technologies is a 5-year-old fabless semiconductor startup established in Grenoble, France. Our first product GAP8 is the world’s first IoT Application Processor armed with 8+1 RISC-V based cores and a high performance HW convolution engine. It is a simple yet very sophisticated unique processor architecture, which delivers an energy efficiency that is 20x better than the state-of-the-art, opening a large range of battery powered applications. Examples of applications are people counting, keyword spotting, combined with beamforming, object recognition, face detection and vibration analysis. GAP8 is especially effective on machine learning inference algorithms (CNN, SVM, Bayesian, Boosting, Cepstral analysis). Yet, GAP8 is by and large programmed just like a regular MCU.

Our technology is very much ahead of the state-of-art, and our chip is just about to prove its revolutionary potential on a wide open global market. For a team, it is a very motivating challenge that each of us could be part of in proportion to one’s own enthusiasm at work. As a growing and highly multicultural team with sharp personalities, Greenwaves Technologies is very proud of its specific collaborative management style. The company is and will be what we each of us make of it, as we experience every day, and we are looking for talented, enthusiastic, curious and committed people, who will be ready to bring their energy and skills for a significant contribution to the success of the company’s project.

Responsibilities:

As a member of the circuit design team, you will actively contribute to the design of our next generations of chips, through various front-end design tasks which may include:

  • IP specification in relation with SoC architects and software teams;
  • RTL (SystemVerilog) design of new IPs and/or update of existing IPs;
  • RTL assembly at subsystem and top chip levels;
  • Timing constraints and associated synthesis trials;
  • Update and improvement of the design flow: synthesis, RTL checks (lint, CDC, power checks…), equivalence checking, STA, etc.;
  • Interfacing with the verification team to elaborate verification plan and analyse encountered bugs;
  • Interfacing with the physical implementation team to optimize RTL based on implementation results;
  • Associated documentation.

Required skills:

Technical:

  • Good knowledge of (synthesizable) Verilog and/or SystemVerilog;
  • Knowledge of the overall ASIC design flow, at least at a high level;
  • RTL simulation and debug using EDA tools (e.g. Questasim, Xcelium);
  • Knowledge of usual EDA scripting languages (TCL, Bash, Makefile);
  • Timing constraints (SDC);
  • Familiarity with versioning/revision control systems.

Non-technical:

  • Good level of spoken and written English, to be used daily to communicate with colleagues and international partners;
  • Liking for debug and problem solving
  • Organizational skills;
  • Strong team spirit and communication abilities;
  • Ability to work autonomously and proactively on assigned tasks.

Desired skills:

  • Knowledge of CPF and/or UPF formats;
  • Low power design techniques and methodologies;
  • Git proficiency;
  • Knowledge of verification techniques (e.g. UVM) is a plus;
  • C programming in embedded environments.

Expected background:

  • Master Degree or plus with a specialization in microelectronics;
  • A first experience in ASIC RTL design is required, desirably including synthesis of designed blocks;
  • Experience in other parts of ASIC design flow is a plus: verification, backend, timing analysis, etc.
Job Category: Engineering
Job Type: Full time (CDI)
Job Location: Grenoble. France (Alsace-Lorraine near train/tram)
Remuneration: Competitive compensation and stock option plan

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2019-09-27T18:22:13+00:00