- GAPMod comes in 2 variants: - one that bears a HyperBus Flash+RAM MCM (GAPMod1.x) - one that bears a Quad-SPI Flash and Quad-SPI RAM (GAPMod2.x) HyperBus memory provides more bandwidth but is more expensive and possibly less easy to source than QSPI memories. ** File GAPMod_xxx_IO_Definition.xlsx documents the role of each GAPMod I/O and how they relate to GAP8 ** - The STM8 visible in the GAPMod1.2 database is there for legacy reasons. It is not assembled on the actual GAPMod1.2 module (see photo, Fig.2 of GAPMod manual: GAPMod_1.2.Documentation_Rel-2.2.pdf). Therefore it should be ignored when importing the GAPMod design into a larger board design. - A level shifter is also present on UART signals. When looking at importing the GAPMod design into a larger board design, in some cases this level shifting stage will be redundant -- depending on the board design into which the GAPMod-like macro would be imported.