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Thermal IR GAPPoc (GAPPoc B 2.x) Design Information
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> The schematic of GAPOC B 2.x includes a fair amount of comments to explain some of the choices that were made and to highlight places where further optimizations (or different choices) could be made in a final product.

> The current design of GAPOC B 2.x includes a number of provisions for debug/bring-up and for coping with specific POC needs; at least some of them could probably be optimized out in a prodution context -- for example, test points and current sense resistors, 0R/NC resistors to enable some assembly variants, expansion connectors...

> The design instantiates a "GAPMod" core module, which is a small SMT daughter board that essentially bears our GAP8 chip, Flash and RAM memories, crystal plus some passives.
A production board would likely consider this GAPMod as a macro to import (flatten) into the overall design.
GAPMod comes in 2 variants:
- one that bears a HyperBus Flash+RAM MCM (GAPMod1.x)
- one that bears a Quad-SPI Flash and Quad-SPI RAM (GAPMod2.x)
The former option provides more bandwidth but is more expensive and possibly less easy to source than the second option.
Initial GAPPoc boards have used the HyperBus option, however GAPPoc B 2.4 is fitted the QSPI option (GAPMod2.x).

** File GAPMod_xxx_IO_Definition.xlsx documents the role of each GAPMod I/O and how they relate to GAP8 **